JPH065646A - Resin sealed semiconductor device and manufacture thereof - Google Patents
Resin sealed semiconductor device and manufacture thereofInfo
- Publication number
- JPH065646A JPH065646A JP4159288A JP15928892A JPH065646A JP H065646 A JPH065646 A JP H065646A JP 4159288 A JP4159288 A JP 4159288A JP 15928892 A JP15928892 A JP 15928892A JP H065646 A JPH065646 A JP H065646A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- integrated circuit
- insulating plate
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プラスチックパッケー
ジ等樹脂で封止された樹脂封止半導体装置およびその製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device encapsulated with resin such as a plastic package and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、この種の樹脂封止半導体装置は、
搭載される半導体ペレットの大型化に伴い、パッケージ
側端と半導体ペレット取付部であるタブとの間の寸法が
一段と狭くなる傾向にある。これは、半導体ペレットが
大きくなっているのに、これを収納するパッケージのサ
イズが規格化されているため、大きくすることができな
いことに起因する。その結果、外部端子であるリードの
うち、パッケージを形成する樹脂に埋設される長さが、
その構造上短い、いわゆる短リードにおいては、その接
着強度が一段と小さくなるため、パッケージから抜け易
く、また、リード折曲成形時に、リードと樹脂との間の
剥がれが生じ易くなると考えられる。そのため、電気的
導通不良、または耐湿性低下等の半導体装置の信頼性低
下を来し易くなる。2. Description of the Related Art Conventionally, this type of resin-sealed semiconductor device has been
As the size of the mounted semiconductor pellet increases, the size between the package side end and the tab that is the semiconductor pellet mounting portion tends to become narrower. This is because the size of the package that accommodates the semiconductor pellets is standardized even though the size of the semiconductor pellets is large, and therefore the size cannot be increased. As a result, of the leads that are external terminals, the length embedded in the resin that forms the package is
It is considered that in a so-called short lead, which has a short structure, its adhesive strength is further reduced, so that the lead is easily pulled out from the package, and peeling between the lead and the resin is likely to occur during lead bending. Therefore, the reliability of the semiconductor device is likely to be deteriorated, such as poor electrical continuity or reduced moisture resistance.
【０００３】そこで、例えば、特開昭６１−２１８１３
９号公報に開示されているように、半導体ペレットの非
回路形成面に、ボンディングパットに被らない大きさの
絶縁シートを接着し、この絶縁シート上面には、内部リ
ードを延在することにより、この内部リードとパッケー
ジ形成樹脂との接着力を大幅に向上させ、大型半導体ペ
レットを搭載する場合でも、パッケージ形成樹脂からの
リード抜けを防止できる構造が示されている。Therefore, for example, Japanese Patent Laid-Open No. 61-21813.
As disclosed in Japanese Laid-Open Patent Publication No. 9-331, an insulating sheet having a size that does not cover the bonding pad is adhered to the non-circuit forming surface of the semiconductor pellet, and an internal lead is extended on the upper surface of the insulating sheet. , A structure capable of significantly improving the adhesive force between the internal lead and the package-forming resin and preventing the lead from coming off from the package-forming resin even when a large semiconductor pellet is mounted.
【０００４】図８は従来の樹脂封止半導体装置を示す平
面図であり、図９はそのＡ１−Ａ２断面側面図である。
図において、１は集積回路チップ、２は図１０に示すよ
うに、両面に接着剤３ａ、３ｂが塗布された、例えばポ
リイミド樹脂の絶縁シートであり、この集積回路チップ
１上に接着固定されている。４は半導体集積回路を形成
していない面である非回路形成主面に沿って延在された
リードであり、絶縁シート２に接着固定されている。５
は図１０に示すように、集積回路チップ１のボンディン
グパット６と絶縁シート２上に貼付けられたリード４と
を電気的に接続するＡｌ線などのワイヤ、７はモールド
樹脂である。FIG. 8 is a plan view showing a conventional resin-sealed semiconductor device, and FIG. 9 is a side view of the A1-A2 cross section.
In the figure, reference numeral 1 is an integrated circuit chip, and 2 is an insulating sheet made of, for example, a polyimide resin with adhesives 3a and 3b applied on both sides, as shown in FIG. There is. Reference numeral 4 denotes a lead extending along a non-circuit forming main surface, which is a surface on which the semiconductor integrated circuit is not formed, and is fixed to the insulating sheet 2 by adhesion. 5
As shown in FIG. 10, a wire such as an Al wire for electrically connecting the bonding pad 6 of the integrated circuit chip 1 and the lead 4 attached on the insulating sheet 2 and 7 are mold resins.
【０００５】この構成による樹脂封止半導体装置では、
リード４は半導体集積回路を形成していない面である非
回路形成主面に沿って延在され、絶縁シート２の接着剤
３ａにより接着されて固定する。In the resin-sealed semiconductor device having this structure,
The leads 4 extend along the non-circuit forming main surface, which is the surface on which the semiconductor integrated circuit is not formed, and are bonded and fixed by the adhesive 3a of the insulating sheet 2.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記構
成の装置では、ワイヤボンディングの際、図１１に示す
ように、キャピラリ８がリード４に押し当てるとき、キ
ャピラリ８の超音波振動９を絶縁シート２が吸収してし
まう。このため、図１２に示すように、絶縁シート２が
キャピラリ８の力を緩衝し、リード４が沈み込み、キャ
ピラリ８がバウンドしてしまう。このため、ワイヤ５が
断線を起す。また、ワイヤボンディングされていても、
ワイヤの接着強度が通常より低いため、信頼性試験の温
度サイクルのとき、ワイヤが剥がれるなどという問題点
があった。However, in the device having the above structure, when the capillary 8 is pressed against the lead 4 during wire bonding, the ultrasonic vibration 9 of the capillary 8 is applied to the insulating sheet 2 as shown in FIG. Will be absorbed. Therefore, as shown in FIG. 12, the insulating sheet 2 buffers the force of the capillary 8, the lead 4 sinks, and the capillary 8 bounces. Therefore, the wire 5 breaks. Also, even if it is wire bonded,
Since the adhesive strength of the wire is lower than usual, there is a problem that the wire is peeled off during the temperature cycle of the reliability test.
【０００７】本発明は、以上述べたワイヤボンディング
のワイヤの断線と信頼性試験の温度サイクル試験の断線
という問題点を除去するため、集積回路チップと内部リ
ードの間に絶縁板を設けて接着し、ワイヤボンディング
性に優れた樹脂封止半導体装置およびその製造方法を提
供することを目的とする。In order to eliminate the above-mentioned problems of wire breakage in wire bonding and temperature breakage test in the reliability test, an insulating plate is provided between the integrated circuit chip and the internal lead for adhesion. An object of the present invention is to provide a resin-encapsulated semiconductor device having excellent wire bondability and a method for manufacturing the same.
【０００８】[0008]
【課題を解決するための手段】本発明に係る樹脂封止半
導体装置は、集積回路チップと内部リードの間に、ボン
ディングパットに被らない大きさの絶縁板を設け、この
絶縁板の一方の面に集積回路チップを接着し、他方の面
に内部リードを接着した構造を設けたものである。In a resin-sealed semiconductor device according to the present invention, an insulating plate having a size not covered by a bonding pad is provided between an integrated circuit chip and an internal lead, and one of the insulating plates is provided. A structure is provided in which an integrated circuit chip is bonded to one surface and internal leads are bonded to the other surface.
【０００９】また、本発明に係る樹脂封止半導体装置の
製造方法は、集積回路チップを絶縁板の一方の面に接着
する第１の工程と、内部リードを絶縁板の他方の面に接
着する第２の工程と、絶縁板の他方の面に形成したキャ
ピティ中に第２集積回路チップを接着する第３の工程と
を設けたものである。Further, in the method of manufacturing the resin-sealed semiconductor device according to the present invention, the first step of adhering the integrated circuit chip to one surface of the insulating plate and the inner lead being adhered to the other surface of the insulating plate. The second step and the third step of adhering the second integrated circuit chip to the capacity formed on the other surface of the insulating plate are provided.
【００１０】[0010]
【作用】本発明は内部リードが絶縁板に接着するため、
接着強度が上り、ワイヤボンディング性を向上すること
ができる。In the present invention, since the inner lead is adhered to the insulating plate,
The adhesive strength is increased, and the wire bondability can be improved.
【００１１】[0011]
【実施例】図１は本発明に係る樹脂封止半導体装置の一
実施例を示す平面図であり、図２はそのＢ１−Ｂ２断面
側面図である。図において、１０はガラス、ポリイミ
ド、セラミックなどの材質を使用した絶縁板、１１ａお
よび１１ｂはこの絶縁板１０の両面に塗布した接着剤ま
たはこの絶縁板１０の両面にそれぞれ接着した接着シー
トである。1 is a plan view showing an embodiment of a resin-encapsulated semiconductor device according to the present invention, and FIG. 2 is a side view of a B1-B2 section thereof. In the figure, 10 is an insulating plate made of a material such as glass, polyimide, or ceramic, and 11a and 11b are adhesives applied to both sides of the insulating plate 10 or adhesive sheets adhered to both sides of the insulating plate 10, respectively.
【００１２】この構成による樹脂封止半導体装置では、
搭載される集積回路チップ１のボンディングパット６を
除いた非回路主面に、内部リード４があり、その金属メ
ッキ部分と集積回路チップ１の配列形成されたボンディ
ングパット６まで、ワイヤ５を延長し、接続する。ま
た、内部リード４は図３に示すように、接着剤または接
着シート１１ａによって絶縁板１０に接着固定される。
このため、ワイヤボンディング時、図示せぬキャピラリ
が内部リード４に押し当てるとき、キャピラリの超音波
振動は絶縁板１０に吸収されることがなくなり、しかも
図示せぬキャピラリの力を緩衝することがないので、ワ
イヤ５の断線をなくすことができる。しかも、ワイヤ５
の接着強度を充分にとれるため、信頼性試験の温度サイ
クルでワイヤの剥れをなくすことができる。In the resin-sealed semiconductor device having this structure,
There is an internal lead 4 on the main surface of the integrated circuit chip 1 excluding the bonding pad 6 except for the bonding pad 6, and the wire 5 is extended to the bonding pad 6 where the metal plated portion and the integrated circuit chip 1 are formed in an array. ,Connecting. Further, as shown in FIG. 3, the inner lead 4 is adhesively fixed to the insulating plate 10 with an adhesive or an adhesive sheet 11a.
Therefore, during wire bonding, when the capillary (not shown) is pressed against the inner lead 4, the ultrasonic vibration of the capillary is not absorbed by the insulating plate 10, and the force of the capillary (not shown) is not buffered. Therefore, disconnection of the wire 5 can be eliminated. Moreover, wire 5
Since the adhesive strength of 1 can be sufficiently obtained, the wire can be prevented from peeling off in the temperature cycle of the reliability test.
【００１３】図４は本発明に係る樹脂封止半導体装置の
他の実施例を示す平面図である。図において、１２はパ
ターン１３を形成し、このパターン１３上にレジストを
コーティングしたガラエポ、ポリイミド、セラミックな
どの材質で作られた絶縁板、１４はこの絶縁板１２に搭
載した第２集積回路チップ、１５はパターン１３に接続
したボンディングパットである。FIG. 4 is a plan view showing another embodiment of the resin-sealed semiconductor device according to the present invention. In the figure, reference numeral 12 denotes a pattern 13, and an insulating plate made of a material such as glass epoxy, polyimide, or ceramic, which is coated with a resist on the pattern 13, 14 is a second integrated circuit chip mounted on the insulating plate 12, Reference numeral 15 is a bonding pad connected to the pattern 13.
【００１４】この構成による樹脂封止半導体装置では、
内部リード４と絶縁板１２は接着剤または接着シート１
１ａにより接着しており、ワイヤボンディングされる部
分にはかからないようになっている。そして、図６に示
すように、集積回路チップ１から内部リード４の表面に
ワイヤボンドを行い、さらにこの内部リード４からパタ
ーン１３のボンディングパット１５にワイヤボンドを行
い、さらに、このボンディングパット１５から第２集積
回路チップ１４にワイヤボンドする。このようなワイヤ
ボンディング時、図示せぬキャピラリが内部リード４に
押し当てるとき、キャピラリの超音波振動は絶縁板１２
に吸収されることがなくなり、しかも図示せぬキャピラ
リの力を緩衝することがないので、ワイヤ５の断線をな
くすことができる。しかも、ワイヤ５の接着強度を充分
にとれるため、信頼性試験の温度サイクルでワイヤの剥
れをなくすことができる。In the resin-sealed semiconductor device having this structure,
The inner lead 4 and the insulating plate 12 are an adhesive or an adhesive sheet 1.
It is bonded by 1a so that it does not cover the wire-bonded portion. Then, as shown in FIG. 6, wire bonding is performed from the integrated circuit chip 1 to the surface of the internal lead 4, and further wire bonding is performed from the internal lead 4 to the bonding pad 15 of the pattern 13, and further from the bonding pad 15. Wire bond to the second integrated circuit chip 14. During such wire bonding, when a capillary (not shown) is pressed against the inner lead 4, ultrasonic vibration of the capillary causes insulation plate 12
Is not absorbed and the force of a capillary (not shown) is not buffered, so that disconnection of the wire 5 can be eliminated. Moreover, since the bonding strength of the wire 5 can be sufficiently obtained, the wire can be prevented from peeling off in the temperature cycle of the reliability test.
【００１５】なお、上記第２集積回路チップ１４は絶縁
板１２にキャビティがあり、エポキシ系接着剤、ポリイ
ミド系接着剤で接着できるようになっている。The second integrated circuit chip 14 has a cavity in the insulating plate 12 and can be bonded with an epoxy adhesive or a polyimide adhesive.
【００１６】図７は本発明に係る樹脂封止半導体装置の
製造方法の一実施例を示す断面図であり、その製造工程
について説明すると、まず、図７（Ａ）に示すように、
絶縁板１２に接着剤または接着シート１１ａにより内部
リード４を接着する。この絶縁板１２には、あらかじ
め、ボンディングパットにかからない形状で接着剤また
は接着シートがついており、内部リード４と絶縁板１２
を温度１２０℃〜１５０℃で熱圧着することによって、
接着剤が溶け、接着固定することができる。そして、図
７（Ｂ）に示すように、絶縁板１２の下面の接着剤また
は接着シート１１ｂと集積回路チップ１のボンディング
パットの被さらない部分とで同様な熱圧着する。そし
て、図７（Ｃ）に示すように、絶縁板１２の上面にある
キャビティの中にエポキシ系接着剤、ポリイミド系接着
剤または半田ペーストを塗布する。そして、図７（Ｄ）
に示すように、このキャビティの中に第２集積回路チッ
プ１４をボンディングし、１５０℃〜１８０℃の恒温槽
の中に入れて硬化させるが、半田ペーストの場合には、
１８５℃〜２２０℃の熱（半田ゴテまたは赤外線など）
によって接着させる。ただし、この場合、半導体集積回
路ではなく、コンデンサ、抵抗など半田接合をする電子
部品である。そして、図７（Ｅ）に示すように、ワイヤ
ボンドを第２集積回路チップ１４と絶縁板１２のボンデ
ィングパット１５、このボンディングパット１５から内
部リード４、この内部リード４から集積回路チップ１へ
それぞれワイヤボンドする。そして、以降の製造工程に
ついては従来の通り進めるものである。FIG. 7 is a sectional view showing an embodiment of a method of manufacturing a resin-sealed semiconductor device according to the present invention. The manufacturing process will be described. First, as shown in FIG. 7 (A),
The inner leads 4 are adhered to the insulating plate 12 with an adhesive or an adhesive sheet 11a. The insulating plate 12 is preliminarily provided with an adhesive or an adhesive sheet in a shape that does not cover the bonding pad.
By thermocompression bonding at a temperature of 120 ° C to 150 ° C,
The adhesive melts and can be adhesively fixed. Then, as shown in FIG. 7B, the same thermocompression bonding is performed with the adhesive or the adhesive sheet 11b on the lower surface of the insulating plate 12 and the portion of the integrated circuit chip 1 which is not covered with the bonding pad. Then, as shown in FIG. 7C, an epoxy adhesive, a polyimide adhesive or a solder paste is applied into the cavity on the upper surface of the insulating plate 12. And FIG. 7 (D)
As shown in FIG. 3, the second integrated circuit chip 14 is bonded in this cavity, and is put in a constant temperature bath at 150 ° C. to 180 ° C. to be hardened.
Heat of 185 ℃ -220 ℃ (Soldering iron or infrared)
Adhere by. However, in this case, it is not a semiconductor integrated circuit, but an electronic component such as a capacitor or a resistor for soldering. Then, as shown in FIG. 7 (E), wire bonding is performed on the bonding pad 15 between the second integrated circuit chip 14 and the insulating plate 12, the bonding pad 15 to the internal lead 4, and the internal lead 4 to the integrated circuit chip 1, respectively. Wire bond. Then, the subsequent manufacturing process proceeds as usual.
【００１７】なお、上記絶縁板１０および１２上に、回
路を形成することができ、内部リードを接続したときに
は集積度を上げることができることはもちろんである。It goes without saying that a circuit can be formed on the insulating plates 10 and 12 and the degree of integration can be increased when the internal leads are connected.
【００１８】[0018]
【発明の効果】以上詳細に説明したように、本発明に係
る樹脂封止半導体装置およびその製造方法によれば、集
積回路チップと内部リード間に絶縁板を介在させて接着
固定するようにしたので、内部リードのワイヤボンド強
度が向上し、ワイヤの断線や信頼性試験の際の断線を防
ぐことができ、安定したワイヤボンドを行なうことがで
きるなどの効果がある。As described above in detail, according to the resin-encapsulated semiconductor device and the method of manufacturing the same according to the present invention, the insulating plate is interposed between the integrated circuit chip and the internal lead so as to be adhesively fixed. Therefore, the wire bond strength of the internal lead is improved, wire breakage and wire breakage during the reliability test can be prevented, and stable wire bond can be performed.
【図１】本発明に係る樹脂封止半導体装置の一実施例を
示す平面図である。FIG. 1 is a plan view showing an embodiment of a resin-sealed semiconductor device according to the present invention.
【図２】図１のＢ１−Ｂ２断面側面図である。FIG. 2 is a side view of a B1-B2 cross section of FIG.
【図３】図２のＢ部の拡大図である。FIG. 3 is an enlarged view of part B in FIG.
【図４】本発明に係る樹脂封止半導体装置の他の実施例
を示す平面図である。FIG. 4 is a plan view showing another embodiment of the resin-sealed semiconductor device according to the present invention.
【図５】図４のＣ１−Ｃ２断面側面図である。5 is a side view of a C1-C2 cross section of FIG. 4;
【図６】図５のＣ部の拡大図である。FIG. 6 is an enlarged view of a C portion of FIG.
【図７】本発明に係る樹脂封止半導体装置の製造方法の
一実施例を工程順に示す断面図である。FIG. 7 is a cross-sectional view showing an example of a method of manufacturing a resin-encapsulated semiconductor device according to the present invention in the order of steps.
【図８】従来の樹脂封止半導体装置を示す平面図であ
る。FIG. 8 is a plan view showing a conventional resin-sealed semiconductor device.
【図９】図８のＡ１−Ａ２断面側面図である。9 is a cross-sectional side view taken along the line A1-A2 of FIG.
【図１０】図９のＡ部の拡大図である。FIG. 10 is an enlarged view of part A in FIG.
【図１１】キャピラリの動作を説明する断面図である。FIG. 11 is a cross-sectional view illustrating the operation of the capillary.
【図１２】キャピラリの動作を説明する断面図である。FIG. 12 is a cross-sectional view illustrating the operation of the capillary.
【符号の説明】 １０，１２ 絶縁板 １１ａ，１１ｂ 接着シート １４ 第２集積回路チップ １５ ボンディングパット[Explanation of Codes] 10, 12 Insulating Plates 11a, 11b Adhesive Sheet 14 Second Integrated Circuit Chip 15 Bonding Pad
Claims (3)
チップと内部リード間に絶縁板を設け、この絶縁板の一
方の面に集積回路チップを接着し、他方の面に内部リー
ドを接着したことを特徴とする樹脂封止半導体装置。1. In a resin-sealed semiconductor device, an insulating plate is provided between an integrated circuit chip and an internal lead, the integrated circuit chip is bonded to one surface of the insulating plate, and the internal lead is bonded to the other surface. A resin-encapsulated semiconductor device comprising:
か、配線パターンおよび第２集積回路チップを接着した
ことを特徴とする請求項１記載の樹脂封止半導体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein an internal lead, a wiring pattern, and a second integrated circuit chip are bonded to the other surface of the insulating plate.
て、集積回路チップを絶縁板の一方の面に接着する第１
の工程と、内部リードを絶縁板の他方の面に接着する第
２の工程と、絶縁板の他方の面に形成したキャピティ中
に第２集積回路チップを接着する第３の工程と、第２集
積回路チップと絶縁板のボンディングパット、このボン
ディングパットから内部リード、この内部リードから集
積回路チップへそれぞれワイヤボンドする第４の工程と
を備えたことを特徴とする樹脂封止半導体装置の製造方
法。3. A method of manufacturing a resin-encapsulated semiconductor device, comprising: adhering an integrated circuit chip to one surface of an insulating plate.
The second step of adhering the inner lead to the other surface of the insulating plate, the third step of adhering the second integrated circuit chip in the capacity formed on the other surface of the insulating plate, and the second step. A method of manufacturing a resin-encapsulated semiconductor device, comprising: a bonding pad for an integrated circuit chip and an insulating plate; a fourth step for wire-bonding the bonding pad to an internal lead; .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4159288A JPH065646A (en) | 1992-06-18 | 1992-06-18 | Resin sealed semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4159288A JPH065646A (en) | 1992-06-18 | 1992-06-18 | Resin sealed semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH065646A true JPH065646A (en) | 1994-01-14 |
Family
ID=15690526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4159288A Pending JPH065646A (en) | 1992-06-18 | 1992-06-18 | Resin sealed semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065646A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9947770B2 (en) | 2007-04-03 | 2018-04-17 | Vishay-Siliconix | Self-aligned trench MOSFET and method of manufacture |
-
1992
- 1992-06-18 JP JP4159288A patent/JPH065646A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9947770B2 (en) | 2007-04-03 | 2018-04-17 | Vishay-Siliconix | Self-aligned trench MOSFET and method of manufacture |
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