JPH065609A - Bump forming method - Google Patents

Abstract

PURPOSE:To cut down plating time by a method wherein plating is conducted at high current density in the beginning, then the plating is continued while current density is being decreased gradually, and finally, the plating is conducted at a relatively low current density. CONSTITUTION:A 15mum thick plating is provided on an aperture part by a wet plating method at the initial plating temperature of 60 deg.C, and current density of 0.75A/cm<2> for plating time of 32 minutes using the plating solution of EEJA microfabrication Au 100 and also using a barrier metal 6 as a plating electrode. Subsequently, a plating operation is conducted and the plating of 2mum in thickness is formed in six minutes while current density is being lowered at the falling rate of 0.042mA/dm<2>/min. Finally, a bump 8' of 20mum height is formed by providing a 3mum thick plating by conducting a plating operation at the current density of 0.4A/cm<2> for 12 minutes. As a result, the plating time can be cut down by forming a bump on the aperture part of the resist pattern where the aperture is formed on the electrode part only.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bump suitable for mounting an element on an electrode portion of a semiconductor element formed in a large number on a wafer.

[0002]

2. Description of the Related Art As shown in FIG. 12, a large number of semiconductor elements 2 formed on a wafer 1 are divided by a cutting area 3.
As shown in FIG. 13, a wiring protective film 5 is formed other than the electrode portion 4. In the conventional method of forming bumps for mounting elements on the electrode portions 4, first, as shown in FIG. 14, a barrier metal 6 is deposited by sputtering on the entire surface of a wafer 1 on which a large number of semiconductor elements 2 are formed. After that, as shown in FIG. 15, a thick photosensitive resist 7 for straight bumps is applied to the entire surface. Next, as shown in FIG. 16, the photosensitive resist 7 is patterned by photolithography so that only the electrode portion 4 is opened. Next, as shown in FIG. 17, bumps 8 are formed in the openings by the wet plating method using the barrier metal 6 as a plating electrode. Next, as shown in FIG. 18, the photosensitive resist 7 is peeled off, and the wafer 1 is washed with pure water. Next, as shown in FIG. 19, a photosensitive resist 9 is applied on the entire surface, and the bumps 8 are covered by photolithography as shown in FIG.
The photosensitive resist 9 is patterned as shown in FIG. Next, the barrier metal 6 is formed by using the patterned photosensitive resist 9 as a mask to prevent the bumps 8 from being altered or dissolved.
The individual bumps 8 are electrically disconnected as shown in FIG. Next, as shown in FIG. 22, the photosensitive resist 9 covering the bumps 8 is peeled off. Then, bump annealing is performed to complete the formation of the bump 8.

By the way, in such a conventional bump forming method, as shown in FIG. 17, the barrier metal 6 is used as a plating electrode in a wet plating method in which the photosensitive resist 7 is patterned to open only the electrode portion 4. Therefore, when the bumps 8 were formed, the wet plating was performed at a constant current, so that the plating required a long time and the bump forming efficiency was poor. This is because if the current density of the wet plating is increased, the hardness of the bump, which is a plated product, increases, and when the bump and the lead terminal to be bonded to the bump are bonded, bonding failure occurs. Therefore, the wet plating must be performed at a constant current. Because there was not.

[0004]

Therefore, the present invention shortens the plating time when forming bumps by wet plating in the opening of the resist pattern in which only the electrode portion is opened.
Another object of the present invention is to provide a bump forming method capable of forming a plated portion having a hardness suitable for bonding with a lead terminal on a bump upper portion.

[0005]

The bump forming method of the present invention for solving the above-mentioned problems involves forming bumps by wet plating on a wafer on which a resist pattern for bump formation is formed in advance. It is characterized in that plating is first performed at a high current density, then plating is performed while gradually decreasing the current density, and finally plating is performed at a relatively low current density.

[0006]

As described above, in the bump forming method of the present invention, when the bumps are formed on the wafer on which the resist pattern for forming the bumps is previously formed by the wet plating, the plating is first performed at a high current density. Therefore, the plating height of the bump can be obtained in a short time, and since the plating is performed at a relatively low current density at the end, the hardness of the bump that grows at this time becomes low, and when bonding the bump and lead terminal , Less likely to cause defective bonding. From the first high current density plating to the last relatively low current density plating, the current density is gradually lowered to perform plating, so the stress on the lower bumps and upper bumps can be relieved, and the lead terminals and It is possible to prevent the bumps from being broken by the pressure applied at the time of bonding.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the bump forming method of the present invention will be described with reference to the drawings. First, as shown in FIG. 1, a barrier metal 6 (Ti1000Å from the lower layer) is formed on the entire surface of a wafer 1 on which a large number of semiconductor elements 2 are formed. , Pd3000Å) by sputtering, and then, as shown in FIG. 2, a thick film (thickness 23 μm) of photosensitive resist 7 for straight bumps was applied to the entire surface. Next, as shown in FIG. 3, a photosensitive resist 7 is formed by photolithography so that only the electrode portion 4 is opened.
Was patterned. Next, as shown in FIG. 4, using the barrier metal 6 as a plating electrode, a plating solution: EEJA Microfab Au 100 was used to perform wet plating first under the conditions of a plating temperature of 60 ° C., a current density of 0.75 A / dm ² , and a plating time of 32 minutes. The opening was plated with a height of 15 μm by the method. Continue to Figure 5
The current density was gradually decreased at a rate of 0.042 mA / dm ² / min as shown in FIG.
Finally, as shown in FIG. 6, a bump 8'having a height of 20 μm was formed by plating with a current density of 0.4 A / dm ² and a plating time of 12 minutes to a height of 3 μm. Next, as shown in FIG. 7, the photosensitive resist 7 was peeled off, and the wafer 1 was washed with pure water. Then, FIG.
As shown in FIG. 9, a photosensitive resist 9 was applied on the entire surface, and the photosensitive resist 9 was patterned by photolithography so as to cover the bumps 8'as shown in FIG. Next, the barrier metal 6 was etched as shown in FIG. 10 using the patterned photosensitive resist 9 as a mask to prevent the bumps 8'from being altered or dissolved, and the electrical short circuit of the individual bumps 8'was cut off. Then, as shown in FIG. 11, the photosensitive resist 9 covering the bumps 8'was peeled off. After that, bump annealing was performed at 250 ° C. for 30 minutes to complete the formation of the bump 8 ′.

On the other hand, the conventional bump forming method will be described with reference to the drawings. The steps shown in FIGS.
~ This is exactly the same as the steps up to FIG. Then, as shown in FIG. 17, using the barrier metal 6 as an electrode for plating and using the same plating solution as in the example: EEJA Microfab Au 100, the plating temperature was 60 ° C., the current density was 0.5 A / dm ² , and the plating time was 64.
Bumps 8 having a height of 20 μm were formed in the openings of the photosensitive resist 7 by the wet plating method under the condition of minutes. Then Figure 18 ~ Figure
The step of completing the formation of the bumps 8 by performing bump annealing at 22 ° C. for 30 minutes at 250 ° C. is the same as that of FIG.

When the hardness of the upper part of the bumps of the example and the conventional example formed as described above was measured, the bump 8 of the conventional example was HV85, whereas the bump 8'of the example was HV.
It was as low as V76. Further, it takes 64 minutes to form the bumps 8 having a height of 20 μm by wet plating in the above-mentioned conventional example, whereas it takes 50 minutes to form the bumps 8 ′ having a height of 20 μm by wet plating in the embodiment. , The bump formation time was shortened. However, when the lead terminals were bonded to the bumps of the example and the conventional example, 125 of the 50,000 bumps of the conventional example had a defective bonding, but the bump 8'of the example of the invention had a defective bonding of only 98 of the 50,000 bumps. Did not happen.

[0010]

As described above, according to the bump forming method of the present invention, it is possible to shorten the plating time for forming the bumps by wet plating on the openings of the resist pattern in which only the electrode portions are opened, so that the productivity is improved. . In addition, since the hardness of the upper part of the bump can be lowered, it is less likely that a bonding failure will occur when the lead terminal is bonded.

[Brief description of drawings]

FIG. 1 is a diagram showing a process of an embodiment of a bump forming method of the present invention.

FIG. 2 is a diagram showing steps of an embodiment of a bump forming method of the present invention.

FIG. 3 is a diagram showing steps of an embodiment of the bump forming method of the present invention.

FIG. 4 is a diagram showing steps of an embodiment of the bump forming method of the present invention.

FIG. 5 is a diagram showing steps of an embodiment of the bump forming method of the present invention.

FIG. 6 is a diagram showing steps of an embodiment of the bump forming method of the present invention.

FIG. 7 is a diagram showing steps of an embodiment of the bump forming method of the present invention.

FIG. 8 is a diagram showing steps of an embodiment of the bump forming method of the present invention.

FIG. 9 is a diagram showing steps of an embodiment of the bump forming method of the present invention.

FIG. 10 is a diagram showing a process of an embodiment of the bump forming method of the present invention.

FIG. 11 is a diagram showing steps of an embodiment of the bump forming method of the present invention.

FIG. 12 is a top view of a wafer on which a plurality of semiconductor elements are formed.

13 is an enlarged perspective view showing an electrode portion of a semiconductor element on the upper surface of the wafer of FIG.

FIG. 14 is a diagram showing steps of a conventional bump forming method.

FIG. 15 is a diagram showing steps of a conventional bump forming method.

FIG. 16 is a diagram showing steps of a conventional bump forming method.

FIG. 17 is a diagram showing steps of a conventional bump forming method.

FIG. 18 is a diagram showing steps of a conventional bump forming method.

FIG. 19 is a diagram showing steps of a conventional bump forming method.

FIG. 20 is a diagram showing steps of a conventional bump forming method.

FIG. 21 is a diagram showing steps of a conventional bump forming method.

FIG. 22 is a diagram showing steps of a conventional bump forming method.

[Explanation of symbols]

 1 Wafer 4 Electrode part 5 Wiring protective film 6 Barrier metal 7 Photosensitive resist 8'Bump 9 Photosensitive resist

Claims (1)

[Claims] 1. When forming bumps by wet plating on a wafer on which a resist pattern for bump formation has been formed in advance, first, plating is performed at a high current density,
Subsequently, the bump forming method is characterized in that plating is performed while gradually decreasing the current density, and finally plating is performed at a relatively low current density.