JPH0654966B2 - Digital data recording / reproducing device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a digital data recording / reproducing apparatus for converting a video signal into a digital signal and recording / reproducing it, such as a digital video tape recorder (hereinafter abbreviated as “digital VTR”). Regarding

[Background of the Invention]

In recent years, with the progress of digital IC (integrated circuit) and magnetic recording technology, development of a digital VTR for digitizing a video signal of a television to perform high-quality recording / reproduction has been advanced. (Television Society Journal Vol.39, No.4, 19
85, p312 to 315 "Digital VTR") Since it is necessary to perform high density recording of about 100 megabits / second in a digital VTR, a helical scan VTR using a rotating head is used. In order to further increase the recording density, analog V
The rotating head is rotated at a speed 2 to 3 times faster than that of R. FIG. 9 shows a mounting diagram of the head, cylinder, and magnetic tape of the helical scan. It is composed of an upper cylinder 41 that rotates together with a head 44, a lower cylinder 42 that has a rotary transformer in it, and a magnetic tape 43 that moves in contact with the upper and lower cylinders. The arrows indicate the rotation of the upper cylinder 41 and the direction in which the magnetic tape 43 advances. . Head 44
Contacts the lower part of the magnetic tape 43 from the position shown in FIG. 9, advances to the upper part of the magnetic tape 43 as it rotates, and separates from the magnetic tape 43 at the upper end. In this way, the head 44 scans the magnetic tape 43, and as a result, the video track 45 as shown in FIG. 10 is recorded on the magnetic tape 43. Similarly during reproduction, the head 44 scans the magnetic tape 43 to obtain a reproduction output. However, since the video head 44 rotates at a speed several times faster than the analog VTR, the head 44
Between the head 44 and the magnetic tape 43 due to the air suction or the vibration of the magnetic tape 43 caused by the head 44 hitting the magnetic tape 43 at the portion where the magnetic tape 43 starts to hit the magnetic tape 43 and the portion away from the magnetic tape 43, that is, There are some areas where the contact is poor. FIG. 11 shows the envelope output signal waveform during reproduction of one video track. The output of the hit start part and the hit end part decreases, and the S /
N is lowered, and a code error in the reproduced image is likely to occur. Therefore, the reliability of the data is higher at the central portion of the video track 45 and becomes the worst at both ends. Therefore,
As shown in FIG. 12, there are problems that a large number of hatched code errors occur in the upper and lower portions of the television screen 46, and the image quality deteriorates. Further, in order to realize high-density recording, a plurality of video heads may be switched to record multi-track, that is, one screen of data may be divided into a plurality of video tracks for recording. For example, in the case of dividing into three tracks. The reproduction screen 47 is shown in FIG. One screen 47 is divided into a first track 48, a second track 49, and a third track 50, and a portion where a code error is likely to occur occurs at the start and end of each track. In this case, the image quality is deteriorated because a large number of code errors indicated by diagonal lines occur in the center of the screen 47.
Therefore, it is necessary to minimize the image quality deterioration due to the start and end of the head 44 hitting the track 45.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital data recording / reproducing apparatus which minimizes image quality deterioration due to code errors that frequently occur at the end of hitting and the end of hitting of a video head against a magnetic tape.

[Outline of Invention]

Means of the present invention for solving the above-mentioned problems, before recording,
It has an image memory and arranges the data in the peripheral part of the screen at the beginning and end of the head hitting the magnetic tape where code errors are likely to occur, and the data in the center part of the screen at the part where code errors are hard to occur. By arranging and recording and reproducing,
Even if a code error occurs, it often occurs in the peripheral part of the screen, so that the data reliability of the central part of the screen where the amount of information is large can be improved.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a digital data recording / reproducing apparatus according to the present invention. The digital data recording / reproducing apparatus 14 records / reproduces digital data obtained by digitalizing a video signal or digital data from a digital system (not shown), such as a digital VTR, and includes an A / D converter 2 and The conversion circuit 15, the encoding circuit 3, the recording / reproducing unit 4, and the correction circuit 5
And an inverse conversion circuit 16 and a D / A converter 6. The A / D converter 2 digitizes a video signal obtained from a television system (not shown). The coding circuit 3 adds a correction code to the digital data output from the A / D converter 2 or digital data sent from a digital system (not shown) to correct the code error. is there.
The recording / reproducing unit 4 records and reproduces the digital data to which the correction code is added by the encoding circuit 3 on a recording medium such as a magnetic tape. The correction circuit 5 corrects the code error of the digital data read from the recording / reproducing section 4 by the correction code added by the code circuit 3. The D / A converter 6 converts the digital data whose code error has been corrected by the correction circuit 5 into a video signal and sends it to a television system (not shown).
The digital data whose code error has been corrected by the correction circuit 5 can be directly sent to a digital system (not shown) without passing through the D / A converter 6.

Here, in the present invention, the conversion circuit 15 is provided between the A / D converter 2 and the encoding circuit 3, and the inverse conversion is performed between the correction circuit 5 and the D / A converter 6. Circuit 16
Is provided. The conversion circuit 15 changes the data of the portion where a code error is likely to occur to an address in the peripheral portion of the screen and outputs the data. As shown in FIG. 2, the first field memory 17 and the second field memory are used. It comprises a memory 18, an address controller 19, and a switching switch 20. The first field memory 17 is for writing and reading the data of the first field of the interlaced scanning in a television system not shown, and the second field memory 18 is for writing the second field data of the interlaced scanning. It writes and reads. The first and second field memories 17 and 18 are provided in parallel. When the address controller 19 reads out the data of the first field or the data of the second field from the first or second field memories 17 and 18, respectively, it appropriately changes the address of the data and the data of the portion where the code error is likely to occur. To the address of the peripheral area of the screen. The switching switch 20 switches the output data for each field when reading data from the first and second field memories 17 and 18.

Further, the inverse conversion circuit 16 restores the data whose address has been changed by the conversion circuit 15 to the original address at the time of reproduction, and as shown in FIG. It comprises a second field memory 22, an address controller 23, and a switching switch 24.
The first field memory 21 includes the recording / reproducing unit 4
The data of the first field of the interlaced scanning is written and read out from the data read from the second field memory 22. The data of the second field of the interlaced scanning is written and read out in the second field memory 22.
When the address controller 23 reads out the data of the first field or the data of the second field from the first or second field memories 21 and 22 at the time of reproduction, the address controller 23 appropriately changes the address and causes the conversion circuit 15 to read the data. The data whose address has been changed is returned to the original address. The changeover switch 24 operates in the same manner as the changeover switch 20 of the conversion circuit 15.

Next, the operation of the conversion circuit 15 and the inverse conversion circuit 16 thus configured will be described with reference to FIGS. 4 and 5. First, in the conversion circuit 15, as shown in FIG.
The first field data of the interlaced scanning output from the / D converter 2 or the digital data from the digital system (not shown) is written in the first field memory 17. Here, as shown in FIG. 4, for example, the first field memory 17 is assigned addresses 1 to 525 corresponding to 525 scanning lines, and the digital data is changed in address. It is written to the address as it is without. At this time, the switching switch 20
Has switched to the contact on the side of the second field memory 18, and the data of the second field of the previous interlaced scan has been read. Next, when such writing and reading are completed, the switching switch 20 switches to the contact on the side of the first field memory 17 and reads the data of the first field from the first field memory 17. At this time, under the control of the address controller 19, as shown in FIG. 4, first, the peripheral data D ₁ is read, and then the next peripheral data D ₂ is read. Then, read the data D _{5 in the} center of the screen, and then read the data in the peripheral
Read D ₃ and read the next peripheral data D ₄ . In this way, the peripheral data D ₁ , D ₂ , D ₃ , D ₄ are read after being changed to the addresses at the beginning and the end of the track where code errors are likely to occur. In the meantime, in parallel with this, the second field data of the current interlace scanning is written in the second field memory 18 as shown in the left side view of FIG. Next, the switching switch 20 is switched to the side of the second field memory 18, and the data of the second field is transferred from the second field memory 18 to the fourth field memory.
The address is changed and read as shown in the figure. By repeating this operation for each field and switching the output data by the switching switch 20, the address is changed to the recording medium of the recording / reproducing unit 4 via the encoding circuit 3 as shown in the right side of FIG. Data is written.

Next, in the inverse conversion circuit 16, the data read from the recording / reproducing unit 4 is corrected by the correction circuit 5 as shown in FIG.
And the data of the first field of the interlaced scanning is written in the first field memory 21. Here, as shown in FIG. 5, for example, addresses 1 to 525 are assigned to the first field memory 21, and the order of addresses read from the recording / reproducing unit 4 is:
That is written in a state in which the data D ₁ of the screen's peripheral _{portion, D 2, D 3, D} 4 are changed to the address of the prone portion of the code error. At this time, the switching switch 24 is switched to the contact on the side of the second field memory 22, and the data of the second field in the last interlace scan is read. Next, when such writing and reading are completed, the switching switch 24 switches to the contact on the side of the first field memory 21 and the written first field data is written from the first field memory 21. read out. At this time, under the control of the address controller 23, as shown in FIG. 5, the data D ₁ whose address has been changed by the conversion circuit 15 is read out, and the data D ₂ , D as shown on the left side of FIG. ₃ and D ₅ are read, and the next data D ₄ is read. In this way, the data D ₁ , D ₂ , D ₃ , D ₄ , whose addresses have been changed by the conversion circuit 15 are
All D ₅ are read back to the original address. During this period, in parallel with this, the second field memory 22 is
The data of the second field of this interlaced scanning is written as shown in the right side of FIG. Next, the switching switch 24 switches to the contact on the side of the second field memory 22 and reads the data of the second field from the second field memory 22 by restoring the address as shown in FIG. . By repeating this operation for each field and switching the output data by the switching switch 24, the video signal as shown in the left side diagram of FIG. 5 is supplied to the television system (not shown) via the D / A converter 6. Can be sent out. As a result, the original image is reproduced and displayed on the screen. Incidentally, the digital data can be directly sent to a digital system (not shown) without going through the D / A converter 6.

Further, here, the case where the scanning of the television system (not shown) is the interlaced scanning is shown, but there is no problem even in the case of the sequential scanning.

As shown in FIG. 6, even in the multi-track system in which one field of data is written over several tracks, the data D ₁ ′, D ₃ ′, D ₄ ′, D ₄ ′, D ₁ ′, D ₃ ′, D ₄ ′, in the peripheral portion of the screen, which does not affect the image recognition in the same manner, is also shown. D ₆ ′ may be changed to the addresses of the beginning and end of each track.

Further, depending on how the address controller 19 of the conversion circuit 15 controls the address change, the data in the peripheral portion of the screen can be set to be circular as shown in FIG. Further, here, the address is changed by dividing the two data of the central portion which has a great influence on the image recognition and the peripheral portion which has little influence on the image recognition. For example, the data is not divided as shown in FIG. It is also possible to continuously change the data in the central portion so that it becomes the address in the central portion of the track.

〔The invention's effect〕

According to the present invention, as described above, the conversion circuit 15 is provided between the A / D converter 2 and the encoding circuit 3, and the correction circuit 5 is provided.
The inverse conversion circuit 16 is provided between the D / A converter 6 and the D / A converter 6, and the magnetic tape 43 and the head 44, which are apt to generate code errors, have a peripheral portion of the screen that does not affect the image recognition at the beginning and the end of the collision. Since the data can be arranged, the reliability of the data in the central portion of the screen can be increased.

[Brief description of drawings]

1 is a block diagram showing an embodiment of a digital data recording apparatus according to the present invention, FIG. 2 is a block diagram showing details of a conversion circuit, FIG. 3 is a block diagram showing details of an inverse conversion circuit, and FIG. FIG. 5 is an explanatory diagram showing the operation of the conversion circuit, FIG. 5 is an explanatory diagram showing the operation of the inverse conversion circuit, and FIG. 6 is an explanatory diagram showing the operation of the conversion circuit and the inverse conversion circuit in the multitrack system.
FIG. 7 is an explanatory diagram showing a state where the data of the peripheral portion is set to be circular. FIG. 8 is an explanatory view showing the operation of the conversion circuit in the state where the address is continuously changed, and FIG. 9 is an explanatory view showing the mounting state of the head, cylinder and magnetic tape of the helical scan, FIG. Is an explanatory view showing a tape pattern recorded on a magnetic tape, and FIG. 11 is an explanatory view showing an envelope output signal waveform at the time of reproducing one video track.
FIG. 2 is an explanatory diagram showing a television screen reproduced by a conventional digital data recording / reproducing apparatus, and FIG. 13 is an explanatory diagram showing a television screen recorded / reproducing by a conventional digital data recording / reproducing apparatus by a multi-track system. 2 ... A / D converter, 3 ... Code circuit, 4 ... Recording / reproducing unit, 5 ... Correction circuit, 6 ... D / A converter, 14 ... Digital data recording / reproducing device, 15 ... Conversion Circuit, 16
...... Inverse conversion circuit, 17 ...... First field memory of conversion circuit, 18 ...... Second field memory of conversion circuit,
19 ... Conversion circuit address controller, 20 ... Conversion circuit switching switch, 21 ... Inverse conversion circuit first field memory, 22 ... Inverse conversion circuit second field memory, 23 ... Inverse conversion circuit Address controller 24, switch for reverse conversion circuit, D ₁ , D ₂ , D ₃ ,
D ₄ …… Screen peripheral data that is placed in the area where code errors are likely to occur.

Claims (1)

[Claims] 1. An A / D converter for digitizing a video signal, and a coding circuit for adding a correction code for correcting a code error at the time of recording to digital data from the A / D converter at the time of reproduction. A recording / reproducing unit for recording and reproducing the digital data to which the correction code is added to a recording medium, a correction circuit for correcting a code error of the digital data read from the recording / reproducing unit, and a digital for correcting the code error. D / A to convert data to video signal
In a digital data recording / reproducing apparatus having a converter, data of a head start portion and a head end portion of a head and a magnetic tape are changed to addresses of an image peripheral portion between the A / D converter and an encoding circuit. Digital data recording, characterized in that a conversion circuit for outputting and a reverse conversion circuit for returning the data whose address has been changed to the original address at the time of reproduction are provided between the correction circuit and the D / A converter. Playback device.