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JPH0653652A - Multilayer ceramic wiring board and manufacture of the same - Google Patents

Multilayer ceramic wiring board and manufacture of the same

Info

Publication number
JPH0653652A
JPH0653652A JP3049702A JP4970291A JPH0653652A JP H0653652 A JPH0653652 A JP H0653652A JP 3049702 A JP3049702 A JP 3049702A JP 4970291 A JP4970291 A JP 4970291A JP H0653652 A JPH0653652 A JP H0653652A
Authority
JP
Japan
Prior art keywords
cavity
ceramic
multilayer ceramic
wiring
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3049702A
Other languages
Japanese (ja)
Inventor
Keiichiro Ho
慶一郎 方
Yuzo Shimada
勇三 嶋田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3049702A priority Critical patent/JPH0653652A/en
Publication of JPH0653652A publication Critical patent/JPH0653652A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To improve signal propagation speed while maintaining a mechanical strength by selectively forming a cavity only in the proximity to an internal layer conductor wiring. CONSTITUTION:A multilayer ceramic wiring substrate produced by a green sheet multilayer forming method which allows three dimensional conductor wirings has a structure that a ground layer 2, a signal layer 3 and a power supply layer 4 are provided in the form of three-dimension within an insulated ceramic 1, a high speed LSI element 6 is provided on the upper surface of the ceramic 1 and input/output pins 7 are provided at the lower surface through via holes 5. Moreover, cavities 8 are selectively provided only in the proximity to conductor wiring within the multilayer ceramic wiring substrate by a cavity forming technology utilizing photolithographic method. Thereby, it becomes possible to obtain a high speed LSI 6 element loading substrate, contributing to the improvement of high density packaging and high transmission speed, because only the dielectric constant of the medium in the vicinity of wiring required for high transmission speed is low, sudden drop of mechanical characteristic such as strength is never generated and design of wirings can be realized very easily.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高速LSI素子を実装
するための多層セラミック配線基板とその製造方法に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic wiring board for mounting a high speed LSI device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、ICやLSI等の半導体素子は、
ガラスエポキシ等のプリント回路基板あるいはアルミナ
セラミック基板に実装されていたが、半導体素子の高集
積化,微細化,高速化に伴い、実装用基板に対しても高
密度微細配線化,高速伝送化,高周波数化,高熱放散化
の要求が増えてきた。
2. Description of the Related Art Conventionally, semiconductor elements such as IC and LSI are
It was mounted on a printed circuit board such as glass epoxy or an alumina ceramic board, but with the high integration, miniaturization, and speedup of semiconductor elements, high-density fine wiring, high-speed transmission, and high-speed transmission were also achieved for the mounting board. There has been an increasing demand for higher frequencies and higher heat dissipation.

【0003】従来のプリント基板には、スルーホールメ
ッキ性,加工性,多層化接着,高温での熱変形等の問題
があり、高密度化には限界がある。そのため、高密度実
装基板としては未だ実用化には至っておらず、セラミッ
ク基板の方が可能性を秘めている。
The conventional printed circuit board has problems such as through-hole plating property, workability, multi-layered adhesion, and thermal deformation at high temperature, so that there is a limit to high density. Therefore, it has not yet been put to practical use as a high-density mounting board, and a ceramic board has more potential.

【0004】しかし、アルミナ基板も1500℃以上の
高温で焼結しなければならないため、同時焼成される配
線導体材料としては、比較的比抵抗の高いW,Mo等の
高融点金属に限定される。したがって、パルス信号の伝
送損失を考慮に入れた場合、配線パターンの微細化には
限界が生じてしまう。
However, since the alumina substrate also has to be sintered at a high temperature of 1500 ° C. or higher, the wiring conductor materials to be co-fired are limited to high melting point metals such as W and Mo having a relatively high specific resistance. . Therefore, if the transmission loss of the pulse signal is taken into consideration, there is a limit to the miniaturization of the wiring pattern.

【0005】一方、高速伝送化に対しても、パルス信号
の伝播遅延時間が基板材料の誘電率の平方根に比例する
ため、基板材料の低誘電率化が必要不可欠となる。しか
し、アルミナ基板は誘電率が約10と比較的高い。
On the other hand, even for high-speed transmission, since the propagation delay time of the pulse signal is proportional to the square root of the dielectric constant of the substrate material, it is essential to reduce the dielectric constant of the substrate material. However, the alumina substrate has a relatively high dielectric constant of about 10.

【0006】そこで、開発されたのが低温焼結性多層セ
ラミック基板である。絶縁材料としては、セラミックと
ガラスの複合材料系や結晶化ガラス系等があるが、いず
れも1000℃以下で焼結するため、配線導体材料とし
て比抵抗の低いAu,Ag−Pd,Cu等の低融点金属
を用いることができる。また、低誘電率セラミックやガ
ラスを選定することで、絶縁材料の誘電率を5以下に下
げることも可能である。更に、グリーンシート多層化法
を使うことができるため、三次元配線が可能で高密度化
に非常に有利である。
Therefore, a low temperature sinterable multilayer ceramic substrate has been developed. As the insulating material, there are a composite material system of ceramic and glass, a crystallized glass system, and the like, but since both are sintered at 1000 ° C. or less, Au, Ag—Pd, Cu, etc. having a low specific resistance are used as the wiring conductor material. Low melting point metals can be used. Further, it is possible to reduce the dielectric constant of the insulating material to 5 or less by selecting low dielectric constant ceramic or glass. Furthermore, since the green sheet multi-layering method can be used, three-dimensional wiring is possible, which is very advantageous for increasing the density.

【0007】[0007]

【発明が解決しようとする課題】しかし、信号の伝搬ス
ピードを効率的に速くする、即ち内層導体の分布容量を
効率よく低減するには、周辺の誘電体のみ比誘電率を下
げれば良いのであり、何も誘電体全体の比誘電率を下げ
る必要性はない。現状のセラミックの中で、石英ガラス
に優る比誘電率を有するものはなく、高々3.8程度で
ある。
However, in order to efficiently increase the signal propagation speed, that is, to effectively reduce the distributed capacitance of the inner layer conductor, it is sufficient to lower the relative permittivity of only the peripheral dielectric. , There is no need to lower the relative permittivity of the entire dielectric. Among the current ceramics, no one has a relative permittivity superior to that of quartz glass, and is at most about 3.8.

【0008】一方、特願昭63−269766号,24
5066号,269766号に記載されているように、
比誘電率が1の空気あるいはガスを含む空隙をセラミッ
ク内部へ均一に導入することは、母体の比誘電率を下げ
るのに非常に有効であるが、低減率に限りがあり、信頼
性を維持した上ではせいぜい3前後までしか下げること
はできない。また、多くの空隙の導入に伴い、機械的特
性、特に曲げ強度の劣化が激しく、実用上問題が多い。
On the other hand, Japanese Patent Application No. 63-269766, 24
As described in Nos. 5066 and 269766,
The uniform introduction of voids containing air or gas with a relative permittivity of 1 into the ceramic is very effective in lowering the relative permittivity of the matrix, but the reduction rate is limited and reliability is maintained. On top of that, I can only lower it to around 3. Also, with the introduction of many voids, mechanical properties, particularly bending strength, are severely deteriorated, and there are many practical problems.

【0009】したがって、本発明の目的は、このような
従来の課題を解決した多層セラミック配線基板とその製
造方法を提供することにある。
Therefore, an object of the present invention is to provide a multilayer ceramic wiring board and a method for manufacturing the same, which solves the conventional problems.

【0010】[0010]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る多層セラミック配線基板においては、
セラミック基板内に三次元的に導体配線が形成されてい
る多層セラミック配線基板であって、内層導体配線の近
傍のみに選択的に空洞を形成したものである。
In order to achieve the above object, in a multilayer ceramic wiring board according to the present invention,
A multilayer ceramic wiring substrate in which conductor wiring is three-dimensionally formed in a ceramic substrate, and a cavity is selectively formed only in the vicinity of the inner layer conductor wiring.

【0011】また、本発明に係る多層セラミック配線基
板の製造方法においては、導体配線パターン形成工程
と、空洞パターン形成工程と、積層体作製工程と、処理
工程とを有する多層セラミック配線基板の製造方法であ
って、導体配線パターン形成工程は、セラミック粉末と
バインダー等の有機添加剤を溶剤中で均一に分散させた
グリーンシートにスルーホールを形成し導体を充填する
と共にグリーンシート上に導体配線パターンを形成する
工程であり、空洞パターン形成工程は、支持体上に感光
性樹脂を用いて所要の空洞パターンを形成する工程であ
り、積層体作製工程は、前記感光性樹脂からなる空洞パ
ターンとセラミックグリーンシートを含む積層体を作製
する工程であり、処理工程は、該積層体の脱バインダー
及び焼成を行う工程である。
In the method for manufacturing a multilayer ceramic wiring board according to the present invention, a method for manufacturing a multilayer ceramic wiring board having a conductor wiring pattern forming step, a cavity pattern forming step, a laminated body manufacturing step, and a processing step. In the step of forming the conductor wiring pattern, the through holes are formed in the green sheet in which the ceramic powder and the organic additive such as the binder are uniformly dispersed in the solvent, the conductor is filled, and the conductor wiring pattern is formed on the green sheet. The step of forming a cavity pattern, the step of forming a cavity pattern is a step of forming a desired cavity pattern using a photosensitive resin on a support, and the step of forming a laminate is a step of forming a cavity pattern made of the photosensitive resin and a ceramic green. It is a step of producing a laminate including sheets, and the treatment step is a step of debinding and firing the laminate. A.

【0012】[0012]

【作用】セラミック粉末とバインダー等の有機添加剤を
溶剤中で均一に分散させたグリーンシートにスルーホー
ルを形成し導体を充填すると共にグリーンシート上に導
体配線パターンを形成する工程と、支持体上に感光性樹
脂を用いて所要の空洞形成パターンを形成する工程と、
前記感光性樹脂からなる空洞形成パターンとセラミック
グリーンシートを含む積層体を作製する工程と、該積層
体の脱バインダー及び焼成を行う工程により内層導体配
線の近傍にのみに選択的に空洞を形成し、周辺の実効比
誘電率のみをできるだけ下げることにより、信号の伝搬
スピードを効率的に速くし、かつ機械的強度を維持する
ようにしたものである。
[Function] A step of forming through holes in a green sheet in which a ceramic powder and an organic additive such as a binder are uniformly dispersed in a solvent to fill a conductor and form a conductor wiring pattern on the green sheet; And a step of forming a required cavity forming pattern using a photosensitive resin,
A cavity is selectively formed only in the vicinity of the inner-layer conductor wiring by a step of producing a laminate including a cavity forming pattern made of the photosensitive resin and a ceramic green sheet, and a step of debinding and firing the laminate. By reducing only the effective relative permittivity in the periphery as much as possible, the signal propagation speed is efficiently increased and the mechanical strength is maintained.

【0013】[0013]

【実施例】次に、本発明について図面を引用して詳細に
説明する。
Next, the present invention will be described in detail with reference to the drawings.

【0014】(実施例1)図1において、本発明の多層
セラミック配線基板は、三次元的な導体配線が可能なグ
リーンシート多層化法によって作製され、絶縁セラミッ
ク部1内に三次元的にグランド層2,信号層3,電源層
4が形成し、セラミック部1の上面に高速LSI素子6
が設置され、ビアホール5を介して下面に入出力ピン7
が設けられた多層セラミック配線基板であり、さらに、
多層セラミック配線基板内部の導体配線の近傍のみに、
光リソグラフィ法を用いた空孔形成技術により選択的に
空洞8が設けられている。
(Example 1) In FIG. 1, a multilayer ceramic wiring board of the present invention is manufactured by a green sheet multilayering method capable of three-dimensional conductor wiring, and three-dimensionally grounded in the insulating ceramic portion 1. The layer 2, the signal layer 3 and the power supply layer 4 are formed, and the high speed LSI element 6 is formed on the upper surface of the ceramic portion 1.
Is installed, and the input / output pin 7 is placed on the bottom surface through the via hole 5.
Is a multilayer ceramic wiring board provided with,
Only near the conductor wiring inside the multilayer ceramic wiring board,
The cavities 8 are selectively provided by the hole forming technique using the photolithography method.

【0015】本発明の実施例1として、セラミック材料
のアルミナを55重量%、ホウケイ酸系鉛ガラスを45
重量%含む2成分系の複合体をセラミックとして用いた
場合について述べる。なお、本組成は特願昭59−22
399号公告に記載されている。この複合体は900℃
程度の低温で焼結し、誘電率7.8,抗折強度3000
kg/cm2を示す。また、金や銀、あるいは銀−パラ
ジウム系等抵抗の低い導体材料を適用することができ
る。
As Example 1 of the present invention, 55% by weight of alumina as a ceramic material and 45% by weight of borosilicate lead glass were used.
A case where a two-component composite containing wt% is used as a ceramic will be described. This composition is used in Japanese Patent Application No. 59-22.
It is described in the publication No. 399. This composite is 900 ℃
Sintered at about low temperature, dielectric constant 7.8, bending strength 3000
Indicates kg / cm 2 . Further, a conductor material having low resistance such as gold or silver or a silver-palladium system can be applied.

【0016】一般に多層セラミック配線基板は次のよう
な方法によって製造される。即ち、上記組成の混合粉末
とバインダー等の有機添加剤を、高速ミキサーやボール
ミルを用い、溶剤中で均一に分散させ、スラリーを作製
し、これをスリップキャスティング法やドクダーブレー
ド法により絶縁層を形成するのに適した膜厚のグリーン
シートを作製する。なお、バインダーや溶剤等の有機ビ
ヒクル類の成分については、特に限定を要しない。
Generally, a multilayer ceramic wiring board is manufactured by the following method. That is, a mixed powder of the above composition and an organic additive such as a binder are uniformly dispersed in a solvent using a high speed mixer or a ball mill to prepare a slurry, which is then formed into an insulating layer by a slip casting method or a docker blade method. A green sheet having a film thickness suitable for forming is prepared. In addition, the components of the organic vehicle such as the binder and the solvent are not particularly limited.

【0017】次に、上下導体を接続するスルーホールを
グリーンシートに形成し、導体を充填すると共に、グリ
ーンシート上に導体配線パターンを形成する。更に、こ
れらを所要の多層構造となるように積層・熱圧着し、積
層体を作製する。次いで、形成時に添加された有機ビヒ
クル類を十分除去、即ち脱バインダーした後に、最適な
条件で焼成され、多層セラミック配線基板が得られる。
Next, through holes for connecting the upper and lower conductors are formed in the green sheet, the conductors are filled, and a conductor wiring pattern is formed on the green sheet. Further, these are laminated and thermocompression-bonded so as to have a required multilayer structure to produce a laminated body. Next, the organic vehicles added at the time of formation are sufficiently removed, that is, the binder is removed, and then baked under optimum conditions to obtain a multilayer ceramic wiring board.

【0018】更に、本発明では感光性樹脂を用い、精度
の高い微細な空孔パターンを形成し、導体配線を形成し
た上記グリーンシートを含むグリーンシートと共に積層
・熱圧着する工程が加わる。図2は、本発明の多層セラ
ミック配線基板の製造プロセスの一例を、また図3には
工程系統図の一例を示す。なお、詳細は特願昭60−2
43218号,243219号,61−186427号
公報に記載されている。
Further, in the present invention, a step of forming a highly precise fine hole pattern using a photosensitive resin and laminating / thermocompression bonding with a green sheet including the above-mentioned green sheet on which conductor wiring is formed is added. FIG. 2 shows an example of a manufacturing process of the multilayer ceramic wiring board of the present invention, and FIG. 3 shows an example of a process system diagram. For details, see Japanese Patent Application No. 60-2.
No. 43218, 243219, 61-186427.

【0019】感光性樹脂としては、フォトレジスト用と
して一般的に使用されている光架橋型,光分解型,光重
合型等があり、アクリル系を始めナイロン系,エポキシ
系,ポリウレタン系,ポリブタジエン系等種々の材料を
適用することができる。詳細は、特願昭61−1062
67号,106268号,106269号,18642
7号公報に記載されている。
As the photosensitive resin, there are photocrosslinking type, photodegrading type, photopolymerizing type and the like which are generally used for photoresists, and acrylic type, nylon type, epoxy type, polyurethane type, polybutadiene type, etc. Various materials such as the above can be applied. For details, see Japanese Patent Application No. 61-1062.
67, 106268, 106269, 18642
No. 7 publication.

【0020】これらの感光性樹脂には、以下の特性が要
求される。 (1)膜厚が広い範囲で、かつ均一なものが形成でき
る。 (2)微細パターンの形成が膜厚に関わらず、形成可能
である。 (3)積層・圧着工程でのパターンの変形が少ない。 (4)脱バインダー工程における急激な分解・融解・膨
張・変形等の現象が起こらない。 (5)分解後残さがない。 特に、精度の高い配線設計をする上で、感光性樹脂、即
ち空洞形成剤の膜厚としては10μmから1mm程度
が、膜厚の精度として±10%以下が必要と思われる。
また、現在実用化されているレベルでも、パターン幅が
10μm,ピッチ幅が20μmのものは可能である。
The following characteristics are required for these photosensitive resins. (1) A uniform film can be formed in a wide range of film thickness. (2) The fine pattern can be formed regardless of the film thickness. (3) There is little pattern deformation in the stacking / press bonding process. (4) Phenomena such as rapid decomposition, melting, expansion and deformation in the binder removal process do not occur. (5) There is no residue after decomposition. In particular, in designing wiring with high accuracy, it is considered that the film thickness of the photosensitive resin, that is, the cavity forming agent, is required to be about 10 μm to 1 mm and the film thickness accuracy is ± 10% or less.
Further, even at the level of practical use at present, a pattern width of 10 μm and a pitch width of 20 μm are possible.

【0021】さて、上記の感光性樹脂を用いて、精度の
高い微細な空洞パターンを形成するには、まず図3
(a)に示すように、支持体10上に感光性樹脂9を所
定の厚さに均一にコーティングする。なお、支持体10
としては、ポリエステル等のキャリアフィルム,ガラス
板,金属シート,セラミックグリーンシート等を挙げる
ことができる。
Now, in order to form a highly precise fine cavity pattern using the above-mentioned photosensitive resin, first, referring to FIG.
As shown in (a), the support 10 is uniformly coated with the photosensitive resin 9 to a predetermined thickness. The support 10
Examples thereof include a carrier film such as polyester, a glass plate, a metal sheet, and a ceramic green sheet.

【0022】このようにして塗布された感光性樹脂9上
に、所望のパターンが形成されたフォトマスクパターン
11を密着させ、光を照射,露光した後に、現像処理を
行い所定の空洞パターン12を形成する(図3(b),
(c))。なお、本実施例では、感光性樹脂9として、
メチルメタクリレートとブチルメタクリレートの共重合
体が52.2重量%,テトラエチレングリコールジアク
リレートが13重量%,トリメチロールプロパントリア
クリレートが2.6重量%,ベンゾフェノンが2.6重
量%,ミヒラーズケトンが0.5重量%,2−エチル4
−tert−ブチルフェノールを0.05重量%,メチ
レンブルーが0.25重量%,エチレングリコールモノ
エチルエーテルアセテートが21重量%,ジエチレング
リコールモノエチルエーテルが5.2重量%及びキシレ
ンが2.6重量%からなる光重合型のものを用いた。ま
た、露光条件は3kW超高圧水銀灯により紫外線を選択
的に1分間照射した。現像条件はメチルクロロホルムを
1kg/cm2の圧力で吹きかけた。
A photomask pattern 11 on which a desired pattern is formed is brought into close contact with the photosensitive resin 9 applied in this manner, and after light irradiation and exposure, development processing is performed to form a predetermined cavity pattern 12. Form (FIG. 3 (b),
(C)). In addition, in this embodiment, as the photosensitive resin 9,
The copolymer of methyl methacrylate and butyl methacrylate was 52.2% by weight, tetraethylene glycol diacrylate was 13% by weight, trimethylolpropane triacrylate was 2.6% by weight, benzophenone was 2.6% by weight, and Michler's ketone was 0. 5% by weight, 2-ethyl 4
0.05% by weight of -tert-butylphenol, 0.25% by weight of methylene blue, 21% by weight of ethylene glycol monoethyl ether acetate, 5.2% by weight of diethylene glycol monoethyl ether and 2.6% by weight of xylene. A photopolymerization type was used. The exposure conditions were that ultraviolet rays were selectively irradiated for 1 minute by a 3 kW ultra-high pressure mercury lamp. The developing conditions were such that methyl chloroform was sprayed at a pressure of 1 kg / cm 2 .

【0023】次に、支持体10がセラミックグリーンシ
ート以外の場合、空洞パターン12を形成した後、それ
らを支持体10から剥離しグリーンシート上に転写する
必要がある。例えば、キャリアフィルムからは110
℃,圧力250kgf/cm2の条件で加圧すれば、簡
単に剥離することができ、空洞形成パターンの樹脂は理
想的な形状を維持しながら、グリーンシート内に埋設さ
れることになる。
Next, when the support 10 is other than the ceramic green sheet, it is necessary to form the cavity patterns 12 and then peel them off from the support 10 and transfer them onto the green sheet. For example, from the carrier film 110
If the resin is pressed under the conditions of ° C and a pressure of 250 kgf / cm 2 , it can be easily peeled off, and the resin of the cavity forming pattern is embedded in the green sheet while maintaining its ideal shape.

【0024】このようにして、精度の高い微細な空洞パ
ターン12は、所望の構造となるよう導体配線2,3,
5を形成したセラミックグリーンシート13を含むグリ
ーンシートと共に、熱圧着用の金型の中へ積層され、圧
力・温度を加えて一体化される(図3(d),
(e))。
In this way, the highly precise and fine cavity pattern 12 has the conductor wirings 2, 3, 3 so that it has a desired structure.
5 is laminated together with a green sheet including the ceramic green sheet 13 in which the ceramic green sheet 5 has been formed into a die for thermocompression bonding, and is integrated by applying pressure and temperature (FIG. 3 (d),
(E)).

【0025】更に、この積層体は空洞パターンの樹脂や
セラミックグリーンシート13内に含まれている有機ビ
ヒクル類が十分分解・飛散するような脱バインダー条件
で処理される。通常、これらの有機物は500〜600
℃までには、酸化雰囲気であれば完全に分解・酸化する
が、急激に温度を分解温度まで上昇させると、積層体に
クラック・変形・デラミネーション等が発生してしま
う。そこで、例えば25℃/時間程度のゆっくりとした
温度上昇スピードで昇温し、かつ500〜600℃で十
分長い時間保持する方が好ましい。
Further, this laminated body is treated under a debinding condition so that the resin of the hollow pattern and the organic vehicles contained in the ceramic green sheet 13 are sufficiently decomposed and scattered. Usually, these organic substances are 500 to 600
Up to ℃, it decomposes and oxidizes completely in an oxidizing atmosphere, but if the temperature is rapidly raised to the decomposition temperature, cracks, deformation, delamination, etc. occur in the laminate. Therefore, it is preferable to raise the temperature at a slow rate of temperature increase of, for example, about 25 ° C./hour, and hold the temperature at 500 to 600 ° C. for a sufficiently long time.

【0026】脱バインダー工程で十分有機物を除去した
積層体は、引続き所定の温度で焼結されるため、空洞パ
ターンの部分は空洞8として焼結体内部に残留すること
になる(図3(f))。特に、内層導体配線近傍の所定
の位置に所望の大きさの空洞8が形成されるように、積
層時に考慮すれば、選択的に基板内部に空洞を形成する
ことができる。
Since the laminated body from which the organic substances have been sufficiently removed in the binder removal step is subsequently sintered at a predetermined temperature, the cavity pattern portion remains as a cavity 8 inside the sintered body (FIG. 3 (f)). )). In particular, if the cavity 8 having a desired size is formed at a predetermined position in the vicinity of the inner-layer conductor wiring, it is possible to selectively form the cavity inside the substrate by considering the lamination.

【0027】例えば、図4のような寸法の空洞8を基板
の内層導体配線近傍に形成し、信号の伝搬遅延時間を測
定すると、5.7ns/mとなり、空洞を形成しない場
合の9.5ns/mに比べ、約40%も短縮することが
でき、多いに高速化に寄与できる。
For example, when the cavity 8 having a size as shown in FIG. 4 is formed in the vicinity of the inner layer conductor wiring of the substrate and the signal propagation delay time is measured, it becomes 5.7 ns / m, and 9.5 ns when the cavity is not formed. It can be shortened by about 40% as compared with / m, which can greatly contribute to speeding up.

【0028】また、複合比誘電率を算出する代表的な式
である体積対数混合則(下記の(1)式)を用い、信号
層とグランド層間に存在する媒体の比誘電率を計算する
と下記のようになる。
Also, using the volume logarithmic mixing rule (equation (1) below), which is a typical equation for calculating the composite relative permittivity, the relative permittivity of the medium existing between the signal layer and the ground layer is calculated as follows. become that way.

【0029】 logK=V1・logK1+V2・logK2……(1) (K:複合体の比誘電率,V1,K1:物質Iの体積分率
及び比誘電率,V2,K2:物質IIの体積分率及び比誘
電率)いま物質Iを本発明の実施例1でセラミックとし
て用いているアルミナとホウケイ酸系鉛ガラスの複合
体、物質IIを空洞とすると、K1は7.8,K2は1と
なる。また、信号層3とグランド層2間で空洞8が占め
る割合:V2を単純に断面方向の厚みから算出すると、
0.5となる。以上の数値を上記(1)式に代入、複合
体の比誘電率を求めると、約2.8となる。
LogK = V 1 · logK 1 + V 2 · logK 2 (1) (K: relative permittivity of complex, V 1 , K 1 : volume fraction and relative permittivity of substance I, V 2 , K 2 : volume fraction and relative permittivity of substance II) If substance I is used as a ceramic in Example 1 of the present invention as a composite of alumina and borosilicate lead glass, and substance II is a cavity, K 1 Is 7.8 and K 2 is 1. Further, if the ratio V 2 occupied by the cavity 8 between the signal layer 3 and the ground layer 2 is simply calculated from the thickness in the cross-sectional direction,
It becomes 0.5. By substituting the above numerical values into the above formula (1) and determining the relative permittivity of the composite, it becomes approximately 2.8.

【0030】更に比誘電率と伝搬遅延時間の関係を示す
理論式(下記の(2)式参照)から理論値を求めると、
下記のように5.6ns/mとなり、上記の実験値と大
差ないことから、配線設計時に信号の伝搬遅延時間を予
測することは十分可能と思われる。
Further, when a theoretical value is obtained from a theoretical formula (see the following formula (2)) showing the relationship between the relative permittivity and the propagation delay time,
Since it becomes 5.6 ns / m as shown below, which is not much different from the above experimental value, it seems that it is sufficiently possible to predict the signal propagation delay time at the time of wiring design.

【0031】Tpd=√K/c……(2) (Tpd:信号の伝搬遅延時間,c:光速)同様に、特
性インピーダンスやクロストークノイズ等の基本的なパ
ルス伝送特性についても設計は十分可能である。
Tpd = √K / c (2) (Tpd: signal propagation delay time, c: speed of light) Similarly, basic pulse transmission characteristics such as characteristic impedance and crosstalk noise can be sufficiently designed. Is.

【0032】一方、曲げ強度に関しては、空洞を形成し
ても厚みさえ十分とれば、実用上必要な値はクリヤーで
きる。
On the other hand, with respect to bending strength, a value required for practical use can be cleared as long as the cavity has a sufficient thickness.

【0033】(実施例2)本発明の実施例2として、セ
ラミック材料の石英ガラスを15重量%,コーディエラ
イトを20重量%,ホウケイ酸系ガラスを65重量%含
む3成分系の複合体をセラミックとして用いた場合につ
いて述べる。なお、本組成は特願平01−218707
号公報に記載されている。この複合体は900℃程度の
低温で焼結し、誘電率4.4,抗折強度1600kg/
cm2を示すと共に、熱膨張係数がSi素子に近く、ベ
アチップ実装が可能である。また、金,銀,銅あるいは
銀−パラジウム系等抵抗の低い導体材料を適用すること
ができる。なお、製造方法に関しては実施例1と何等変
わらない。
(Example 2) As Example 2 of the present invention, a three-component composite containing 15% by weight of quartz glass as a ceramic material, 20% by weight of cordierite and 65% by weight of borosilicate glass was used. The case of using as a ceramic will be described. In addition, this composition is Japanese Patent Application No. 01-218707.
It is described in Japanese Patent Publication No. This composite was sintered at a low temperature of about 900 ° C. and had a dielectric constant of 4.4 and a flexural strength of 1600 kg /
In addition to showing cm 2 , the thermal expansion coefficient is close to that of the Si element, and bare chip mounting is possible. Further, a conductor material having low resistance such as gold, silver, copper, or silver-palladium system can be applied. The manufacturing method is the same as that of the first embodiment.

【0034】実施例1と同様に図4のような寸法の空洞
を基板の内層導体配線近傍に形成し、信号の伝搬遅延時
間を測定すると、4.7ns/mとなり、空洞を形成し
ない場合の7.0ns/mに比べ、約35%も短縮する
ことができ、実施例1よりも更に高速化に寄与できる。
また、配線設計や強度の維持も実施例1同様に十分可能
である。
As in Example 1, when a cavity having a size as shown in FIG. 4 was formed near the inner conductor wiring of the substrate and the signal propagation delay time was measured, it was 4.7 ns / m. It can be shortened by about 35% as compared with 7.0 ns / m, which can contribute to further speeding up compared with the first embodiment.
Further, the wiring design and the strength can be maintained sufficiently as in the first embodiment.

【0035】なお、本発明の図4は、ほんの一例に過ぎ
ず、任意に空洞の位置をコントロールできることが本発
明の多層セラミック配線基板の製造方法の特徴であり、
また重要な点である。また、本発明はその要旨を変更し
ない限り、上記実施例に限定されるものではない。
FIG. 4 of the present invention is merely an example, and the feature of the method for producing a multilayer ceramic wiring board of the present invention is that the position of the cavity can be controlled arbitrarily.
Another important point. Further, the present invention is not limited to the above embodiments unless the gist thereof is changed.

【0036】[0036]

【発明の効果】以上説明したように本発明の多層セラミ
ック配線基板では、誘電率を低減させるのに有効な空洞
を、グリーンシート多層化法により三次元配線が施され
ている内層導体の近傍のみに、感光性樹脂を用いて選択
的に形成することができる。したがって、高速伝送化に
必要な配線周辺の媒体の誘電率のみ低く、強度等機械的
特性の急激な低下は起こらず、配線設計も比較的容易で
あるため、高速LSI素子実装用基板の提供が可能とな
り、実装の高密度化と高速伝送化の向上に大きく寄与で
きる。
As described above, in the multilayer ceramic wiring board of the present invention, the cavity effective for reducing the dielectric constant is provided only in the vicinity of the inner layer conductor on which the three-dimensional wiring is formed by the green sheet multilayer method. In addition, it can be selectively formed by using a photosensitive resin. Therefore, only the dielectric constant of the medium around the wiring required for high-speed transmission is low, the mechanical characteristics such as strength do not drop sharply, and the wiring design is relatively easy. Therefore, it is possible to provide a substrate for mounting a high-speed LSI element. This makes it possible to greatly contribute to higher packaging density and higher transmission speed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の多層セラミック配線基板を示す構造断
面図である。
FIG. 1 is a structural cross-sectional view showing a multilayer ceramic wiring board of the present invention.

【図2】本発明の基板製造プロセスの一例を示す図であ
る。
FIG. 2 is a diagram showing an example of a substrate manufacturing process of the present invention.

【図3】本発明の工程系統の一例を示す図である。FIG. 3 is a diagram showing an example of a process system of the present invention.

【図4】本発明の具体例を示す構造断面図である。FIG. 4 is a structural cross-sectional view showing a specific example of the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁セラミック部 2 グランド層 3 信号層 4 電源層 5 ビアホール 6 高速LSI素子 7 入出力ピン 8 空洞 9 空洞形成用感光性樹脂 10 支持体 11 フォトマスクパターン 12 空洞形成パターン 13 セラミックグリーンシート 1 Insulation Ceramic Part 2 Ground Layer 3 Signal Layer 4 Power Layer 5 Via Hole 6 High Speed LSI Element 7 Input / Output Pin 8 Cavity 9 Photosensitive Resin for Cavity Formation 10 Support 11 Photomask Pattern 12 Cavity Formation Pattern 13 Ceramic Green Sheet

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 セラミック基板内に三次元的に導体配線
が形成されている多層セラミック配線基板であって、 内層導体配線の近傍のみに選択的に空洞を形成したもの
であることを特徴とする多層セラミック配線基板。
1. A multilayer ceramic wiring board in which conductor wiring is three-dimensionally formed in a ceramic substrate, wherein a cavity is selectively formed only in the vicinity of the inner layer conductor wiring. Multilayer ceramic wiring board.
【請求項2】 導体配線パターン形成工程と、空洞パタ
ーン形成工程と、積層体作製工程と、処理工程とを有す
る多層セラミック配線基板の製造方法であって、 導体配線パターン形成工程は、セラミック粉末とバイン
ダー等の有機添加剤を溶剤中で均一に分散させたグリー
ンシートにスルーホールを形成し導体を充填すると共に
グリーンシート上に導体配線パターンを形成する工程で
あり、 空洞パターン形成工程は、支持体上に感光性樹脂を用い
て所要の空洞パターンを形成する工程であり、 積層体作製工程は、前記感光性樹脂からなる空洞パター
ンとセラミックグリーンシートを含む積層体を作製する
工程であり、 処理工程は、該積層体の脱バインダー及び焼成を行う工
程であることを特徴とする多層セラミック配線基板の製
造方法。
2. A method for manufacturing a multilayer ceramic wiring board, comprising: a conductor wiring pattern forming step, a cavity pattern forming step, a laminated body manufacturing step, and a treating step, wherein the conductor wiring pattern forming step comprises a ceramic powder. This is the process of forming through holes in a green sheet in which organic additives such as binders are uniformly dispersed in a solvent, filling conductors, and forming a conductor wiring pattern on the green sheet. A step of forming a desired cavity pattern using a photosensitive resin on the top, and a laminate producing step is a step of producing a laminate including the cavity pattern made of the photosensitive resin and a ceramic green sheet, Is a step of debinding and firing the laminate, a method for manufacturing a multilayer ceramic wiring board.
JP3049702A 1991-03-14 1991-03-14 Multilayer ceramic wiring board and manufacture of the same Pending JPH0653652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3049702A JPH0653652A (en) 1991-03-14 1991-03-14 Multilayer ceramic wiring board and manufacture of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3049702A JPH0653652A (en) 1991-03-14 1991-03-14 Multilayer ceramic wiring board and manufacture of the same

Publications (1)

Publication Number Publication Date
JPH0653652A true JPH0653652A (en) 1994-02-25

Family

ID=12838520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3049702A Pending JPH0653652A (en) 1991-03-14 1991-03-14 Multilayer ceramic wiring board and manufacture of the same

Country Status (1)

Country Link
JP (1) JPH0653652A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139130A (en) * 1994-11-09 1996-05-31 Hitachi Ltd Semiconductor device
WO2003022571A1 (en) * 2001-09-13 2003-03-20 Motorola, Inc., A Corporation Of The State Of Delaware Process for the production of patterned ceramic green-sheets and multilayered ceramic devices
JP2006185989A (en) * 2004-12-27 2006-07-13 Murata Mfg Co Ltd Circuit board and its manufacturing method
JP2006196832A (en) * 2005-01-17 2006-07-27 Kyocera Corp Multilayer wiring board
US10499506B2 (en) 2016-03-11 2019-12-03 Murata Manufacturing Co., Ltd. Composite substrate and method for manufacturing composite substrate
US11140778B2 (en) 2018-03-02 2021-10-05 Murata Manufacturing Co., Ltd. Multilayer ceramic substrate and method of manufacturing multilayer ceramic substrate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4963964A (en) * 1972-10-27 1974-06-20
JPS5615098A (en) * 1979-07-18 1981-02-13 Ngk Spark Plug Co Low dielectric multilayer ceramic substrate
JPS62101453A (en) * 1985-10-29 1987-05-11 Nec Corp Manufacture of ceramic electronic parts
JPS63249394A (en) * 1987-04-06 1988-10-17 日本電気株式会社 Multilayer circuit board
JPH01120095A (en) * 1987-11-02 1989-05-12 Murata Mfg Co Ltd Multilayer circuit board
JPH0421993A (en) * 1990-05-16 1992-01-24 Nec Corp Storage device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4963964A (en) * 1972-10-27 1974-06-20
JPS5615098A (en) * 1979-07-18 1981-02-13 Ngk Spark Plug Co Low dielectric multilayer ceramic substrate
JPS62101453A (en) * 1985-10-29 1987-05-11 Nec Corp Manufacture of ceramic electronic parts
JPS63249394A (en) * 1987-04-06 1988-10-17 日本電気株式会社 Multilayer circuit board
JPH01120095A (en) * 1987-11-02 1989-05-12 Murata Mfg Co Ltd Multilayer circuit board
JPH0421993A (en) * 1990-05-16 1992-01-24 Nec Corp Storage device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139130A (en) * 1994-11-09 1996-05-31 Hitachi Ltd Semiconductor device
WO2003022571A1 (en) * 2001-09-13 2003-03-20 Motorola, Inc., A Corporation Of The State Of Delaware Process for the production of patterned ceramic green-sheets and multilayered ceramic devices
JP2006185989A (en) * 2004-12-27 2006-07-13 Murata Mfg Co Ltd Circuit board and its manufacturing method
JP2006196832A (en) * 2005-01-17 2006-07-27 Kyocera Corp Multilayer wiring board
JP4606181B2 (en) * 2005-01-17 2011-01-05 京セラ株式会社 Multilayer wiring board
US10499506B2 (en) 2016-03-11 2019-12-03 Murata Manufacturing Co., Ltd. Composite substrate and method for manufacturing composite substrate
US11140778B2 (en) 2018-03-02 2021-10-05 Murata Manufacturing Co., Ltd. Multilayer ceramic substrate and method of manufacturing multilayer ceramic substrate

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