JPH0653412A - Semiconductor memory device and fabrication thereof - Google Patents

Abstract

PURPOSE:To eliminate deterioration of hold characteristics caused by a step for forming a fine contact hole connecting between a storage electrode and source drain region of a stacked capacitor type DRAM. CONSTITUTION:A contact hole connecting between a storage electrode and a source drain region is made, a first conductor film 11 and a first coating 12 are laminated sequentially on an interlayer insulation film interposed between the storage electrode and the source drain region, and then the first conductor film 11 and the first coating 12 are etched into a predetermined pattern thus forming a recess 13. A spacer 14 is formed on the inner wall part of the recess and a fine contact hole is made, while surpassing the resolution limit of photolithographic technology, with the first conductor film 11a and the spacer 14 as masks thus ensuring a margin between the contact hole and the source drain region 5-1 while suppressing junction leak current. This constitution enhances hold characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor structure and a method of forming a dynamic random access memory (DRAM).

[0002]

2. Description of the Related Art Since the cell area is reduced with the high integration of DRAMs, various attempts have been made to increase the ratio of cell storage capacity to cell area.
Miniaturization is promoted. In particular, in a stacked capacitor type DRAM, a C.I. O. B (Capacitor over bit line (Capacito
r Over Bitline) 16M D cell structure
It has been adopted from RAM, and sidewall spacer type contact holes have been devised with the miniaturization of contact holes.

FIG. 5 is a sectional view of a conventional stacked capacitor type DRAM cell having a high aspect contact, and FIGS. 6A and 6B are sectional views in the order of manufacturing steps thereof. Hereinafter, description will be given with reference to these drawings.

A known LOCO is formed on the P-type silicon substrate 1.
The field insulating film 2 is formed by using the S method, and the gate insulating film 3, the gate electrodes 4-1, ...
Are sequentially formed, and N-type impurities are introduced on both sides of the gate to form the source / drain-in regions 5-1 and 5-2 in a self-aligned manner. A first interlayer insulating film 7 is deposited on the entire surface of the substrate, and contact holes 7 are formed on the source / drain regions 5-2.
And the bit line 8 is formed. The second interlayer insulating film is opened to form a contact hole 21 for electrically connecting the storage electrode 1 and the source / drain region 5-2.
At this time, due to the resolution limit of the photolithography technique, the source / drain region 5-2 and the gate electrode 4-1 are formed.
On the other hand, since the contact hole 21 cannot secure a sufficient margin, as shown in FIG.
Since the contact hole 2 is opened above, N-type impurities are introduced into the inside of the contact hole 21 to form the impurity diffusion layer 20 to reduce the junction leakage current. An insulating film having good step coverage is grown on the entire surface of the substrate and well-known anisotropic dry etching is performed to form an insulating spacer 19 on the side surface of the contact hole 21 to form a contact hole 21a. Then, the storage electrode 16 is formed in a predetermined pattern,
A capacitor insulating film 17 and a plate electrode 18 are sequentially laminated and patterned to form a capacitor.

[0005]

This conventional storage electrode 1
6 and the method of forming the contact hole 21a for electrically connecting the source / drain region 51 with each other, as the contact 21a has a high aspect ratio, the source due to the diffusion of phosphorus of the polysilicon film 6 forming the storage electrode 16 Impurity diffusion into the P-type silicon substrate near the drain region 5-1 is insufficient and junction leakage current increases. Therefore, after the contact hole 21 is opened, ion implantation is performed and the impurity diffusion layer region 20 is formed.
Need to be formed. However, if the contact hole 21 is opened so as to hang on the gate electrode 4-1, transistor characteristics are changed by in-implantation for reducing the junction leakage current, so that sufficient ion implantation is impossible.

Further, in the method of forming the contact hole 21a,
Crystal defects occur in the source / drain region 5-1 due to anisotropic dry etching for forming the contact hole 21 and anisotropic dry etching for forming the insulating spacer 19 on the side surface of the contact hole 21. Since it is difficult to sufficiently reduce the junction leakage current, there was the problem that the hold characteristics deteriorated.

According to another aspect of the present invention, there is provided a semiconductor memory device, wherein a gate electrode selectively covering the surface of a semiconductor substrate via a gate insulating film and a channel region below the gate electrode are sandwiched between the semiconductor substrate. A switching transistor having a pair of source / drain regions provided on a surface portion, and a surface of at least one interlayer insulating film covering the switching transistor is selectively covered, and the source / drain region of the source / drain region is covered through a contact hole. In a semiconductor memory device including a memory cell including a charge storage capacitor having a storage electrode connected to one side, a first conductor film selectively deposited on a surface of the interlayer insulating film and having a predetermined opening, A spacer provided on the side surface of the opening for self-aligning the first conductor film with the opening with the spacer; And Ntakuto hole, filling the contact hole, is that has the storage electrode and a second conductive film covering the spacer and the first conductor film.

The method of manufacturing the semiconductor memory device is
A switching transistor having a pair of source / drain regions provided on the surface of the semiconductor substrate with a gate electrode selectively covering the surface of the semiconductor substrate via a gate insulating film and a channel region below the gate electrode sandwiched therebetween. A step of depositing at least one interlayer insulating film, a step of depositing a first conductor film having an etching rate lower than that of the interlayer insulating film on the entire surface of the uppermost interlayer insulating film, A step of forming a first film on the entire surface of the first conductor film, and the first film and the first film above one of the source / drain regions of the switching transistor by using a photolithography technique.
Forming a recess by removing the conductor film in a predetermined pattern, forming a second coating having an etching rate lower than that of the interlayer insulating film, and forming a spacer on a side surface of the recess; A step of forming a contact hole on the one source / drain region using the conductor film and the spacer as a mask, and a second conductor film that makes ohmic contact with the first conductor film and the source / drain region. And a step of simultaneously etching and removing the first conductor film and the second conductor film into a predetermined pattern to form a storage electrode of a charge storage capacitor.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view of a stacked capacitor type DRAM cell according to a first embodiment of the present invention, FIGS. 2 (a) to 2 (c) and FIG.
(A), (b) is process order sectional drawing for demonstrating the manufacturing method.

As shown in FIG. 2A, for example, a gate insulating film is formed on an element formation region which is defined by forming a field oxide film 2 in an isolation region on a P-type silicon substrate 1 by using a known LOCOS method. Film 3, gate electrodes 4-1, 4-2, ... Made of polysilicon or the like are formed. Next, using the gate electrode and the field oxide film as a mask, arsenic ions or phosphorus ions are implanted to form N @ + type source / drain regions 5-1 and 5-2 in a self-aligned manner. Next, a silicon oxide film is deposited to a thickness of about 100 nm on the entire surface of the substrate as a first interlayer insulating film 5 by a vapor deposition (CVD) method.
A contact hole 7 is opened on the drain region 5-2, a bit line 8 is formed, a BPSG film having a high reflow property is grown as a second interlayer insulating film 9 to a thickness of 400 to 600 nm, and heat treatment is performed. After that, a silicon oxide film is grown to a thickness of about 100 nm to form the third interlayer insulating film 10. Anisotropic dry etching is performed on the third interlayer insulating film 10 as compared with the first interlayer insulating film 6 and the second and third interlayer insulating films 9 and 10. A polysilicon film is deposited to a thickness of about 100 to 200 nm, and the first coating film 12 is formed of a silicon oxide film or the like on the entire surface of the polysilicon film (11) by the CVD method.

After that, the first coating film 1 is formed by known anisotropic dry etching using photolithography technique.
2 and the polysilicon film (11) are sequentially removed by etching to form a recess 13 as shown in FIG. 2 (b). A conductor film or an insulating film (second film), such as a polysilicon film or a silicon nitride film, which has a smaller etching rate than the first, second, and third interlayer insulating films and has good step coverage, is grown by a CVD method. Then, anisotropic dry etching is performed using the first coating film 12 as a mask to form a spacer 14 on the inner wall of the recess 13 as shown in FIG. Then, using the polysilicon film (11) and the spacer 14 as a mask, anisotropic dry etching is performed on the entire surface,
As shown in FIG. 3A, the contact holes 15 are formed by etching away the first to third interlayer insulating films. At this time, the first coating film 12 is also removed by etching at the same time, and the etching rate of the polysilicon film (11) is small, so that the first to third interlayer insulating films are protected. The height of the spacer 14 becomes lower and becomes the spacer 14a.

After that, as shown in FIG. 3B, a polysilicon film is grown as the second conductor film 16 to a thickness of about 200 nm by a CVD method, and then a phosphorus diffusion method is applied to the polysilicon film by a photolithography technique. Membrane (11),
By simultaneously etching and removing the polysilicon film (16) by anisotropic dry etching, a storage electrode composed of the first conductor film 11a and the second conductor film 16 is formed, and as shown in FIG. Then, a polysilicon film to be the plate electrode 18 is deposited on the capacitor insulating film 17 and the capacitor insulating film covering the storage electrodes, phosphorus is diffused, and patterning is performed in a predetermined shape by a photolithography technique.

Since a hole is formed in the first conductor film 11 formed on the third interlayer insulating film 10 and a spacer is provided on the side surface thereof and then the contact hole 15 is formed, the contact hole 1 is formed.
5 and the source / drain region 5-1 can be easily secured. Further, it is possible to prevent the peripheral portion of the source / drain region 5-1 from being damaged during etching, so that the junction leakage current is reduced and the hold characteristic of the memory cell is improved.

FIG. 4 is a sectional view showing a DRAM cell according to the second embodiment of the present invention.

In this embodiment, since the spacer is projected above the first conductor film 11b, the surface area of the second conductor film 16a is increased and the storage capacity can be increased. Such a structure has an overetching amount of anisotropic dry etching for forming the spacer 14 on the side surface of the recess 13 in FIG. 2B and a spacer by anisotropic dry etching for forming the contact hole 15. This can be achieved by increasing the thickness of the first coating film 12 formed on the polysilicon film (11) from the etching amount of 14.

[0015]

As described above, according to the present invention, the first conductor film having a smaller etching rate than the interlayer insulating film is formed on the interlayer insulating film between the charge storage capacitor and the switching transistor. And forming a first coating on the first conductive film, and then etching the first conductive film and the first coating in a predetermined pattern above one of the source / drain regions of the switching transistor. The recess is removed to form a recess, and a spacer made of a material having a smaller etching rate than the interlayer insulating film is formed on the inner wall of the recess.
By opening a minute contact hole on one of the source / drain regions using the spacer and the first conductor film as a mask, a margin between the contact hole and the source / drain region is secured, and the source / drain region is damaged by etching. Is reduced, the junction leakage current can be reduced. Moreover, the surface area of the storage electrode is increased by projecting the spacer above the first conductor film, and the storage electrode capacitance is increased. As described above, the hold characteristic of the semiconductor memory device is improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a DRAM cell according to a first embodiment of the present invention.

2A to 2C are explanatory views of the manufacturing method of the first embodiment.
It is a process order sectional view divided and shown in (c).

3A to 3C are sectional views in order of the processes, which are illustrated by dividing them into (a) and (b) for explaining a post-process corresponding to FIG.

FIG. 4 is a sectional view showing a DRAM cell according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a DRAM cell in a conventional example.

6A and 6B are explanatory views of a manufacturing method in a conventional example (a),
It is a process order sectional view divided and shown in (b).

[Explanation of symbols]

1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4-1, 4-2 Gate electrode 5-1 and 5-2 Source / drain region 6 First interlayer insulating film 7 Contact hole 8 Bit line 9 Second Interlayer insulating film 10 Third interlayer insulating film 11, 11a, 11b First conductor film (polysilicon film) 12 First coating 13 Recesses 14, 14a, 14b Spacer 15 Contact hole 16 Second conductor film 17 , 17a Capacitor insulating film 18, 18a Plate electrode 19 Insulating spacer 20 Impurity diffusion region 21, 21a Contact hole

Claims (3)

[Claims] 1. A pair of source / drain regions provided on a surface portion of the semiconductor substrate with a gate electrode selectively covering the surface of the semiconductor substrate via a gate insulating film and a channel region below the gate electrode sandwiched therebetween. And a charge storage capacitor having a storage transistor which selectively covers the surface of at least one interlayer insulating film covering the switching transistor and which is connected to one of the source / drain regions through a contact hole. A semiconductor memory device including a memory cell including: a first conductor film selectively deposited on a surface of the interlayer insulating film and having a predetermined opening; and an opening side surface of the first conductor film. A spacer provided on the contact hole, the contact hole that self-aligns with the opening with the spacer, and the contact hole is filled, A semiconductor memory device having the storage electrode including the spacer and a second conductor film covering the first conductor film. 2. The semiconductor memory device according to claim 1, wherein the height of the spacer is larger than the thickness of the first conductor film. 3. A pair of source / drain regions provided on the surface of the semiconductor substrate with a gate electrode selectively covering the surface of the semiconductor substrate via a gate insulating film and a channel region below the gate electrode sandwiched therebetween. And a step of depositing at least one interlayer insulating film, and depositing a first conductor film having an etching rate smaller than that of the interlayer insulating film on the entire surface of the uppermost interlayer insulating film. And a step of forming a first coating on the entire surface of the first conductor film, and the first coating on one of the source / drain regions of the switching transistor using a photolithography technique. And a step of removing the first conductor film in a predetermined pattern to form a recess, and a second step having an etching rate smaller than that of the interlayer insulating film. Forming a coating film to form a spacer on the side surface of the recess; forming a contact hole on the one source / drain region using the first conductor film and the spacer as a mask; A second conductor film in ohmic contact with the first conductor film and the source / drain regions, and the first conductor film and the second conductor film are simultaneously etched and removed into a predetermined pattern. And a step of forming a storage electrode of a charge storage capacitor.