JPH0652883B2 - Synchronization maintaining device in SS-TDMA satellite communication system - Google Patents

Description

The present invention relates to a synchronization maintaining device in an SS (satellite switching) -TDMA (time division multiple access) satellite communication system, and particularly to a drift value of a clock source mounted on a satellite. Measurement technology.

(Prior Art) As is well known, the TDMA satellite communication method is a TDMA generated by a reference station by periodically dividing time on a satellite, that is, dividing a TDMA frame by time division and allocating it to each earth station.
This is a method in which each earth station (slave station) that generates its own TDMA frame timing based on the frame timing sends the burst of its own station within the allocated time.

And, the SS-TDMA satellite communication system is based on the above TDMA.
It was devised to further improve the frequency utilization efficiency in satellite communication systems.It configures a large number of spot beams for transmission / reception on the satellite by frequency reuse, and switches connection between a large number of transponders and a large number of transmission / reception beams. In addition to the matrix switch mounted on the satellite, a synchronization maintaining device is provided in the reference station to synchronize the switching cycle of the switching sequence on the satellite (hereinafter referred to as "switch frame") with the cycle of the TDMA frame, and This is a system in which the burst transmission timing of each earth station (slave station) operating in the normal TDMA system without considering its existence is such that the own beam and the target beam are connected on the satellite.

By the way, as described above, in the SS-TDMA satellite communication system, the synchronization maintaining control of the switch frame and the TDMA frame has important significance, but the stability of the clock source of the matrix switch is provided in the reference station. Since it is significantly inferior to the stability of the clock source of, there are the following problems.

That is, the synchronization maintaining device has a high-stability clock source with a long-term stability of about 10 ⁻¹¹ , uses this highly stable clock to generate a TDMA frame, and maintains synchronization with the switch frame on the satellite. is doing. Therefore, each earth station (subordinate station) is generating the TDMA frame timing in synchronization with the clock of the clock source provided in the synchronization maintaining device.

On the other hand, the clock source mounted on the satellite is guaranteed to have a stability of about 10 ^-9 at most due to its weight, reliability, and other constraints. The deviation of the oscillation frequency from the clock source becomes so large that it cannot be ignored over time. SS-TDM
In the case of the A satellite communication system, this deviation in oscillation frequency (that is, clock drift) is fatal for the system.

Therefore, in the SS-TDMA satellite communication system, generally, the third
As shown in the figure, the drift of the satellite clock source can be corrected in the synchronization maintenance control.

That is, FIG. 3 is a system diagram of synchronization maintenance control of the SS-TDMA satellite communication system. Matrix switch on the satellite 3
1.In addition to the clock source 32 and the like, a telemetry receiver 33 is mounted, and a reference station including a synchronization maintaining device 34, a high stability clock source 35 and the like on the ground, and a command transmitting station including a telemetry transmitter 36. Will be placed.

The synchronization maintaining device 34 controls the transmission timing with the matrix switch 31 on the satellite while measuring the clock drift value of the satellite onboard clock source 32. The measured clock drift value is command-transmitted from the telemetry transmitter 36 and received by the satellite-mounted telemetry receiver 33, and the oscillation frequency of the clock source 32 is controlled.

The clock drift value is conventionally measured by, for example, FIG. 4 or FIG.
Although it is performed as shown in the figure, this will be described later, and first, the transmission timing control will be briefly described.

The satellite-mounted matrix switch 31 performs connection switching of a plurality of beams according to a predetermined sequence, and the same sequence is repeated for each TDMA frame.
In the switching sequence of the matrix switch 31, a connection is set in advance at least once in each frame so that the beam is looped back (loopback) at the same time. This time slot is a window for maintaining synchronization (“ (Shown as "synchronization window"). The synchronization maintaining device 34 uses this synchronization window to perform a synchronization burst (referred to as a metric burst or a metering burst).
Is looped back and transmitted, the start timing of the switching sequence of the matrix switch 31 is detected, and frame synchronization is established.

As shown in the figure, the synchronization burst (metric burst) is composed of three signal areas, and the recovery signal CBT for carrier recovery and clock recovery is provided in the previous signal area.
A unique word UW indicating the character of the signal is set in the signal area of R in the middle, and a specific bit pattern (called a metric pattern) for synchronization control is set in the signal area of the latter. Then, the metric pattern is divided into a first half portion and a second half portion, and the boundary position thereof serves as a reference position for transmission position error detection.

That is, the synchronization maintaining device 34 controls so that the latter half of the metric pattern area of the synchronization burst is cut off at the trailing edge of the synchronization window on the satellite and transmits the synchronization burst. Then, the transmission pattern and the reception pattern of the synchronization burst are compared with each other to find the position where the synchronization burst is cut off, and the transmission timing is controlled so that the position is always constant. This control amount is given by the number of controlled symbols, that is, the number of symbol clocks.

Now, the variable factors in the transmission timing control described above include the drift of the clock source on the above-mentioned satellite in addition to those due to the Doppler of the satellite, but if the satellite does not have the Doppler, the transmission timing of the synchronization maintaining device 34. The control value, or symbol clock number, should be equal to the satellite clock drift value. That is, in order to measure the clock drift value, the important point is how to remove the Doppler component of the satellite and perform the measurement. Conventionally, the following two methods are roughly performed. That is, a method of adding hardware (circuit) and directly removing the Doppler component for measurement (Fig. 4)
And a method of adding software and performing measurement by arithmetic processing (FIG. 5).

FIG. 4 is a principle diagram (FIG. 4 (a)) of clock drift value measurement in which the Doppler component is directly removed by adding hardware (circuit) and a block diagram of the measurement circuit (FIG. 4).
(b)).

As shown in FIG. 4 (b), this measuring circuit includes the high stability clock source 35, a counter 41 for generating a reference control frame from the highly stable clock, and a basic section 40 of the synchronization maintaining device. And a measuring unit 42 for measuring the clock drift value by receiving the output of the counter 41 (reference control frame) and the transmission control frame and the reception control frame from the basic unit 40.

In FIG. 4 (a), the timing of the reference control frame is constant even if the satellite position changes at certain times T1 and T2. On the other hand, the respective timings of the transmission control frame and the reception control frame change due to the influence of satellite Doppler and clock drift at certain times T1 and T2, and have, for example, related timings as shown in the figure.

Now, the timing of the transmission control frame at time T1 is T _t (T1), the timing of the reception control frame is T _r (T1), and the timing at time T2 is T _t (T2) and T _r (T2). For example, these are the time lengths from the reference control frame, but the average value _Tm (T) of timings _Tt (T1) and _Tr (T1)
1) becomes T _m (T1) = (T _t (T1) + T _r (T1)) / 2 (1), and the average value T _m (T2) at time T2 is T _m (T2) = (T _t (T2) + T _r (T2)) / 2 (2), and both should be the same value if there is no drift in the clock source mounted on the satellite. That is,
The average values T _m (T1) and T _m (T2) have the effects of satellite Doppler removed.

Therefore, in the measuring unit 42, first, the average values T _m (T1) and T _m (T2) are calculated by the above equations (1) and (2), and then the difference value ΔT between them is calculated as ΔT = T _m (T2 ) -T _m (T1) = [(T _t (T2) + Tr (T2))-(T _t (T1) + T _r (T1))] / 2 ……
Obtain as in (3). That is, this difference value ΔT gives the drift value of the satellite clock source. This method enables highly accurate measurement.

Next, FIG. 5 is a configuration example of a synchronization maintaining device for measuring a clock drift value by adding software. That is, in FIG. 5, a clock drift value measuring unit 57 is provided. The operation of the synchronization maintaining device is as described above,
First, the signal flow will be described with reference to FIG. Although not shown, the high-stability clock source 35 supplies a clock to each unit such as the transmission timing generation unit 54, the transmission burst generation unit 56, and the reception timing generation unit 53 in the synchronization maintaining device.

In FIG. 5, the reception burst received by the synchronization maintaining device.
10 is input to the burst detection unit 51, and the burst detection unit 51
From this, the reception burst information 11 is input to the reception burst buffer 52, and the burst detection signal 12 is input to the reception timing generation unit 53.

In the reception burst buffer 52, the reception data 13 is extracted from the reception burst information 11 and the transmission timing control unit 54
Output to.

The reception timing generation unit 53 generates reception timing (that is, the timing signal of the reception TDMA frame) 14 from the burst detection signal 12, and outputs the reception timing 14 to the transmission timing control unit 54.

The transmission timing control unit 54 extracts the metric pattern from the reception data 13 and compares it with the set pattern. As a result of the comparison, the cut position of the metric pattern is determined, the transmission timing control information 16 is output to the transmission timing generation unit 55 in order to control the transmission timing so that the position is always constant, and the clock drift value is set. It is also output to the clock drift value measuring unit 57 for measurement.

In the transmission timing generation unit 55, the transmission timing control unit 54
The transmission timing (that is, the timing signal of the transmission TDMA frame) 17 is generated according to the transmission timing control information 16 from, and is output to the transmission burst generation unit 56.

In the transmission burst generation unit 56, the input transmission timing 17
A transmission burst 18 is generated in synchronization with the.

The above is the transmission timing control. Of course, the transmission timing control information 16 obtained in this operation process includes a Doppler component.Therefore, in order to remove this Doppler component, the clock drift value measurement unit 57 uses the transmission timing control information 16 Store for a certain period of time. As a result, since the transmission timing change history due to the clock drift is obtained, the clock drift value measuring unit 57 calculates the Doppler component from the Doppler information of the satellite input from the outside at regular time intervals and the accumulated change history to calculate the Doppler component. The excluded clock drift value is measured. This method has the advantage that no special hardware circuit like the one described above is required.

(Problems to be Solved by the Invention) However, the above-described conventional clock drift measuring method for the synchronization maintaining device has the following problems.

That is, in the method shown in FIG. 4, the Doppler component can be directly removed, so that there is an advantage that the measurement can be performed with high accuracy, but a special hardware circuit is provided in the synchronization maintaining device for measuring the clock drift value. It must be provided, and the device scale increases.

Further, the method shown in FIG. 5 has an advantage that no special hardware circuit is required unlike the method shown in FIG. However, since the accuracy of satellite Doppler information cannot generally be expected to be high, the accuracy is inferior to the method shown in FIG. 4 in the configuration in which the accuracy of the satellite Doppler information given to the synchronization maintaining device directly affects the clock drift value. I can only measure. Further, since the acquisition time interval of the satellite Doppler information is a unit of "minute" such as 10 minutes even if it is short, it is impossible to perform the measurement in a short time.

The present invention has been made by paying attention to such characteristics of both types, and provides a synchronization maintaining device capable of directly removing the Doppler component of the satellite without providing a special measurement circuit and performing highly accurate measurement. The purpose is to

(Means for Solving the Problems) In order to achieve the above object, the synchronization maintaining device in the SS-TDMA satellite communication system of the present invention has the following configuration.

That is, the synchronization maintaining device in the SS-TDMA satellite communication system of the present invention is a synchronization maintaining window formed in a switching sequence of switches for performing connection reconfiguration between a large number of transponders and a large number of transmission / reception beams in a satellite. At the TD, the synchronization burst is looped back and forth via the satellite line, and the received synchronization burst is used as a reference for reception on the ground side
The MA (time division multiple access) frame period is generated, and the transmission TDMA frame timing is controlled based on the comparison result of the synchronization bit patterns of the transmitted and received synchronization bursts. SS (satellite switching) for maintaining synchronization with the TDMA frame period on the side-in a synchronization maintaining device in a TDMA satellite communication system; the number of symbol clocks, which is a control amount within a certain fixed period, corresponds to the movement of a synchronization burst to be received. Means for accumulating the number of symbol clocks required to control the reception TDMA frame timing during the fixed time in order to synchronize the reception TDMA frame timing on the terrestrial side; the number of symbol clocks as a control amount within the fixed period And the transmission / reception bit pattern of the synchronization burst The symbol clock required to control the transmission TDMA frame timing during the fixed time in order to maintain the synchronization between the cycle of the switching sequence of the satellite-mounted switch and the terrestrial TDMA frame timing based on the comparison result A means for accumulating the number; outputting the drift value of the clock source mounted on the satellite obtained by halving the difference between the number of symbol clocks and the received TDMA frame timing accumulated within the certain period. It is characterized by having means and ;.

(Operation) Next, the operation of the synchronization maintaining device in the SS-TDMA satellite communication system of the present invention configured as described above will be described with reference to FIG.

FIG. 1 is a diagram for explaining the principle of clock drift value measurement according to the present invention. That is, as shown in FIG. 1 (a), even if the position of the satellite changes at certain times T1 and T2, if the oscillation frequency of the satellite clock source does not drift, the start timing SOTF (T _n ) and the position of the intermediate point T _c of the start timing SORF (T _n ) of the received frame do not change.

On the other hand, if there is a drift in the satellite clock source, the first
As shown in FIG. 6B, a difference of only the clock drift value ΔT appears between the intermediate points T _c (T1) and T _c (T2).
Then, the difference between the transmission frame start timing SOTF (T1) and the transmission frame SOTF (T2) at a certain time T1 and T2 is ΔT _tx , and the reception frame start timing SORF is
Letting ΔT _rx be the difference between (T1) and the same SORF (T2), the relationship ΔT = (ΔT _tx −ΔT _rx ) / 2 (4) holds.

Therefore, in the present invention, the number of symbol clocks required to control the transmission frame timing is accumulated from a certain time T1 to a certain time T2 in order to maintain synchronization with the switching sequence of the switch mounted on the satellite, and the ΔT is stored. _{In addition} to obtaining _tx , the number of symbol clocks required to control the reception hum timing between a certain time T1 and a certain time T2 for synchronizing with the movement of the received synchronization burst is accumulated to obtain ΔT _rx . The satellite clock drift value ΔT is calculated based on the equation (4).

Thus, according to the present invention, the timing of the transmission TDMA frame and the timing of the reception TDMA frame, which have a fixed relationship with each other, is used, so that the clock drift value can be measured without providing a special circuit by hardware. It is possible and does not increase the device scale.

Further, compared to the method using satellite Doppler data, the Doppler component can be removed easily and in a relatively short time, and the clock drift value can be measured with high accuracy.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 shows a synchronization maintaining device in an SS-TDMA satellite communication system according to an embodiment of the present invention. In FIG.
The synchronization maintaining device according to the present invention is basically the same as the conventional device shown in FIG.
In order to eliminate the need for 57 and measure the clock drift value thereof, the reception timing generation unit 3 and the transmission timing control unit 4
And some functions have been added.

That is, the reception timing generation unit 3 generates reception timing control information 15 in addition to the reception timing 14 and outputs them to the transmission timing control unit 4. Here, the reception timing control information 15 has the number of symbol clocks required for control from the previous reception timing to the current reception timing.

Further, the transmission timing control section 4 outputs the transmission timing control information 16 to the transmission timing generation section 55 as described above, and also accumulates the transmission timing control information 16 and the reception timing control information 15 for a certain period. Here, the transmission timing control information 16 has the number of symbol clocks required for control from the previous transmission timing to the current transmission timing. Therefore, accumulating the reception timing control information 15 and the transmission timing control information 16 for a certain period means that the ΔT _rx and ΔT _tx are obtained. Then, the transmission timing control unit 4 calculates the above equation (4) and outputs the clock drift value 19.

(Effects of the Invention) As described above, according to the synchronization maintaining apparatus in the SS-TDMA satellite communication system of the present invention, the timings of the transmission TDMA frame and the reception TDMA frame which have a certain mutual relation are used. Therefore, the clock drift value can be measured without providing a special circuit by hardware, and the Doppler component can be removed easily and in a relatively short time compared to the method using satellite Doppler data. Therefore, there is an effect that the clock drift value can be measured with high accuracy.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of clock drift value measurement according to the present invention, and FIG. 2 is an SS-TDMA according to an embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a synchronization maintaining device in a satellite communication system, FIG. 3 is a system diagram of synchronization maintaining control of an SS-TDMA satellite communication system, and FIG. 4 is an explanatory diagram of the principle of a conventional clock drift value measuring method (addition of hardware). FIG. 5 is a block diagram of the configuration of a conventional synchronization maintaining device (measurement method by adding software). 3 ... Reception timing generator, 4 ... Transmission timing controller, 31 ... Matrix switch, 32 ... Clock source,
33 …… Telemetry receiver, 34 …… Synchronizer, 35 ……
High stability clock source, 36 …… Telemetry transmitter, 51 ……
Burst detector, 52 ... Receive burst buffer, 55 ...
Transmission timing generator, 56 ... Transmission burst generator.

Claims (1)

[Claims] 1. A synchronization burst is looped back through a satellite line in a synchronization maintaining window formed in a switch switching sequence for switching connection between a large number of transponders and a large number of transmission / reception beams in a satellite. Reception TD on the ground side based on the synchronization burst that was transmitted / received and received
The MA (time division multiple access) frame period is generated, and the transmission TDMA frame timing is controlled based on the comparison result of the synchronization bit patterns of the transmitted and received synchronization bursts, thereby synchronizing the switching sequence of the switch mounted on the satellite and the ground. SS (satellite switching) for maintaining synchronization with the TDMA frame period on the side-in a synchronization maintaining device in a TDMA satellite communication system; the number of symbol clocks, which is a control amount within a certain fixed period, corresponds to the movement of a synchronization burst to be received. Means for accumulating the number of symbol clocks required to control the reception TDMA frame timing during the fixed time in order to synchronize the reception TDMA frame timing on the terrestrial side; the number of symbol clocks as a control amount within the fixed period And the transmission / reception bit pattern of the synchronization burst The symbol clock required to control the transmission TDMA frame timing during the fixed period in order to maintain the synchronization between the cycle of the switching sequence of the satellite-mounted switch and the terrestrial TDMA frame timing based on the comparison result Means for accumulating the number; 1 / the difference between the number of symbol clocks for the received TDMA frame timing and the number of symbol clocks for the transmitted TDMA frame timing accumulated within the certain period
2. A means for outputting the drift value of the clock source mounted on the satellite, which is obtained by the step 2), and a synchronization maintaining device in the SS-TDMA satellite communication system.