JPH065068A - Dynamic ram - Google Patents

Abstract

PURPOSE:To obtain a dynamic RAM wherein it outputs latched data at a data latch circuit when a memory cell is active, it eliminates a dummy operation between a readout operation and a write operation when a pipeline mode which latches stored data in the data latch circuit is executed when the memory cell is on standby and it executes the pipeline mode with good efficiency in direct conjunction with the readout operation and the write operation. CONSTITUTION:The title RAM is provided with the following: a data latch circuit which latches data stored in a memory cell; and an output buffer which outputs the latched data to the outside. When the memory cell 1 is on standby, data (n) in the memory cell 1 is latched in the data latch circuit 7; a transfer- gate transistor 10 between the data latch circuit 7 and the output buffer 8 is turned on; the data (n), at the memory cell 1, which is stored in the data latch circuit 7 is output to the outside via the output buffer 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic RAM.
With regard to the above, in particular, in order to increase the speed, a pipeline mode for externally outputting the data already read from the memory cell specified one cycle before the cycle specifying the predetermined data when reading the stored data from the predetermined memory cell Relates to a dynamic RAM that can be executed.

[0002]

2. Description of the Related Art In a dynamic RAM, in addition to the normal operation mode, various kinds of operation modes have been realized in actual products as operation modes for increasing the speed. One of them is called pipeline mode. Here, the pipeline mode will be described.

FIG. 3 is a block diagram of a conventional dynamic RAM capable of executing the pipeline mode. In the figure, 1 is a memory cell of the address (R _{n, C n)} specified by the row address Rn column address Cn consists in a capacitor and the transfer gate transistor, the word line WL _n are activated Sometimes data is transferred to the data input / output line 2 or data from the data input / output line 2 is stored.

The data transferred from the memory cell 1 to the data input / output line 2 is amplified by the sense amplifier 3 and then output to the preamplifier 5 via the transfer gate transistor pair 4 to be level-adjusted and further transferred to the transfer gate transistor 6. The data is latched and stored by the data latch circuit 7 via. Then, the data stored in the data latch circuit 7 is externally output via the output buffer 8.

The input data D _in is stored in the memory cell 1 via the input buffer 9, the transfer gate pair 4, and the sense amplifier 3.

Next, the operation at the time of executing the pipeline mode having the above-mentioned configuration will be described with reference to the timing diagram of FIG. The row address strobe signal RAS from the outside is used as a trigger to trigger the row address R
The word line WLn designated by n is activated, the data n is transferred from the memory cell 1 to the data input / output line 2, and is amplified by the sense amplifier 3.

Next, triggered by the fall of the column address strobe signal CAS bar from the outside, the signal y _n specified by the column address Cn is activated, and the transfer gate transistor pair 4 is turned on. Therefore, the data n amplified by the sense amplifier 3 is transferred to the preamplifier 5 via the transfer gate transistor pair 4. The flow of the data signal from the memory cell 1 to the preamplifier 5 is referred to as a data flow A.

The data n output from the preamplifier 5 is
The signal φ activated by the rise of the row address strobe signal RAS bar is used as a trigger to be stored in the data latch circuit 7 via the transfer gate 6. A flow of the data signal from the preamplifier 5 to the data latch circuit 7 is referred to as a data flow B.

The data latch circuit 7 is indispensable for executing the pipeline mode. In one cycle S _n , there is the above-described data signal flow (data flow A + data flow B) and another data signal flow (data flow C). This data flow C is a data signal flow in which the data (n-1) stored in the data latch circuit 7 is output to the outside via the output buffer 8 in the previous cycle S _n-1 .

Therefore, the data output to the outside in the cycle S _n is the data of the address address (R _n-1 , C _n-1 ) designated in the previous cycle S _n-1 . In this mode, when reading from the memory cell 1, the row address R _n and the column address C _n designating the memory cell 1 and the data (n−1) output from the output buffer 8 to the outside are deviated by one cycle. However, since the access time is determined only by the path of the data flow B, the access time of the dynamic RAM can be dramatically improved.

As described above, although the pipeline mode in which the access time is dramatically improved can be achieved, as can be seen from FIG. 4, when reading from the memory cell 1, the row address R _n and the row address R _n for designating the memory cell 1 and Column address C _n
And the data (n-
Since 1) and are shifted by one cycle, in the case of performing the writing operation of the data (n + 1) after the read operation in the cycle S _n, if in the next cycle S _{n + 1} cycle S _n data (n + 1) When writing is attempted, the data n of the memory cell 1 stored in the data latch circuit 7 is written.
Will not be output to the outside.

[0012] In order to prevent this, in the case of writing operation of the data (n + 1) after the read operation in the cycle S _n performs a dummy operation in the next cycle S _{n + 1} cycle S _n. That is, in the cycle S _{n + 1} , the data rat circuit 7 outputs the data n of the memory cell 1 at the address (R _n , C _n ) specified in the cycle S _n . Then, the write operation is performed in the next cycle S _{n + 2} .

[0013]

As described above, in the conventional dynamic RAM, when the write operation is performed after the read operation in the pipeline mode, the dummy operation must be performed between the read operation and the write operation. Therefore, there was a problem that the efficiency was low.

The present invention has been made to solve the above problems, and eliminates the dummy operation between the read operation and the write operation, and directly connects the read operation and the write operation to efficiently implement the pipeline mode. The purpose is to obtain a dynamic RAM that can be implemented.

[0015]

A dynamic RAM according to the present invention comprises a data latch circuit for storing data stored in a memory cell and an output buffer for externally outputting the stored data. In a dynamic RAM that outputs accumulated data of a data latch circuit and accumulates the stored data in the data latch circuit during standby of the memory cell, the stored data accumulated in the data latch circuit during standby of the memory cell is described above. The output buffer is provided with control means for controlling output.

[0016]

In the dynamic RAM according to the present invention, the stored data is stored in the data latch circuit and the stored data is output from the data latch circuit when the memory cell is on standby.

[0017]

1 is a block diagram of the present invention. A difference from the conventional example shown in FIG. 3 is that a new transfer gate 10 having a signal ψ as a control signal is provided between the data latch circuit 7 and the output buffer 8. Further, the signal ψ is input to the output buffer 8.

Next, the operation of this embodiment in the pipeline mode will be described with reference to the timing diagram of FIG. In cycle S _n, the memory cell 1 becomes active word line WL _n the fall of the row address strobe signal RAS bar to a trigger from the outside is activated, data n from the memory cell 1 is output.

In cycle S _n , when the external row address strobe signal RAS bar is precharged, that is, when word line WL _n is inactive and memory cell 1 is in the standby state, signal φ is activated. Then, the transfer gate pair 4 is turned on, the signal ψ is activated, the transfer gate 10 is turned on, and the data n read from the memory cell 1 is latched via the data input / output line 2 to the transfer gate 6. It is stored in the circuit 7 (data flow B).

Further, when the row address strobe signal RAS bar is precharged in the cycle S _n, the data n stored in the data latch circuit 7 is transferred to the output buffer 8 (data flow D) and output to the outside.

That is, in one cycle S _n , the data flow B in which the data n is latched and accumulated in the data latch circuit 7 and the accumulated data n are externally transmitted from the data latch circuit 7 via the output buffer 8. And the data flow D is output.

[0022] Therefore, output from the memory cell 1 in the cycle S _n When writing operation after performing the read operation of the data n, the data n is outside the end of the precharge period of the read operation in the cycle S _n Therefore, the write operation can be performed without the dummy operation after the cycle S _n , and the read operation and the write operation can be directly connected.

Further, there is an advantage that the data signal can be exchanged with the external system even when the row address strobe signal RAS bar is in the precharged state.

[0024]

As described above, according to the present invention, when the memory cell is in the standby mode, the storage data is stored in the data latch circuit and the stored data is output from the data latch circuit. When performing the write operation after the read operation of the memory cell at the time of execution, it is not necessary to perform the dummy operation before the write operation, the read operation and the write operation can be directly connected, and at the time of standby of the memory cell This has the effect of exchanging data with the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram for explaining the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional dynamic RAM.

FIG. 4 is a timing diagram for explaining the operation of the conventional dynamic RAM.

[Explanation of symbols]

 1 memory cell 7 data latch circuit 8 output buffer 10 transfer gate

[Procedure amendment]

[Submission date] December 10, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012] In order to prevent this, in the case of writing operation of the data (n + 1) after the read operation in the cycle S _n performs a dummy operation in the next cycle S _{n + 1} cycle S _n. That is, in the cycle S _{n + 1,} and outputs the cycle _S address specified by _{n (R} n, _{C n)} data n of the memory cell 1 from Detara' latch circuit 7. Then, the write operation is performed in the next cycle S _{n + 2} .

Claims (1)

[Claims] 1. A data latch circuit for accumulating data stored in a memory cell, and an output buffer for externally outputting the data accumulated, wherein the data latch circuit outputs data accumulated when the memory cell is active, In a dynamic RAM that stores the stored data in the data latch circuit when the cell is on standby, a control means that controls the output of the stored data stored in the data latch circuit when the memory cell is on standby is provided. Dynamic RA featuring
M.