JPH06500223A - Device for connecting a computer to a communication network and method for bit rate adaptation within this device - Google Patents

Abstract

The computer interface for allowing data transfer between the computer (R) and other data peripherals (EA,ED) coupled to the network (OF,PF) comprises a modular interface assembly (SB). The latter has at least one connection at an initial data transfer bit rate. Integral bit rate adaption is used to obtain a higher data transfer bit rate via a parallel computing unit. The computer (R) is connected to the interface assembly (SB) via a multi-bus system (I).

Description

[Detailed description of the invention] Plan on the communication network! [l! The device for connecting the I and the pin training within this device. Methods for adapting The uninvented invention includes an apparatus according to the preamble of claim 1, a method according to the preamble of claim 11, and a method according to the preamble of claim 11. and the application of the method in the above devices.

Basically, two types of subscriber connections are reserved for integrated digital services II (ISDN). Two-base and one-rate connections are defined. -The next rate connection is even better. can be divided into any channel structure. Hl channel structure, HO channel structure, B channel structure A distinction is made between channel structures and mixed structures, where the mixed structure has B channels and H channels. A combination between the O channel and the O channel can be chosen. @'s B51 (0 and Hl cha) Although the data transmitted by the channel has no meaning because it is exchanged through the communication network, (bit-transparent transmission), signaling channel (D channel) Required for forming and tearing down connections within a communications network. Enter the Keikaki system Until now, when connecting SDN subscribers, it has only been possible to connect from base connection or at most H1 Starting from a single rate connection with a channel structure. Maximum transmission rate of 144kBit/s The type of connection via the base connection that allows sending I/- is relatively small per connection unit. This can be realized with low circuit engineering outlay. But the drawback is that the base connection only requires two B channels and one D channel are planned, so each connection unit This is due to the small number of subscriber connections. For example, 30 subscriber connections are required at the same time. If required, 15 connection units must be utilized; On the one hand, high circuit engineering costs increase costs and maintenance costs, and on the other hand, system reduce the reliability of the entire system. Connection via higher rate connection on H1 channel*a The format does allow for a projected transmission rate of 2MBit/s, but if the car has two l5 Can be used for communication between DN subscribers. In other words, transmission occurs within the communication network. This is done bit-transparently over the entire channel bandwidth of the higher rate connection. C.C. According to ITTl-431, users are provided with 30 B channels (base channels) and and one D channel (auxiliary channel) of 64 kBit/s. B-channel structure that allows 30 different subscribers to access the computer at the same time. For interface modules that do not handle higher rate connections in Interface module for handling higher rate connections in H1 channel structure cannot be used.

Therefore, the problem of the present invention is to connect Xll to a public or private digital communication network. If a large number of subscriber equipment connected to the yII can be accessed at the same time, the two units operating at different transmission rates. A pin rate application that can be applied in terminal equipment to enable data exchange between the wire and the wire. The objective is to provide a method for responding to

This problem is solved by the measures listed in the characteristic parts of claims 1 and 11. be done. Advantageous embodiments of the invention are set out in the other claims.

The present invention has the following advantages: A large number of cost-desirable termination devices can be installed simultaneously. may be connected to the central infrastructure via a private or public communications network. this thing is only advantageous in smaller subscriber switching facilities, for example in private networks within enterprises. It can be realized without any special cost even through a public communication network. in an expensive company LAN distribution & I (local area network) equipment is omitted, and instead Existing conductors of private or public networks are used for communication between individual end devices and computers can be done. Furthermore, a compact interface module is used. , which not only significantly improves the overall system reliability (but also reduces costs). be done. Software implementation of bitrate adaptation reduces interface modulation. module hardware can be reduced to common flexible functionality. new pi ) The rate adaptation algorithm or other progressive algorithm can be developed against existing hardware without the need for matching. last This interface module supports all 30 B channels of higher rate connections at the same time. Allows processing channels.

Hereinafter, the present invention will be explained in more detail by way of example with reference to FIG.

Figure 141: To connect many end devices to one total XIl via public communication network Use of the device according to the invention in Figure 2: Connect multiple terminal devices to one device via public and private communication networks. Use of the device according to the invention for connecting FIG. 3, hermitage of the interface module Physical configuration and possible realization Figure 4. Multiple connections in a total of 11 W machine connection systems For interface module personnel Figure 5: Possibility into two stages of the method for the focus rate at applied in the device. capable division FIG. 6: Predetermined numbers per subscriber channel processed by the method of the invention data flow Hawk Figure 7: Two data centers where the data flow is sequentially and alternately filed No. 8 Figure: Data sets at various processing stages of bitrate adaptation proceeding in the second stage Figure 9 – Two searches for synchronizing the processing steps and data flow of the pagination unit Data word of windowed data unit Figure 10: Bits between multiple processing clocks Diagram showing the data flow before the first stage of trait adaptation Figure 11: Data at various stages of the processing clock in preparation for data extraction unit Figure 42: Data with extraction words at various stages of the processing clock during data extraction. Diagram showing the data unit Figure 1 shows the interface with calculation 11R in public digital communication 110F. How the communication network OF works and the interface shows an example of using the module SB. has been widely standardized internationally, and is collectively known as the “Digital Integrated Service Network”. , on the other side directly via a higher rate connection the S/T reference point 5T (3 2) and, on the other side, to computer R via bus system B. has been done. Using purely digital termination equipment ED or using digital and an analog part or a purely analog part via the R reference point RR. Communication 1fOF using the terminal device EA connected to the terminal adapter TA The subscriber of the communication network O via the S reference point SR, preferably via the base connection Enter the connection with F, and furthermore, for example, S/T reference I! ! ? Point ST and interface -Total via Sumosier SB) [JJ! Contact with R. Phases within the communication network OF Corresponding connections are indicated by dashed lines in the drawings.

Total WIi! R communicates with more subscribers or end #i equipment EA and ED simultaneously If so, a corresponding number of B channels must be used simultaneously. Must As the number of B-channels required increases, the economic benefits of higher rate connections increase with the increase in the number of B channels required. The transmission capacity required becomes increasingly obvious compared to the Heath connection. −Next Interface module in which rate connections can be connected directly at the S/T reference point ST Thanks to SB, 30 subscribers can simultaneously perform their communication functions from any location. can be done. Thus total) [IIR is total with end #J equipment El) and (or) EA. For example, the following VANS (Valued Added Network 5service): X, 400 Message handling, 0DA10DI F application, EDT (English, Elect ronic Data Interchange), public data bank, public game network or public information (e.g. at the time of a sales offer inquiry in a department store). News.

To participate in these services, I5DN subscribers must have a terminal access. Combined with adapter TA for digital and analog or pure analog parts EA or pure digital terminal with integrated 15DN connection. It is sufficient to use the terminal terminal device ED.

In Figure 2, the total XIIR is connected to at least one interface module SB. It is connected to a private digital communication 11PF having subscriber switching equipment. Join Switching equipment is often used in business or government, where it is shown in Figure 2. Connection to digital or analog public communications 110F is possible as in . Located within the private range FB and equipped with an interface module SB Calculation 11R is a private communication 11P via a higher rate connection at the S/T access point ST. It is connected to F. Digital and via the termination equipment EA consisting of analogue or pure analogue parts; or Via purely digital termination equipment ED, subscribers of public communications w4OF can also access private communications. Subscribers of the network PF can also access the total xWR. In this way, the calculation The application program is Public Communication I! Connected to IOF or private communication network PF can be accessed from end devices ED and EA via normal communication lines. . Such services within the private range PB are, for example, private electronic mail, private data bases, etc. private network (e.g. via a Te1epac connection TPA to the subscriber TP) central server and warehouse (for programs, backups, etc.) Warehouse management (Meeting site registration and inquiries).

Figure 3 shows a possible realization of the interface module SB. channel allocation unit KZE, parallel page playback PRW and bus matching unit. and BAE. Connect to communication mOF or PF via S/T reference point ST. The channel allocation unit KZE, which is connected to It consists of electronic components. For this purpose, on one side the S/T reference point is ST and a frame synchronizer R3 (UK) on the other side.

A serial transmitter-receiver unit SE is provided which is connected to a frame aligner). It is. The frame synchronizer R3 is connected to the pass-through connection unit DS. 1 to 6 as well as internal interfaces to the various coupling units. If necessary, connect the corresponding coupling unit via S. can be connected to another pass-through unit. Sending-receiving unit SE, frame system The synchronizer R3 and the pass-through unit DS connect to the central calculation via the bus TB. Transmission direction from communication network OF or PF connected to machine ZR to computer R (first In Figure 1), the transmitter-receiver unit SE is transmitted serially via the S/T reference point ST. and further sends these to frame synchronizer R3. give. At the same time as data is received, data transmission in the opposite direction is also started. For example, CCITT Recommendations C.703, G.823.1.431, G-132 and In addition to the transmission functions performed in accordance with G.735 to G.739, Error recognition also takes place in the receiving unit SH. That is, for example, the communication network O In the event of a failure of F or PF or interface module SB, the central computer ZR is alarmed via bus TB. In addition, within the communication mOF or PF The clock used for data transmission in the received serial data flow extracted and also synchronizes the interface module SB with the communication mOF or PF used to. The clock obtained at that time is preferably the communication wROF or an interface module SB that must be operated synchronously with the PF. Assigned to the components of Frame synchronizer-R3 is, for example, CC[T Frame boundaries, i.e. frames that are coded according to Recommendation G.732 Recognize beginnings and endings. Additionally, the frame synchronizer-R3 is It can be monitored and initialized by computer ZR. Again incorrect functional progression calculated Machine ZR will be notified. Frame synchronizer - synchronization signal generated in R5 is passed through connection unit D along with the bit-transparent data for this stage. It is transmitted to S. The transit connection route is updated by the program in the central calculation @ZR. Communication via the STB that can be fixedly, but arbitrarily predetermined during the initialization phase The access unit DS has individual 64kBit/s channels (D and B channel) data to the constituent units 1 to 6. Per B channel Simultaneously with each data flow, a byte synchronization signal is sent to the corresponding coupling unit from 1 to 6, thereby defining the start of each byte in the B channel data flow. being admired.

In the embodiment according to FIG. 3 there are basically two 64 per coupling unit Kl to 6. kBit/s channels, i.e. 12 64 kBit/s channels in total can be processed. This means that all 30 B channels and D Conditioning the possibility of additional connections to another coupling unit when processing a channel Ru. For this purpose, as mentioned above, a separate transit connection unit is connected to the internal interface IS. DEs are cascaded and additional coupling units are required for these64 They can be connected according to the number of kBit/s channels.

1 to 6 in the coupling unit are connected to the channel allocation unit KZE and the interface mode. Forms the original interface between Zier SB's parallel arithmetic operation unit PRW do. In the channel allocation unit KZE, as mentioned above, there are As the function progresses, individual channels occur within the parallel practical implementation device PRW. Data is processed. For this purpose one central calculation 11ZR and several calculation units are used. Knits REI to RE3 are provided. Each calculation unit REI or RE 3 is the decoding required for local memory and address decoding. 1, K2 or K2 in the two binding units. Connected to 3, K4 or 5, K6. Computation unit REI, RE2 or RE3 is the corresponding binding unit Kl, K2 or 3, K4 or 5, K 6 and together form a data processing block. Furthermore, calculation unit REI or R The E3s are connected to each other and to their respective computers ZR. Central calculator ZR exchanges information between the channel allocation unit KZE and the bus matching unit BAE. The bus TB is controlled so that it can be replaced. All calculation units REI By connecting the RE3s to each other and the central computer ZR through a special connection, and sufficient computing power to process at least 12 64kBit/s channels. is achieved. Each of these channels has one data processing processor. and in this case, in this example, the combination unit is processed every 1 to 6 times. Two chassles are processed. Provided for each calculation unit RE1 to RE3 The data of the four channels are finally transmitted to the central computer ZR. Terminal machine The devices ED and/or EA are V, 24/V, 28 termination devices and therefore the coupling Units 1 to 6 operate in focus-transparent mode and also calculate Unit REI or RE3 is preferably CCITT standard! , 460 and 1. 463 (V, +10), this is not shown in Figure 5. This is explained by the method illustrated in FIG. However, HDLC-LAP- B (H4gh Level Data Link Control-Lin k Access Procedure-Ba1anced) Plfl, S DLC (Synchronous Data Link Control) End equipment ED and/or EA operating according to standards may also be used. this child This means that interface mode SB must also operate according to this standard. means. A quick match to one of these standards is possible using computational units such as REI. Ishi RE3 and central total XI! New software version from TIIR via ZR This is possible by loading the page run. In this example, HDLC-LAP - It is possible to switch between B-key quasi and bit-transparent modes; The HDLC-LAP-B standard has a particularly good legacy. Because the coupling unit This is because ports 1 to 6 support these in terms of /X-ware.

In addition to these standards, in particular the following protocols may be used: X, 25. T.

90, T, 70. V, 120, etc.

For example, in the bus matching unit BAE of the interface module SB. 0 circuit equipment that matches to standardized bus B such as multipath ■. The modular configuration of the system makes it possible to use this concept for other bus systems as well. I forgive you. For this purpose, the bus matching unit of the interface module SB is used. It is sufficient to match the knitted BAE to a corresponding computer-hass system.

In particular, instead of the multipath mentioned above, non-standardized bus systems can also be used. Multipath■, VM E bus, F11tUR e bus, EISA bus Ill standardized Hass systems such as USB or PC/AT Babas may also be used. 0 interface module S for matching to the selected bus system B B on one side via the bus TB with the central computer ZR and on the other side with the bus A bidirectional memory unit SE is provided which is connected to system B. memo Reunit SE mainly handles arriving or departing data in addition to passing state information. It serves as a buffer for data. In addition, the interface module SB It is directly connected to the central calculation @ZR at the top, and also connected to the bus on the computer R side. There is a bus-based m unit BS accessing system B. bus control uni The set BS handles normal bus functions such as arbitration, succession and write control. Special initialization to initialize the interface module SB along with the functions The program portions are preferably loaded from the computer R during the initialization phase. As a result, a so-called ROM (readable memory) is installed in the interface module SB. Export-only memory) must exist for permanent storage of the initialization program. There isn't.

The universal layout of the circuit in Figure 3 not only allows arbitrary assignment of the B channel; , D channel processing is delegated to any computational unit REI, RE2 or RE3. It also makes it possible to One possible configuration is, for example, if the computing unit REI 1 in the coupling unit for processing the D channel, or The remaining shown computational units RE2 and RE3 process the eight B channels. It will be understood.

As already briefly shown, in order to handle more than 12 B channels, , another transit connection unit DE connects the internal interface to increase the channel capacity. Is. For example - all 30 B channels and and the corresponding D channels are to be processed simultaneously, as shown in FIG. Along with the circuit, the transmitting-receiving unit SE and the frame synchronizer R 3, two separate circuits have to be inserted. In this way, inside Mosier interface mode that is step-by-step configurable to up to 12 64kBit/s channels The use in which Zier SB should properly access a total of 11[11R] in this way and at the same time. can be matched to the number of people. However, all channels of −order rate connections are For example, more than three computational units y t with corresponding coupling units are equal It is realized in one module as if it is located in the mosier. It is also conceivable that other thysenel assignments to the various binding units may be chosen. 6 As mentioned above, the data flow in the interface module SB In order to control the progress of the calculation unit I-RE 1 to RE3 and the central computer A traveling progera L located within the ZR is provided. This progress program The system is also modularly constructed and can be accessed from the TIIR or from the communication network OF. or from the terminal device ED or EA via PF to the interface module SB It can be loaded into . Thus existing firmware can be maintained, updated and and matching as well as diagnosis of the interface module SB can be easily achieved. Ru.

Computation units REI to RE3 and a total of 1 central [transmission unit for jllZR] Because of their mutual coupling via the so-called "links 7" It remains in particularly good condition. No other digital signal processor is comparable in terms of computational power. An implementation with a processor or other processors is also possible.

For frame synchronizer R3 and pass-through unit DE, e.g. Moji5. -Advanced CMOS Frame Aligr+@r ( P EB 2035) or Siemens Memory Time Switch (MTSC) ) may be used.

Figure 4 shows Figure 1 and One possible embodiment of the device shown in FIG. 2 is shown, in which the entire system is Expanded in the sense of Xa connection. Although not shown in Figure 4, it has already been shown (LA N applications) The first variant is an extension based on the solution shown in Figs. 1 and 2. Regarding Zhang. :*Total of 1 [mR is connected to the communication network OF or PF, and In this case, the computers R can also directly communicate with each other via the network OF or PF, FIG. In a second variant, shown in , the various totals XIIR, R2 and R3 are connected to the bus system. through the system BS to the communication network OF or PF via the S/T reference point ST. The interface is connected to the earth module SB. Calculator R, R2 and Further connectivity possibilities for R3 and R3 are, for example, circuits realized as Ethernet. This occurs when connecting to the road network NW via the reference point RP. Expansion through this network connection Possibilities and abilities are expandable to nearly limitless potential. A large number of terminal devices are increasing at the same time. comviator system. You can also directly access data without storing it. For example, if computer R3, which transmits information to a main computer such as computer R, is in the circuit network NW. Tie it in and get 1 razu.

High performance requirements are not imposed on the second computer R3. In other words, economic solutions For example, this can be accomplished by using a personal computer.

Finally, in Fig. 4, a calculation IJiR4 connected to the network NW is provided. , whereby the interface module SB performs the VAN application and calculations described above. In addition to machine connection system, LAN/LAN coupling (local network) via 15DN It is shown that he is also leaving a legacy for the rear network). individual separated accessions 1110F Or it can connect to another l5DN subscriber via PF.

15DNil network OF and/or PF between two LANs connected to For transmission of large data blocks, transmission available via separate B channels Transmission bandwidth greater than bandwidth is desired. This is because the increase in transmission bandwidth and This is because the transmission time for data blocks of equal size is correspondingly reduced. Ru. Larger transmission bandwidth means more B channels can be combined into a wideband channel This is achieved by However, communication w4OF and/or PF 2 During this integration of an increasing number of B channels between two points, the various B channels are Do not follow equal connection paths in the network OF and/or PF; Because of this, the data in the data blocks distributed to various B channels are different. It is necessary to bear in mind that this may cause delays. Therefore, via the various B channels The delay time within one of the participating LANs for the data of a data block to be transmitted It is necessary to correct accordingly. *The method is based on the delay time that exists between B channels. Simplified so that it has to be determined only once, i.e. after the fulfillment of the connection. It will be done. This N-singleization means that once assigned B channels are The fact that the connection paths within the communication mOF and/or PF do not change over time This is the result.

The interface module SB now offers broadband such that the delay in L between the B thousand channels integrated for the channel can be determined. It is designed to. Broadband channels can then be used in any combination and any Tokumaru synthesized from several B channels The following examples in FIGS. 5 to 12 illustrate methods for bi-trait adaptation. It will be revealed. The challenge of bitrate adaptation is due to the insertion of additional and filling information. terminal #i equipment EA and ED (bit v- of communication network OF or PF) (see Figure 1 and and FIG. 2) are based on the original speed matching of the net bit rate. focus at the same time Rate adaptation should also occur in the opposite direction. This problem is solved in the current example. CCITT Recommendations 1.460 and 1. Predetermined by 463 (V, 110) This is solved by a bitrate adaptation algorithm based on the specified specifications. algorithm The software implementation of the system is unique in its ease of maintenance. It is advantageous for This is because new demands on algorithms can be made even faster. This is because it is realized in Furthermore, the method can be used, for example, in SB (Figs. 1 to 4) or calculation units REI to RE3 (Fig. 3) ) can be used for

Figure 5 shows the bit rate adaptation in the two bit rate adaptation stages RAI and RA2. 1 shows one possible realization of the method according to the invention for. 1st Pinot Tray) J Odan RAI is the end @ side of equipment EA and/or ED (Figures 1 and 2). The second bit rate adaptation stage RA2 transfers the resulting data rate DR to the communication network O. to the intermediate transmission rate ZUR which is assimilated to the network rate NR corresponding to F or PF. Adapt. At the same time bit rate adaptation in the opposite direction, i.e. from the network rate NR to 2 through the trade adaptation stage RA2 to the intermediate transmission rate ZUR and finally bit rate adaptation to the data rate DR via a first bit rate adaptation stage RAI; Responses will also be taken. In the present embodiment, the B channel based on the I5DN standard is V,24/ V.

Terminal equipment EA with the following parameters provided with 28 interfaces or Connected to ED (Figures 1 and 2): l stop bit, 7 data bit, 9 ゜6kBit/s (D transmission rate, asynchronous operation, XON/X0FF70-control 2' H,co's bit rate 11! If you follow the CCITT recommendations to realize the The speed adaptation in the tray linkage stages RAI and RA2 is preferably CCITT This is done in accordance with Recommendation I, 460'5 or 1.463 (V, 110). this child means that the data rate DR is 9. 6 kB i t/s + s ray) NR is 64k Bit/s, also means that the intermediate transmission rate ZUR is 16kBit/s. Taste.

Figures 6 to 12 show that the overall bit rate adaptation is performed in both stages and in the trade adaptation stage RA. from the sub-rate NR of the communication network OF or PF via 1 and RA2 to the terminal equipment E. This is indicated by the transition of A or ED to data rate DR.

FIG. 6 shows the connections 1 to 6 from the pass-through connection unit DS (FIG. 3) to the coupling unit. B-channel data whose length is theoretically unlimited, such that it can be allocated Flow DAS indicates 0 critical data is limited to 2 bits per byte BY Also, during the data flow DAS in Fig. 6, different hatchings and indicated by consecutive numbering of bytes. measurement) REL or R E3 (Figure 3) specifies data byte by byte from the corresponding data flow DAS. 1 to 6 (Fig. 3) to the coupling unit in the order shown, and then and the calculation unit in memory locations BYO to BY+5 or BY16 to BY31. in the local memory of bits REI to RE3 (Figure 3) in equal order; That is, byte BY (N) of data flow DAS is stored in memory location BYO. BY(N+1) is assigned to memory location BYI (and so on).

FIG. 7 shows local memory cells of calculation units REI to RE3 (FIG. 3). Two data centers DSO and DSL are shown located within the Each data center Dso and DSI in this example has four words WO through W3. or from W4 to W7, and each word WO to W7 consists of four bytes. ing. This results in a word length WL of 32 bits. The resulting data is The data is extracted from the data flow DAS (Figure 6) for each step, and the data is Stored in set DSO or DSI. Dataset DSO or DS If one of I is written with completely new data, the other data set DSI Or data storage during DSO continues. data safety) DSO or DSI In the unwritten stage, processing of data in this data set DSO or DSI is in progress. , then one data set DSO or DSI is being processed at any given time. while other datasets are written with new data. The premise is that the data set The first DSO or O51 continues before the second data set is filled again. This means that it can be treated as such. To achieve this, for example, according to Fig. A parallel computing device PRW with the corresponding capabilities described is used. data set The storage order of individual high 1-BYs (Figure 6) in a DSO or DSI is Lines corresponding to numbering BYO to BY15 or BY16 to BY31 be exposed.

In other words, the bite BY (Figure 6) is placed in the column from top to bottom, and in each column from the right. To the left are stored in the data set DSO or DSI. For clarification, Important bits particularly hatched in FIG. 6 are also carried over to FIG.

FIG. 8 shows completely new data as performed in the second bit rate adaptation stage RA2. The first stage shows the three separate processing steps of the DSO (data cell filled with The contents of words Wl to W3 are shifted to the left as follows: word W1 has only two bit positions, word W2 has only four bit positions, and word W3 is shifted to the left by six bit positions. Word WO remains unchanged . Figure 8b shows the data set DS resulting from the shift from the starting position in Figure 8a. Showing the stair-step arrangement of important data in O.6 important data overlap vertically. This is a prerequisite for the second step.

In this case, all important data in four words WO to W3 are in word WO. (Fig. 8c), the drawing of word WQ into data word TmpA. In the second bit rate adaptation stage RA2, the actual third step The adaptation is finished and new data can be stored in the DSO. .

Subsequent processing of the dataset DSL is performed in an equal manner, while the dataset New data is placed in the DSO again. After this processing step, the transmission has been reduced by a factor of 4. 64kBit/s cable-1-NR is 1 It has been reduced to an intermediate transmission rate ZUR of 6 kBit/s.

In this example we started from a word length WL of 32 Bits. as in the present case four words WQ to W3 are selected for data set DSO or DSI. The very word W0 that grows important related data by the explained method is obtained. However, if other word lengths W such as 1G or 6dBit L is also possible. As in the current example, important data is related to one word. If you want to store the number of words per data set DSO or DSI General rule that it must be equal to the number of hides in a word occurs.

Data flow 1) As (Figure 6) is transferred to the processing step of the first focus rate adaptive RAI. A specific synchronization bit pattern is used in the data flow AS to synchronize with the It is necessary to search for the corner Nb. In the current V, 24 implementation system, this This is a zero byte sent at the beginning and at regular intervals during the data transfer.

This zero byte occupies a specific position in the data word TmpA for synchronization purposes. There must be. In the present embodiment, the least significant bit of the synchronization bit pattern Nb When the bit matches the least significant bit of data word TmpA, that is, synchronization occurs. The bit pattern Nb is on the right in the data word TmpA! When the synchronization has been achieved. FIG. 9 shows the steps required for synchronization. No. Data flow DAS reduced in bit rate adaptation RA2 of 2 (6th The part located in the data word TmpA in the figure) has a word length WL of 32 bits. and a synchronization bit pattern length of 9 Bits, respectively. Compared with two stationary search windows SFO and SFI with bit patterns It will be done.

If the comparison with both search windows SFO and SFI yields a negative result, the data word T mpA is shifted one position to the right. Then again, the data word TmpA data that exists in both search windows SFO and SFI A comparison is made with The content of search window SFO is the current position of data word TmpA. If it matches the contents of data word TmpA, the start of an important data flow is recognized. and the synchronization bit pattern Nb is located to the right in the data word TmpA. It is location. The contents of search window SFI match the contents of data word TmpA at this position. If so, the data word TmpA is in the present embodiment the synchronization bit pattern. Another eight bit positions, such that the right position is satisfied in the data word TmpA. The method steps required for this synchronization must be shifted to the right. Along with this, unimportant signals such as pause signals, break signals, etc. are automatically deactivated. data flow. The data that remains after synchronization is not the same as the usage data. , various control data and additional Contains transmission data.

Only one search window SFO can also be used instead of two search windows SFO and SFI. obtain. However, in that case, a longer search time must be allowed. Why On average, the search window SFO and 5FIO were more slender in many locations. This is because it is necessary to make many comparisons. However, on the other hand, there are too many locations search windows may also be used for synchronization. If too many search windows are chosen, the search cable efficiency decreases. Because, on the one hand, the number of comparisons increases again, and on the other hand, This is because larger memory demands are required for the search window.

Figure 10 shows the first bit rate sequence synchronized and placed in the data unit DE. In the data flow DA3 before stage RAI and in the first bit rate adaptation stage RAI Processing clocks TktO to Tkt4 used in the processing are shown. data Unit DE consists, for example, of two data words TmpA and TmpB. and is completely processed within the processing clock TktO. Data unit D After processing E, data words TmpC and TmpD become new data words Tm pA and TmpB. Similarly, the names of the remaining data words are also shifted.

This name change and shift is based on the process listed in Figure 10. to Tkt4. In the table of Figure 10, the second bit rate The data starting from the adaptation stage RA2 are transferred from right to left to the calculation units REI to RE. 3, the individual Pintos are named according to their functions. Inside the clock TktO The following information is present in the data word TmpA. synchronization bit pattern Nb is a zero byte with all bits zero-centred. Then the same One 1 that can be incorporated into the search window SFO or SFI (Figure 9) is Subsequently, the start bit sta causes 3 to correspond to the protocol V, 24/V, 28. Usage data interrupted by another control data such as A, SB, X or “1” The original start of bO to b70 is indicated. The last pi of usage data bO to b7 Finally, a stop bit sto is sent after each event. vF specific information unit is formed by the empty byte Lb, in which another Mill 1110 data is encoded. can be done. For example, the encoding of the transmission message or in the V, 24/V, 28 standard. Other instructions are scheduled for. The sequence to be explained is now the entire back of Figure 10. five data words TmpA to Tm. It repeats regularly after pE and is used simply to monitor the synchronization status of the transmission. This shows the structure of a possible data flow. When checking the synchronization state results in a negative result For the first time, the data flow must be newly synchronized by the method described in Figure 9. Must be.

FIG. 11 shows a data unit DE with both data words TmpA and TmpB. shows. For three processing steps that proceed one after another and with equal clocks The starting position is shown in FIG. 11a. Then add the data entry as shown in the table in Figure 1o. -1' Equal data units for TmpA and TmpB clock Tkt It has been revealed for O. The length of both data words TmpA and TmpB Now all wIm data except the start and stop bits sta or sto are removed. The remaining data remaining in the data word TmpA is data to the left. shifted in the direction indicated by the arrow above word TmpA (Fig. 11b). , during which the remaining data remaining in the data word TmpA is transferred to the right. shifted in the direction indicated by the arrow below word TmpA (Fig. 11b). Ru.

The results of this described embodiment are evident from FIG. 11b. This is currently planned Microprocessor and associated accessories used for the second REI or RE3 outputs for those special functions for left or right shifting of double words left or right. It is also the starting point. The contents of data unit DE in FIG. 11b are thereby relevant. Therefore, the data in their new form can be used as a data word among the data words TmpA. It is shifted to the right until it is again located on the right within TmpB. The shift direction is This is indicated by the arrow at the top of Figure 11c.

Before using modern microprocessors, which are used with special features Instead of the method steps described above, the shift of the data word TmpA or TmpB is It can also be done individually. In that case, the disadvantages are above all that it is longer and more expensive. The law is in progress.

FIG. 12 further proceeds with an equal clock TktO, which can be called the actual extraction stage. The method steps are shown below. Is the usage data bo or b7 the data flow that has just been selected? ZRC is also used for post-processing or interpolation (see Figure 3). or transmitted to the total IEliR (see FIGS. 1, 2, and 4). This passing An additional extraction word BXW is introduced above the data unit DE to explain and clarify the process. entered. The extraction word BXW is extracted at the beginning of the process as shown in Figure 12a. It's completely filled with j's. By the above right shift operation, the data word Tm The contents of pA and TmpB are shifted to the right into the extracted word BXW (12th b).

Usage data bO to b7 (black box in Figure 12b) are read from the extracted word BXW. and is also transmitted via register BA. Extracted word read in BXW The focus position is superimposed in 1 with the corresponding start and stop focus sta and stp. (see Figure 12c). Another important data is data word TmpA. data word TmpA is no longer important data. Data occurs to the left (the 1st 12d) into the extracted word BXW. This clock Tkt now Finally, byte usage data bO to b7 are read in O (Figure 12e), and By 1 again in the extracted word BXW! (Figure 12f), the current data The processing of the data unit DE is thus completed, and the next clock A new assignment of data word symbols in can be made according to the instructions in FIG.

As mentioned above, bitrate adaptation occurs in both directions simultaneously. Figures 6 to 1 The method explained by Figure 2 can of course be applied in other directions, i.e. the data rate I)R? It can also be applied to the network rate NR. Corresponding method steps are then A simplification that does not require the synchronization step described by Figure 9, simply reversing the order. Applied in the introduction.

Data set in local memory of calculation units REi to RE3 (Figure 3) Data flow DAS (Fig. 6) to be processed in DSO and DSL (Fig. 7) The data in Fig. is stored in the intermediate memory of The data may be transferred into the local memory of EI or RE3 (Figure 3). The above-mentioned alternation of data Seno (N) So and DSI (Fig. 7) is performed by intermediate storage of data. (especially if both data centers) DSO and DSI are processed by each other. obtain.

For the implementation of it from 1 to 6 (Fig. 3) in the coupling unit, it is called HS CX. Siemens Mozier or other suitable Mojire may be used. , at that time, the H3CX had already integrated intermediate memory configured as FIFO memory. has been done. Finally, the intermediate memory stores the number of data sets DSO and DSL in the chicks. It also makes it possible to reduce to a data set DSO or DSI.

The total word length WL is 32 bits in the present example, including all variables and memory. Shown against Nint. The method steps presented can be easily adapted to any arbitrarily chosen word. It can also be applied to the code length WL.

Of course, the invention is not limited to the original application of the current l5DN standard; It is also used in modified ability features and in other classes when setting equal intelligence R. obtain.

Fig, 1 ~． 2 Sunset 3 ~・4 NRZURDR ~, 5 F’IQ, 8 ~． 7a Fig, 7b ~,plow At dusk mouth sit 6ii 5i examination Noto ← Lotto I+co-1 Continuation of front page (31) Priority claim number 02453/9l-6 (32) Priority mill 1991 8 April 21st (33) Priority claim country: Switzerland (CH) (81) Designated country: EP (AT, BE, CH, DE.

DK, ES, FR, GB, GR, IT, LU, MC, NL, SE), JP, US (72) Inventor: Skalski, Beta Switzerland Zeher-8048 Chu -rich Schneebelistrasse 7

Claims (22)

[Claims] 1. Communication between a computer and another data transmission and data reception device connected to a communication network A device for connecting computers to a digital communication network for the purpose of exchanging data between and at least one each at the calculator (R) on the one hand and at the reference point (ST) on the other hand. Through at least one connection having one base channel shape and an auxiliary channel An interface connected to switching equipment installed in a communications network (OF; PF). An interface module (SB) is provided, and an interface module (S B) the channel allocation unit (KZE), the parallel computing mechanism (PRW) and the bus It consists of an adaptive unit (BAE) and is embedded in a parallel computing mechanism (PRW). A central computer (ZR) and at least one calculation unit (RE1) are provided. A parallel computing mechanism (PRW) processes all channels of a connection simultaneously. A device for connecting a computer to a digital communication network. 2. The communication network (OF; PFL) is standardized according to the ISDN standard, and The connection at the point of sight (ST) is a first rate connection with a B channel structure. The device according to claim 1, characterized in that: 3. The channel allocation unit (KZE) sends/receives the unit (SE), frames Contains a synchronizer (RS) and a transit connection unit (DS), A signal-receiving unit (SE) connects to a connection or primary rate connection on one side and to the transit connection unit (DS) via the frame synchronizer (RS) on the the pass-through unit (DS) is connected to at least the coupling unit (K1, ..., K6), and is also connected to the transmitter-receiver unit (SE) and frame synchronizer. Chronizer (RS) and transit connection unit (DS) via bus (TB) Claim 1 or 2 characterized in that it is connected to a central computer (ZR) The device described. 4. The transit connection route of the transit connection unit (DS) is determined in advance by the program. 4. The device according to claim 3, characterized in that: 5. The central computer (ZR) is also a calculation unit with a parallel calculation mechanism (PRW) (RE1, RE2, RE3) also consist of each transputer or signal processor. 3. The device according to claim 1 or 2, characterized in that: 6. The bus adaptive unit (BAE) is connected to the memory unit (SE) and the bus control unit. 3. The device according to claim 1 or 2, characterized in that it consists of a BS (BS). . 7. from the terminal equipment (EA, ED) via the digital communication network (OF, PF). Alternatively, the progress program can be transferred to the interface module (SB) via the computer (R). ) The device according to claim 1 or 2, characterized in that it can be loaded into a . 8. The interface module (SB) is configured as a modular and Appropriate for the number of terminal devices (EA, ED) that access the computer (R) at the same time. 3. A device according to claim 1 or 2, characterized in that it can be adapted to 9. Through the computer (R) connected to the interface module (SB) Another circuit network (NW) is connected to another computer (R2, R3) via a reference point (RP) 3. The device according to claim 1 or 2, characterized in that: 10. At least one other calculator (R4) connects the network via a reference point, (RP) 10. The device according to claim 9, wherein the device is connected to (NW). 11. Different transmissions of control and/or usage data in the data flow between at least two units or data lines operating at and a method for bit rate adaptation of a data channel exchanged between , the data flow (DAS) of the calculation units (RE1, RE2, RE3) At least one data set (DS) predefined by word length (WL) 0, DS1) or data units (DE), and usage information is divided into data units (DE). extracted from the set (DS0, DS1) or data unit (DE) and also calculated. A device characterized in that it is transmitted to a computer (R, R2, R3, R4) or data line. A method for bit rate adaptation of data channels. 12. Bit rate adaptation is based on CCITT Recommendation V. 110. 12. The method according to claim 11, wherein the method comprises: 13. Data is transmitted in both the transmit and receive direction, and there is little bit rate adaptation. Claim 1 characterized in that it is carried out in at least one stage (RA2, RA1) 1 or 12. 14. A synchronization bit pattern that is provided in the control data and is periodically manipulated. (Nb) for synchronization and important data in the data flow (DAS). used for the recognition of the start of the data flow (DAS) and the calculation unit For this synchronization of (RE1, RE2, RE3) at least one search window (S Claim 11 or 12, characterized in that F0, SF1) is provided. How to put it on. 15. Occasionally generated during data flow (DAS), e.g. pause signals. Claim 11 or 12 characterized in that unimportant data is erased. Method described. 16. When performing two-stage or multi-stage bit rate adaptation (RA1, RA2), the last stage ( RA2) contains at least one data set (DS0, DS1) and data flow (DAS) is stored continuously in data sets (DS0, DS1) and these are successively in at least two datasets (DS0, DS1). It is used to store data and the words in the dataset (DS0, DS1). The number of nodes (W0, ..., W3; W4, ..., W7) is the calculation unit (RE1, RE2). , RE3) and the number of bytes in the word of these datasets (D The individual words (W0, ..., W3; W4, ..., W7) of S0, DS1) are offset from each other. and in word (W0;W1) or another register of equal size. 13. The method according to claim 11 or 12, characterized in that the method is combined. 17. All functions, especially data flow (DAS) and compute units (RE1, R E2, RE3) is tested during the progress of bit rate adaptation. 13. The method according to claim 11 or 12, characterized in that: 18. Data flow (DAS) control data is partially or completely erased 13. The method according to claim 11 or 12, characterized in that: 19. A data unit (DE) consists of at least one data word (TmpA,... , TmpF), and the contents of the data unit (DE) are extracted words (B XW), and then the computer (R; R2, R3, R 13. The method according to claim 11 or 12, characterized in that the method is transmitted to 4). 20. The progression is done by clocks (Tkt0, Tkt1,...) and Claim characterized in that at least one data unit (DE) is processed The method according to range 11 or 12. 21. Multiple data channels with corresponding data flows (DAS) are A request characterized in that it is processed in the processing unit (RE1, RE2, RE3). The method according to claim 11 or 12. 22. Another computer (R; R2, R3) connected to the communication network (OF, PF) Data transmission and data exchange with data receiving equipment (EA, ED) To connect the computers (R; R2, R3, R4) to the digital communication network (OF, PF). Application of the method according to claim 11 in a device for.