JPH0648597B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a reference potential generation circuit for determining data read from a memory cell. Is.

(Prior Art) Conventionally, a semiconductor memory device, for example, a floating gate type MOSFE
An EPROM using T as a memory cell is constructed as shown in FIG. In FIG. 3, MC11, M
.., MCmn are memory cells composed of floating gate type MOSFETs, DC1, DC2, ..., DCm are dummy cells composed of floating gate type MOSFETs, WL1, WL2.
, WLm are row lines, BL1, BL2, ..., BLn are column lines, DBL is a dummy column line, 11 is a row decoder, 12 is a column decoder, BT1, BT2, ..., BTn are column gates MO.
SFET and DBT are MOSFETs equivalent to this column gate MOSFET and set to be conductive by the power supply voltage, and 13 is MO.
A first load circuit composed of SFETs QM1 to QM12, 14 a second load circuit composed of MOSFETs QD1 to QD12,
Reference numeral 15 is a data detection circuit for sense up or the like.

In the EPROM having such a configuration, the dummy cells DC1,
Second load circuit based on data of DC2, ..., DCm
The reference potential V _REF generated in 14 and the potential V _IN generated in the first load circuit 13 based on the data read from the selected memory cell MCiji = 1 to m, j = 1 to n) The detection circuit 15 detects the data stored in the memory cell MCij by comparison, and outputs the read data from the data detection circuit 15 to an output buffer or the like (not shown). The dummy cells DC1, DC2, ...
The memory cells MC11, MC12, ...
A transistor equivalent to MCmn is used, and dummy column lines DBL are also equivalent to column lines BL1, BL2, ..., BLn. These are, for example, memory cell arrays.
It is provided in 16. The current supply capacity of the load transistor QD5 in the second load circuit 14 on the dummy cell side is set to be larger than the current supply capacity of the load transistor QM5 in the first load circuit 13 on the memory cell side. Data detection circuit 15
The data is detected by making a difference between the potentials V _IN and V _REF supplied to both ends of. In order to make a difference in the current supply capacity in this way, for example, when the size of the transistor QM5 is W5 / L, the size of the transistor QD5 is W.
6 / L, and the channel width of the transistor QD5 is set large so that “W6> W5”. This produces a difference between the two potentials V _IN and V _REF as described above. The sizes of the transistors QM1 to QM4 forming the load circuit 13 are W1 / L and W2 / L, respectively.
If L, W3 / L, and W4 / L, the sizes of the transistors QD1 to QD4 of the load circuit 14 are W1 / L and W, respectively.
2 / L, W3 / L, W4 / L are set, and "W1>
The relations "W2" and "W3>W4" are set.

In the memory cell of the EPROM described above, data is stored depending on whether or not electrons are injected into the floating gate. That is, the electron injected into the floating gate maintains the off state even when the control gate is supplied with the signal of "1" level, and the electron not injected into the floating gate is turned on.
On the other hand, since electrons are not injected into the dummy cell, it is equivalent to that of the main body side memory cell in which electrons are not injected, and there is no potential difference between V _IN and V _{REF as} it is. The current supply capacity is set to be larger than QM5. By doing so, a potential difference can be generated between V _IN and V _REF even when a memory cell into which electrons have not been injected is selected.

By the way, in a general semiconductor memory device, its operation is controlled by a chip enable signal or a chip select signal in order to reduce current consumption when the chip is in a non-selected state. When the chip is activated by the chip enable signal ▲ ▼ and data is read out, the signal ▲
▼ is amplified by the buffer circuit inside the chip and transmitted to each internal circuit. The signal ▲ ▼ sets the address buffer, the decoder, the sense amplifier, etc. to the operating state. Therefore, from the time when the address changes and the data is read when the chip is in the operating state, the time until the signal ▲ ▼ is transmitted to the address buffer etc. via the buffer circuit and the address buffer circuit becomes the operating state is calculated. It will take extra access time. In addition to the difference in the internal transmission time, the load transistor Q
The operation speed further decreases due to the difference in current supply capability between M5 and QD5.

Hereinafter, this will be described in detail with reference to FIGS. 4 (a) to 4 (d). (A) The figure shows the chip enable signal C
E, (b) is the potential of the selected row line, (c) is the reference potential V _REF , and potential V _IN0 corresponding to the read data from the memory cell (the memory cell in which electrons have not been injected into the floating gate). , V _IN1 (in the case of a memory cell in which electrons are injected into the floating gate), and (d) shows the output of the data detection circuit 15, respectively. When the chip is in a non-operating state, that is, when the chip enable signal CE is "0", all the row lines WL1, WL2, ..., WLm are set to "0" level. Then, when the signal CE goes to "1" level and the address input is transmitted, the selected one row line goes to "1" level. At the same time when the signal CE becomes "1" level, the load circuits 13 and 14 start operating. A memory cell in which electrons are injected into the floating gate maintains an off state even when the row line becomes "1" level, so the column line corresponding to this memory cell is charged, and the memory cell of the data detection circuit 15 is charged. The side potential V _IN1 begins to be charged as shown in FIG. Meanwhile, the potential V _{REF is} also charged. Then, the respective potentials V _REF , V _IN1 , V _INO
The output of the data detection circuit 15 becomes the "1" level or the "0" level at the time point when the temperature is stabilized.

However, in such a configuration, the load transistor QD5
Since the current supply capacity is higher than that of the load transistor QM5, V _REF is charged faster than V _{IN1 in the} region where the row line is not at the sufficient "1" level. Therefore, although a higher potential than the _{V REF} towards _{V IN1} is stable point, V from _{V IN1} is at one time in the middle of charging
_REF has a higher potential. During this period, the data detection circuit 15 cannot detect the data to be detected, and the read speed becomes slow. In order to avoid this, it is sufficient to wait for the time when the load circuit 14 is operated until the row line becomes sufficiently "1" level, but in order to do so, the time when the row line becomes sufficiently "1" level It is necessary to take into account that the margin is lost due to the variation of the setting of the time, and the operation speed becomes rather slow when the charging timing is delayed due to the variation of the process.

(Problems to be Solved by the Invention) As described above, the conventional semiconductor memory device has a drawback that the data reading speed is reduced when the chip is in the operating state.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device capable of improving the data reading speed when the chip is in the operating state.

[Structure of Invention]

(Means and Actions for Solving Problems) That is, in the present invention, in order to reduce the charging speed of the load circuit on the dummy cell side, the load capacitance of the dummy column line is set to be larger than the load capacitance of the column line. Means are provided.

According to such a configuration, even if the current supply capacity of the load circuit on the dummy cell side is larger than the current supply capacity of the load circuit on the memory cell side, the load capacity of the dummy column line is set to be larger than the load capacity of the column line. Therefore, the charging speed of the load circuit on the dummy cell side can be reduced. As a result, the potential generated by the load circuit on the memory cell side can be set so as not to become lower than the reference potential generated by the load circuit on the dummy cell side, so that the data read speed at the start of the chip operation can be increased.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same components as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In the circuit shown in FIG. 1, in order to set the load capacitance of the dummy column line larger than the load capacitance of the column line, in addition to the dummy column line shown in FIG. 3, a second control gate is connected to the ground point. A second dummy column line connecting the dummy cell group is provided. At this time, for example, the channel width W5 of the load transistor QM5
Is 1/2 the channel width W6 of the load transistor QD5, it is preferable to provide two dummy column lines equivalent to the column lines BL1, BL2, ..., BLn. That is, as shown in FIG. 1, one dummy cell group DC11, DC21,
The gates of DCm1 are row lines WL1, WL2, respectively.
..., WLm connected to the other dummy cell group DC12, DC
22 ..., DCm2 are connected to their respective ground points so that they do not turn on. Further, between the two dummy column lines DBL1 and DBL2 and the load circuit 14, a MOSFET DB equivalent to the column gate MOSFETs BT1, BT2, ...
T1 and DBT2 are provided. The load transistor QM
When the channel width W5 of 5 is 1/3 of the channel width W6 of the load transistor QD5, the number of dummy column lines is three,
The control gate of each dummy cell connected to the two dummy column lines is connected to the ground point.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIGS. First, the chip enable signal CE
Becomes "1" level, the chip enters the operating state and the load circuits 13 and 14 start operating. Here, since there are two dummy column lines DBL1 and DBL2 and the channel width W6 of the load transistor QD5 is 1/2 of the channel width W5 of the load transistor QM5, the row lines WL1 and WL
2, ..., WLm are all at "0" level, all memory cells MC11, MC12, ..., MCmn and dummy cells DC11,
When DC12, ..., DCm2 are off, potential V
_REF and V _IN1 are similarly charged and go up. This is the load transistor QD5 as described above.
This is because the channel width W6 is twice W5 and the two column lines are also connected to the dummy side. When the selected row line goes to "1" level and the dummy cell connected to this row line starts to turn on, the rise of the reference potential V _REF slows down. On the other hand, since the memory cell on the main body side remains off, the potential V _IN1 continues to rise, but the reference potential V _REF is increased.
Stops rising at a predetermined value when the dummy cell turns on. In the data detection circuit 15, the potentials V _IN1 and V
_The "1" level or "0" level is determined at the initial stage of potential change that determines the magnitude relationship of _REF , and this is output as read data to an output buffer (not shown) or the like.

According to such a configuration, the potential V _IN1 is the reference potential V
_{Since the} level does not become lower than _REF, the output of the data detection circuit 15 at the initial stage of potential change can be determined, the comparison operation can be sped up, and the data read speed at the start of the chip operation can be sped up.

Although the EPROM is used as an example in the above embodiment, the present invention is not limited to this. For example, a mask ROM is used.
It is applicable to all semiconductor memory devices using the reference potential V _REF . Further, in the above embodiment, the number of dummy column lines is increased in order to set the load capacitance of the dummy column lines larger than the load capacitance of the column lines. However, the number of dummy column lines is set to 1 and the load is applied to this dummy column line. You may connect a capacity. Further, it is not always necessary to determine the capacitance of the dummy column line according to the ratio of the channel widths W5 and W6 of the load transistors QM5 and QD5. That is, as shown in FIG. 2C, the load capacitance may be provided so that the reference voltage V _REF does not exceed V _IN1 . Further, instead of the transistors DBT1, DBT2 equivalent to the column gate transistors BT1, BT2, ..., BTn, transistors whose conduction is controlled by the same gate signal as those of the column gate transistors BT1, BT2 ,. good. Further, a load capacitance may be provided in the load circuit 14 in accordance with the ratio of W5 and W6. By doing so, the dummy cell side and the body side memory cell side can be made completely the same in circuit, and the potentials V _REF and V The rise in _IN1 and V _INO can be matched exactly.

[Effects of the Invention] As described above, according to the invention, it is possible to obtain the semiconductor memory device capable of improving the data reading speed when the chip is in the operating state.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a conventional semiconductor memory device. The circuit diagram shown in FIG. 4 is a timing chart for explaining the operation of the circuit shown in FIG. WL1, WL2, ..., WLm ... Row line, MC11, MC1
2, ..., MCmm ... Memory cells, BL1, BL2, ...,
BLn ... Column line, 13 ... First load circuit, 15 ... Data detection circuit, DC11, DC12, ..., DCm2 ... Dummy cell, DBL1, DBL2 ... Dummy column line, 14 ... Second load circuit .

Claims (2)

[Claims] 1. A row line, a memory cell selectively driven by the row line, a column line for receiving data from the memory cell, a first load circuit connected to the column line, A data detection circuit that compares the potential of a column line with a reference potential to detect stored data in the memory cell, a dummy cell for generating the reference potential, a dummy column line that receives data from the dummy cell, A second load circuit connected to the dummy column line and having a larger current supply capacity than the first load circuit;
And a means for setting the load capacitance of the dummy column line to be larger than the load capacitance of the column line. 2. A row line, a memory cell selectively driven by the row line, a column line for receiving data from the memory cell, a first load circuit connected to the column line, A data detection circuit that compares the potential of a column line with a reference potential to detect stored data in the memory cell, a plurality of dummy cells for generating the reference potential, and a dummy column line that receives data from the dummy cell. A second load circuit connected to the dummy column line and having a larger current supply capacity than the first load circuit, the dummy column line being larger than the number of the memory cells connected to the column line. A semiconductor memory device characterized in that the load capacitance of the dummy column line is made larger than the load capacitance of the column line by increasing the number of the dummy cells connected to.