JPH0645421A - Integrated circuit - Google Patents

Abstract

PURPOSE:To ensure a test without causing an erroneous operation of an internal logic circuit even when there is prepared a test pattern where a plurality of output buffers are simultaneously operated. CONSTITUTION:There are provided an input buffer 3 for driving an internal logic circuit 2 at the center of a semiconductor chip 1 and an output buffet 4 for transmitting a signal from the internal logic circuit to the outside of the chip around a chip peripheral part, and further there are divided the output buffer 4 into two groups Oa and Ob. Further, there is provided around the chip control terminals 7a and 7b for applying an output buffer control signal which disables each group in a lump. Accordingly, even though a test pattern is applied which pattern simultaneously actuates all output buffers, output buffers of one group are disabled by applying the output buffer control signal to one of the control terminals to prevent a greater current from flowing at a time, whereby the internal logic circuit is prevented from erroneously operated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an internal logic circuit, an input buffer for driving the internal logic circuit, and an output buffer for outputting a signal of the internal logic circuit to the outside of a chip, which are formed on one semiconductor chip. Related to integrated circuits.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional integrated circuit chip of this type. In the figure, an internal logic circuit 2 is formed in the center of a chip 1, and a large number of input buffers 3 (I
Mark) and an output buffer 4 (marked O) are provided with the respective bonding pads 3a, 4a. A power supply bonding pad 5 and a ground bonding pad 6 are further provided in the peripheral portion.

The input signal is applied to the internal logic circuit 2 via the input buffer 3, and the signal output processed by the internal logic circuit 2 is sent out of the chip through the output buffer.

[0004]

In such an integrated circuit, when all the output buffers around the chip are driven at the same time, a large current flows, which causes a large voltage drop and malfunction of the internal logic circuit. There was a problem of doing. Therefore, when creating a test pattern, it was necessary to be careful not to operate all output buffers at the same time.

[0005]

In order to solve the above-mentioned problems, the present invention divides a plurality of output buffers into a plurality of groups, and a signal controlled to be inactive for each group independently of an internal logic circuit connected thereto. A control terminal (bonding pad) to be applied is provided.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a semiconductor chip according to an embodiment of the present invention. In the figure, a plurality of input buffers 3 (marked with I) are provided around the semiconductor chip 1 as in the conventional example of FIG.
And the output buffer 4 are the respective bonding pads 3
a, 4a, and a power supply bonding pad 5 and a ground bonding pad 6 are formed at the corners of the peripheral portion. In addition to this, in the present invention, the output buffer 4 is divided into two groups, Oa and Ob. Bonding pads (control terminals) 7a and 7b for controlling the output buffer are provided adjacent to the peripheral power supply pad 5 and the ground pad 6, respectively.

Output buffer control terminal 7a
When an output buffer control signal is applied to the output buffer, for example, a gate circuit attached to the output buffer operates, and the output buffer of the Oa group of the output buffers is made inactive independently of the internal logic circuit connected thereto. . Similarly, when an output buffer control signal is input to the control terminal 7b, the output buffers of the Ob group are made inoperative. Therefore, when a control signal is applied to one of the control terminals 7a or 7b, only about half of the output buffers operate even if there is a drive input from the internal logic circuit to all the output buffers.
As for the output buffer current, only half the current of the entire operation flows, so no abnormal voltage drop occurs and no malfunction of the internal logic circuit occurs.

In the above example, the output buffers are divided into two groups, but it is also possible to divide these into three groups. Naturally, three output buffer control terminals are provided for each group, and one third of the buffers work. It is also possible to reduce the output buffer current and further suppress the power supply voltage fluctuation.

[0009]

As described above, according to the present invention, since a plurality of output buffers can be divided into a plurality of groups in advance and each divided group can be controlled to be in the inoperative state independently of the internal logic circuit, It is possible to prevent a large current from flowing even if a test pattern in which the output buffers operate simultaneously is created, and it is possible to prevent malfunction of the internal logic circuit due to a voltage drop due to a large current.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor chip according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor chip of a conventional integrated circuit.

[Explanation of symbols]

 1 semiconductor chip 2 internal logic circuit 3 input buffer 4 output buffer 4a output buffer bonding pad Oa a group output buffer Ob b group output buffer 5 power supply bonding pad 6 ground bonding pad 7a, 7b control terminal

Claims (1)

[Claims] 1. In an integrated circuit in which an internal logic circuit and a plurality of input buffers and output buffers corresponding to the internal logic circuit are formed on a semiconductor chip, the plurality of output buffers are divided into a plurality of groups. An integrated circuit, wherein each output buffer of each group is provided with a control terminal to the periphery of the chip to which a control signal for controlling an inoperative state is provided independently of an internal logic circuit connected to the output buffer. .