JPH0645401A - Package for semiconductor device - Google Patents

Abstract

PURPOSE:To reduce any noise to be produced in a semiconductor device in the vicinity of a source which produces the poise, establish impedance matching, and ensure reduced thermal resistance and stress modification. CONSTITUTION:A solder bump 4 for connection of a flip chip is provided on a connection surface of a semiconductor chip 2 of a flip chip carrier 6. Further, a low melting point brazing material 5 is provided such that it is not electrically connected with the solder bump 4 and it provides power supply potential or ground potential with respect to the semiconductor chip 2. A chip sealing part 8 is provided around a metal pedestal formed with the low melting point material 5 kept at the ground potential so as to seal the metal pedestal with the chip. An external bump 7 is provided on a surface opposite to a surface on which the semiconductor chip 2 is mounted for electrically connect a circuit board 1 and the semiconductor chip 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package, and more particularly to a semiconductor device package featuring flip chip connection.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to the drawings.

FIG. 7 is a partially enlarged sectional view of an example of a conventional semiconductor device package, and FIG. 8 is a partially cutaway perspective view of the semiconductor device package of FIG.

As shown in FIGS. 7 and 8, the ceramic substrate 24 has a four-layer structure. That is, the external lead 2
9 is a layer for forming a metallized pattern for brazing, a layer for forming a ground terminal and a signal wiring with the semiconductor chip 2, a power source metallized layer 28 and a grounded metallized layer 27. The ceramic substrate 24 is formed by laminating these ceramic layers, providing desired grounding through the through holes, and firing. After this,
The metallized pattern exposed on the surface of the ceramic substrate 24 is plated with Ni, the external leads 29 are brazed with an Ag-Cu brazing material, and further plated with Ni and Au. The solder bump 4 has a columnar Cu core bump having a height of 50 μm and Ni and Au of 2 to 3 and 1.5 to 2 respectively.
.mu.m, and a solder plating of 30 .mu.m is deposited thereon. The semiconductor chip 2 is connected to the ceramic substrate 24 by the flip chip connection method. Next, a cap 3 is used for heat dissipation and protection of the semiconductor chip 2. As a material of the cap 3, a ceramic such as Cu, Al, AlN, or SiC which is a highly heat-conductive metal corresponding to high heat generation density and high power consumption is used. The semiconductor chip 2 has a C on the inner surface of the cap 3.
A u or Al thin film is contacted through a pure metal thin film 32 having a thickness of about 50 μm and pressure is applied to the cap 3, and the ceramic substrate 24 is bonded with a resin 31 so as to cover the semiconductor chip 2. As described above, the semiconductor device package is completed.

At this time, the electrostatic capacitance between the ground potential and the power supply potential becomes a simple parallel plate capacitance. By such a method, generally, a semiconductor device package can be manufactured with a stable yield. Since the minimum ceramic layer thickness is about 0.2 mm, the material of the ceramic substrate 24 is alumina (Al ₂
In the case of O ₃ ), the capacitance per pair is 55 pF / cm
It will be about ² .

[0006]

In this conventional package for a semiconductor device, a ground layer and a power layer are provided inside for the purpose of reducing the DC resistance and inductance inside the package of the ground and the power source. The power supply terminal and ground terminal of the mounted semiconductor chip, the power supply lead for external connection, and the ground lead are connected. By adopting this structure, it is possible to control the noise generation due to the inductance inside the semiconductor device package. However, the power supply and ground noise generated inside the semiconductor chip must be smoothed by a capacitor or the like. In order to obtain this effect better, a capacitance is applied between the ground layer and the power supply layer inside the semiconductor device package. It is desirable to do.

In this conventional semiconductor device package, when the thickness of ceramics between layers is 0.2 mm, the electrostatic capacitance between the ground layer and the power source layer is simply the capacitance between parallel plates, so that the ground layer and the power source layer The capacity per pair is 55 pF / cm
There was a problem that the limit was about ² .

Further, in the conventional semiconductor device package, there is also a problem that the crosstalk generated between the solder bumps cannot be reduced.

Further, from the viewpoint of heat dissipation, the heat generated on the front surface of the semiconductor chip is dissipated only from the cap on the back surface of the semiconductor chip and the solder bumps on the front surface, so that the semiconductor chip and the ceramic substrate have different thermal expansion coefficients. There is a problem that stress is generated in the solder bump connection portion due to heat generation during the operation of the semiconductor chip and the life is shortened.

An object of the present invention is to provide a long-life package for a semiconductor device, which is free from power supply and ground noise generated inside a semiconductor chip and crosstalk generated between bumps.

[0011]

The present invention provides, in a package for a flip-chip semiconductor device, (1) a semiconductor chip, a pad formed on the semiconductor chip, and an internal terminal connected to the pad by a solder bump. When,
The solder bump has a low melting point brazing material which is insulated and electrically connects with the semiconductor chip as a ground potential or a power source potential.

(2) A semiconductor chip, an external terminal connected to a circuit board by solder bumps, and a low melting point brazing material which is insulated from the external terminal and electrically connected to the semiconductor chip as a ground potential or a power supply potential. Have.

Further, the low melting point brazing material is divided into at least two parts, and each is electrically connected to the semiconductor chip so as to input / output an electric signal including a ground potential, a power source potential and a power source.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the present invention, and FIG. 2 is a partially enlarged partially cutaway perspective view of FIG.

In the first embodiment, as shown in FIGS. 1 and 2, a flip chip carrier (or flip chip package) 6 for mounting the semiconductor chip 2 on the flip chip is mounted on the connecting surface of the semiconductor chip 2. Solder bumps 4 for flip chip connection are provided. The solder bumps 4 are provided as terminals for inputting / outputting signals. Further, a low melting point brazing material 5 is provided so as to be insulated from the solder bumps 4 and have a power supply potential (V _DD ) or a ground potential (GND) with respect to the semiconductor chip 2. Solder bump 4 and GND
A chip seal portion 8 is provided around the low melting point brazing material 5 (or V _DD ) so that it can be sealed with a chip. Also,
External bumps 7 are provided on the surface opposite to the surface on which the semiconductor chip 4 is mounted for electrical connection with the circuit board 1. The semiconductor chip 2 is mounted on the above flip chip carrier (or flip chip package) 6 by flip chip connection, and the semiconductor chip 2 is sealed with a cap (ceramic, metal, etc.) 3. In this state, the circuit board 1 is connected.

Here, the radius of the solder bump 4 is 0.15 m.
m, height 0.2 mm, and the distance from the center of the solder bump 4 to the low melting point brazing material 5 is 0.25 mm, the solder bump 41
The electrostatic capacity between the low melting point brazing material 5 and the individual solder bumps 4 is about 5 pF. Further, by setting the low melting point brazing material 5 to the ground potential, the solder bump 4 can have an apparent coaxial structure. Where a is the radius of the solder bump 4, b
Is the distance from the center of the solder bump 4 to the metal pedestal formed by the low melting point brazing material 5, Z ₀ = (μ ₀ / ε ₀ ).
^{Since the} impedance is calculated by the formula of ^1/2 log (a / b), specific impedance matching can be achieved by adjusting the lengths of a and b.

FIG. 3 is a sectional view of a second embodiment of the present invention, and FIG. 4 is a partially enlarged partially cutaway perspective view of FIG.

As shown in FIGS. 3 and 4, the second embodiment is a flip chip carrier (or flip chip package) 6 similar to that of the first embodiment. In the first embodiment, a semiconductor chip is used. 2 and the flip-chip carrier (or flip-chip package) 6 are provided with a low melting point brazing material 5 at ground potential or power supply potential in the second embodiment. It is provided between the substrates 1. That is, the external bumps 7 of the flip chip carrier (or flip chip package) 6 are provided as external terminals for signal input / output, insulated from the external bumps 7 and at the ground potential or the power supply potential with respect to the semiconductor chip 2. A low melting point brazing material 5 is provided on the. The conduction from the semiconductor chip 2 to the low melting point brazing material 5 is conducted via the chip seal portion 8 for sealing the solder bump 4 in the semiconductor chip 2.

FIG. 5 is a plan view of a flip chip carrier according to a third embodiment of the present invention, and FIG. 6 is a perspective view of FIG.

In the third embodiment, as shown in FIGS. 5 and 6, a solder bump 4 for flip-chip connecting a semiconductor chip to a flip-chip carrier (or flip-chip package) 6 for inputting and outputting an electrical signal. And a low melting point brazing material is provided so as to be insulated from the solder bumps 4 and electrically connected to the semiconductor chip. Each of the metal pedestals formed by this low melting point brazing material is divided into at least two so as to become the power supply potential layer 22 and the ground potential layer 21.

Alternatively, the metal pedestal formed by the low melting point brazing material is divided into at least two parts, and the power supply potential layer 22 and the ground potential layer 21 are provided on the circuit board connection side.

[0023]

As described above, in the semiconductor device package of the present invention, the solder bumps for flip chip connection are used as signal input / output terminals, and these solder bumps are individually surrounded so as to have the power supply potential or the ground potential. By providing a metal pedestal formed by a low melting point brazing material,
The noise generated in the semiconductor device can be filtered at a position closer to the generation source, and with this structure, it is not necessary to provide a metallization layer for the power supply potential and the ground potential in the semiconductor device package. The package has the effect of being light, thin, short and compact.

Further, since the solder bump has an apparent coaxial structure when the metal pedestal is set to the ground potential, the diameter of the solder bump is a and the distance from the center of the solder bump to the metal pedestal is b.
Then, the impedance is Z ₀ = (μ ₀ / ε ₀ ) ^1/2
Since it can be given by the expression of log (a / b), there is an effect that impedance matching becomes possible by arbitrarily setting a and b.

Furthermore, since the area connected to the semiconductor chip is increased, the heat radiation effect is increased, and the adhesive strength is increased, and the stress resistance of the solder bump portion due to the difference in thermal expansion coefficient is improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a partially enlarged partially cutaway perspective view of FIG.

FIG. 3 is a sectional view of a second embodiment of the present invention.

FIG. 4 is a partially enlarged perspective view with partial cutaway of FIG.

FIG. 5 is a plan view of a flip chip carrier according to a third embodiment of the present invention.

FIG. 6 is a perspective view of FIG.

FIG. 7 is a partially enlarged cross-sectional view of an example of a conventional semiconductor device package.

FIG. 8 is a partially cutaway perspective view of the semiconductor device package of FIG.

[Explanation of symbols]

1 circuit board 2 semiconductor chip 3 cap 4 solder bump 5 low melting point brazing material 6 flip chip carrier or flip chip package 7 external bump 8 chip seal part 9 cap seal part 21 ground potential layer 22 power supply potential layer 24 ceramic substrate 27 ground metallized layer 28 power source metallization layer 29 external lead 30 internal wiring routing pattern 31 resin 32 pure metal thin film

Claims (3)

[Claims] 1. In a flip-chip semiconductor device package, a semiconductor chip, pads formed on the semiconductor chip, internal terminals connected to the pads by solder bumps, and the solder bumps are insulated from each other. A package for a semiconductor device, comprising a semiconductor chip and a low melting point brazing material that is electrically conductive as a ground potential or a power supply potential. 2. A flip chip semiconductor device package, wherein a semiconductor chip, an external terminal connected to a circuit board by solder bumps, and the external terminal are insulated from each other and electrically connected to the semiconductor chip as a ground potential or a power supply potential. A semiconductor device package characterized by having a low-melting point brazing material that provides electrical continuity. 3. The low melting point brazing material is divided into at least two parts, and each is electrically connected to a semiconductor chip so as to input and output an electric signal including a ground potential, a power source potential and a power source. The semiconductor device package according to claim 1 or 2.