JPH0644202Y2 - Optical signal transmitter / receiver - Google Patents

Description

TECHNICAL FIELD The present invention relates to an optical signal transmitter / receiver used when transmitting a digital optical signal using an optical fiber,
It is suitable for use in an optical signal repeater to which a 3R function is added.

2. Description of the Related Art Conventionally, an optical signal transmission / reception device called an optical signal transmission / reception module having a so-called 3R function of identification reproduction, waveform shaping and timing extraction is known. This transmission / reception module includes a transmission unit and a reception unit. In the transmission unit, input data NRZ-encoded at a clock frequency f ₀ is converted into, for example, a CMI code (or DMI, PF) having a clock frequency 2f _0.
M, MFM code, etc.), this CMI signal is E / O converted (electricity-to-optical conversion) by the light emitting diode and sent to the optical fiber. In addition, in the receiver, the optical CM
The I signal is received by the phototransistor and O / E converted (optical to electrical conversion), and this CMI signal is converted to the NRZ code.
The clock pulse is extracted from the received data. Therefore, by connecting a plurality of transmission / reception modules via an optical fiber to form a so-called optical link, long-distance transmission of optical signals can be performed.

An optical link using such a transceiver module having a 3R function is effective in reducing data jitter due to pulse width variation, phase variation, and the like. However, in the optical link having only the 3R function, the regenerated data after the relay is
The data error due to the error of the self-clock of each repeater is accumulated, which may make it impossible to transmit the data accurately, especially when performing long-distance transmission by multi-stage relay.

In order to solve this problem, a transceiver module with a built-in digital PLL circuit has been proposed and partially commercialized. This transmission / reception module uses the PLL circuit to create a clock that is synchronized with the clock extracted by the reception unit, and based on this clock, the transmission unit converts the NRZ signal obtained from the reception unit into a CMI signal. I have to. Therefore, in the case of an optical link, in each repeater,
Since the outgoing data is synchronized with the input data clock,
Accurate data transmission can be performed without accumulating data errors due to clock errors.

Problems to be Solved by the Invention Since the transceiver module having the conventional 3R function and incorporating the PLL circuit uses the digital PLL circuit, the following problems have occurred.

(1) The circuit becomes complicated, and the design becomes difficult especially when the frequency is high.

(2) As a result, the cost increases, and (3) when high-speed data transmission is performed, high-speed transmission becomes difficult.

(4) Since the frequency handled by the PLL circuit is fixed, it has no versatility and cannot be applied to the existing transceiver module.

Means for Solving the Problems In the present invention, the above-mentioned problems are solved by using an analog PLL circuit in place of the digital PLL circuit.

Embodiment FIG. 1 shows a circuit configuration of a transmitting / receiving module 1 according to the present invention.

This transmission / reception module 1 includes a transmitter 2, a receiver 3, and a PLL.
And the circuit 4. The transmitter 2 has a frequency of 4f ₀
Oscillator 5, switching circuit 6, 1/2 divider 7, synchronization circuit 8, modulation circuit 9, synchronization circuit 10, drive circuit 11 and E / O converter 12 composed of a light emitting diode, etc. An input terminal 13, a clock output terminal 14 and a clock input terminal 15 are provided.

The data input terminal 13 has a clock frequency f ₀ (for example,
f ₀ = 1MHz) and NRZ encoded input data is supplied,
This input data is applied to the synchronizing circuit 8. When the external clock is not supplied to the clock input terminal 15, the changeover switch 6 outputs the signal 4f ₀ obtained from the oscillator 5.
The output pulse of is selected and supplied to the 1/2 frequency divider 7. The 1/2 frequency-divided 2f ₀ clock is applied to the synchronizing circuit 8 to be synchronized with the input data. The synchronized data is converted into PFM code in the modulation circuit 9 based on the clock of 2f ₀ . Of course, code formats such as CMI, DMI, and MFM may be used instead of PFM. This PFM signal drives the O / E converter 12 via the drive circuit 11 and is converted into an optical signal. At the same time, a 2f ₀ clock is output from the output terminal 14 via the synchronization circuit 10.

When the external clock of 2f ₀ is supplied to the clock terminal 15, the switching circuit 6 selects the output pulse of 4f ₀ obtained from the PLL circuit 4 driven in synchronization with the external clock and selects 1/2 minute. Supply to the frequency divider 7. Therefore, the input data is applied to the modulation circuit 9 in synchronization with the clock phase-locked with the external clock.

The PLL circuit 4 is, for example, a VC of frequency 2f ₀ using each CMOS IC.
O16, frequency multiplier 17, phase comparator 18, low-pass filter 19 and other analog PLL circuits
A signal obtained through the frequency multiplication circuit 17 is compared in phase with the external clock by the phase comparator 18, and a control signal is obtained by passing the comparison output to the low-pass filter 19. The output of the VCO 16 is synchronized with the external clock by controlling the capacity of the varicap 20 that constitutes the VCO 16 with this control signal. This VCO output is multiplied by the frequency multiplication circuit 17 and supplied to the 1/2 frequency divider 7 via the switching circuit 6. The output of VCO16 is
Before input, the DC component is cut by the capacitor, and the waveform is shaped by the CMOS inverter in which the resistor is connected in parallel. Therefore, these capacitors, resistors and inverters can be replaced with Schmitt trigger type inverters.

The receiving circuit 3 is an O / E converter 2 including a phototransistor.
1, an amplifier 22, a synchronizing circuit 23, a demodulating circuit 24, an oscillator 25 having a frequency of 16f ₀ , a malfunction prevention circuit 26, a synchronizing circuit 27, etc., and a CD output terminal 28 and a data output terminal 2
9, 30 and a clock output terminal 31 are provided.

The PFM signal received by the O / E converter 21 is amplified by the amplifier 22, then added to the synchronizing circuit 23, and sampled by the 16f ₀ clock supplied from the oscillator 25. The sampled signal is applied to the demodulation circuit 24 and converted into an NRZ signal based on the clock of 16f ₀ . The data of this NRZ signal is output from the output terminal 30, and the inverted output is output terminal.
It is output from 29. At the same time, a part of the output of the demodulation circuit 24 is added to the malfunction prevention circuit 26 and the synchronization circuit 27, and the synchronization circuit 27 outputs the 2f ₀ clock extracted from the input data to the output terminal 31. Further, a signal CD for determining the normal reception of the optical signal is obtained from the terminal 28.

FIG. 2 shows an embodiment in which an optical link is constructed by using n transmitting / receiving modules 1 configured as described above.
The parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In Figure 2, module 1 ₁ for the first-stage transmission, only the transmission section 2 is used. When the data by the NRZ code is input from the input terminal 13, this data is converted into the PFM signal based on the clock from the oscillator 5, and this PFM signal is converted into the E / O signal.
It is converted and sent to the optical fiber 35 _1.

The relay module 1 ₂ is an optical fiber in the receiver 3.
35 O / E changes the optical PFM signal sent from ₁ to demodulation circuit 2
Add to 4. The PLL circuit 4 is operated with the 2f ₀ clock extracted from this input data as an external clock. The modulation circuit 9 outputs the NRZ signal demodulated by the demodulation circuit 24 to the PLL circuit 4
It is converted into the PFM signal again based on the clock synchronized with. The PFM signals are transmitted are E / O conversion on the optical fiber 35 _2. In the relay module, although not shown in FIG. 2, data input / output terminals 13 and 30 are connected to each other and clock input / output terminals 15 and 31 are connected to each other.

In the same manner, the relay modules 1 ₃ ... 1 _n-1 are sequentially sent, and in each relay module, the PLL circuit 4 synchronizes the data with the clock.

Only the receiving unit 3 is used in the last-stage module 1 _n . After the optical CMI signal sent from the optical fiber 35 _n-1 is O / E converted, the NRZ signal is demodulated by the demodulation circuit 23 and obtained at the output terminals 29 and 30, and the clock is output terminal 31.
Can be obtained.

According to the above-described embodiment, since the analog PLL circuit is used, the following effects can be obtained.

(1) Since the VCO 16 and the low-pass filter 19 which compose the PLL circuit 4 are composed of a small number of elements such as a varicap, a resistor, a gate and a capacitor, the circuit structure is simple and can be provided at low cost.

(2) If the gate is a C-MOS gate, a VCO having a relatively high frequency can be realized.

(3) If a choke coil is used for the low pass filter 19, the lock range and stability of the PLL circuit 4 are improved.

(4) Therefore, since a high frequency can be easily handled, high-speed transmission is possible when performing long-distance transmission by multistage relay, and moreover, accurate transmission can be performed without a 1-bit error.

(5) Since the frequency variable range of the VCO is wide, the PLL circuit 4 can be externally connected to the transmitter / receiver module configured to extract the clock from the input data, and the versatility is high. Therefore, it is possible to easily add a PLL circuit to an existing optical link that does not have a PLL circuit and improve the performance of the optical link.

Effect of the Invention High-speed long-distance data transmission can be facilitated by a multi-staged optical link, and accurate data transmission can be performed. Further, it has high versatility, can be easily added to an existing optical link, and can be provided at a lower cost.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of an optical link. In the symbols used in the drawings, 1 ... transmission / reception module 2 ... transmission unit 3 ... reception unit 4 ... PLL circuit 9 ... modulation circuit 24 ... demodulation circuit 27 ... synchronization circuit 31 ... external clock output It is a terminal.

Claims (1)

[Scope of utility model registration request] 1. An optical signal transmitter / receiver having a 3R function of combining data and a first clock, transmitting the combined signal, and separating the combined signal into the data and the second clock after receiving the combined signal. Of the phase comparator, the output of the phase comparator is applied via a low pass filter, and the second clock is phase-compared based on the capacitance value of the varicap. An analog PLL circuit including a VCO in which the frequency of the output clock is set is provided, and the data and the first clock are demodulated from the composite signal based on the output clock of the analog PLL circuit. An optical signal transmitter / receiver.