JPH0643595U - Electronic clock correction circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To make it possible to easily correct the display time even from a position away from the clock. [Structure] Two photodetectors 31, 35 and the photodetector 3
A first comparison circuit 41 that outputs a first detection signal when the output of one of the photodetectors 1 and 35 becomes large, and a second comparison circuit 41 that outputs a second detection signal when the output of the other photodetector becomes large.
The comparison circuit 45 and a first control circuit 51 that outputs the first detection signal as a fast-forward control signal when the first detection signal is intermittent
And a second control circuit 71 that outputs the second detection signal as a fast-return control signal when the second detection signal is intermittent,
The output terminal of the control circuit 51 and the output terminal of the second control circuit 71 are connected to the frequency switching circuit 15, and the output terminal of the second control circuit 71 is also connected to the waveform shaping circuit 21 to control the fast forward control signal or the fast reverse control. When a signal is input, the frequency switching circuit 15 allows a signal having a higher frequency out of the signals from the frequency dividing circuit 12 to pass therethrough, and causes the waveform shaping circuit 21 to output a waveform for inversion by the fast return control signal.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an electronic timepiece such as a digital or analog wall clock, and more particularly to a circuit for performing time adjustment control of an electronic timepiece.

[0002]

[Prior art]

 Even today, in analog watches using hands, a reference signal is output from an oscillation circuit using a crystal oscillator, and the reference signal is divided by a frequency dividing circuit to form a reference frequency signal of 1 Hz. In many cases, the step motor is driven by the reference frequency signal, and the wheel train decelerates the rotation of the step motor to drive the hands, and parent-child watches connected to other watches by signal lines are normally open. Many analog wall clocks move the hands by rotating the crown when adjusting the display time with a finger.

[0003] Some digital electronic timepieces fast-forward or fast-return the display time by pressing the fast-forward operation button or the fast-reverse operation button. For example, as shown in FIG. 8, a crystal oscillator is used. The reference signal from the oscillating circuit 11 is divided by the dividing circuit 12, and the reference frequency signal φ1 of several hertz and the reference frequency signal φ2 of 1 hertz are sent to the frequency switching circuit 15, and the reference frequency signal φ2 of 1 hertz is usually generated. In the digital clock in which the φ2 reference frequency signal is output from the frequency switching circuit 15, the up / down counter 26 counts it, the count value is sent to the driver 27, and the time is displayed on the display unit 28. A fast-forwarding operation button 13 and a fast-rewinding operation button 14 are provided as the frequency switching circuit by operating the fast-forwarding operation button 13. The second AND circuit 17 in 15 is closed and the first AND circuit 16 is opened to output the φ1 reference frequency signal to the up / down counter 26 to speed up the increase of the count value and fast forward the display time of the display unit 28. , There is one that operates the fast-reverse operation button 14 to open the first AND circuit 16 and switches the up-down counter 26 to down-count, and decreases the count value of the up-down counter 26 to rewind the display time. In recent years, digital clocks have been put into practical use, and those that enable time adjustment by remote control have also been put into practical use. For example, some clock bodies preset the count value of another clock body to the up / down counter of another clock body. (For example, JP-A-50-122961).

Further, in the analog type electronic timepiece, not only the one in which the hands are corrected by the crown as described above, but also the hands are fast-forwarded or fast-returned by pressing the fast-forward operation button or the fast-reverse operation button as in the digital timepiece. Furthermore, in recent years, it has been attempted to correct the display with the hands by remote control from a position remote from the timepiece by using infrared rays or ultrasonic waves even in an analog timepiece.

[0005]

[Problems to be solved by the device]

 Electronic clocks are also widely used today as wall clocks, and long-life wall clocks that use a battery as a drive source have been commercialized. Since these clocks can be driven extremely accurately, the time correction is extremely rare, but sometimes it is necessary to correct the display time.

[0006] However, these long-life timepieces usually do not need to touch the timepiece body, so they are often attached to a position that is difficult to reach, and when it becomes necessary to adjust the time, a stand is used. There were some inconveniences, such as having to make corrections with the crown or the operation buttons after removing the clock from the wall. Although it is proposed that the remote control device such as ultrasonic waves should be used for remote correction as described above, a dedicated remote control device for the watch alone should be an accessory of an electronic watch such as a wall clock. Has the drawback of not being practical.

[0007]

[Means for Solving the Problems]

 According to the present invention, two photodetectors, which are arranged separately on the left and right of the front surface of the watch body and have similar characteristics, and the output of the first photodetector of the two photodetectors is the second photodetector. A first comparison circuit that outputs a first detection signal when the output of the second photodetector is larger than the output of the first photodetector, and a second comparison circuit that outputs a second detection signal when the output of the second photodetector is larger than the output of the first photodetector A comparison circuit is provided, and a first control circuit that passes the first detection signal that is input when the first detection signal is interrupted several times, and a second detection signal that is input when the second detection signal is interrupted several times And a second control circuit for controlling the output terminals of the first control circuit and the second control circuit to the frequency switching circuit, and the output terminal of the second control circuit to the control terminal of the up-down counter or the waveform shaping circuit. It is also connected to the terminal and the frequency is changed by the signal from the first control circuit and the second control circuit. The switching circuit is increasing the frequency of the reference frequency signal passing through, the up-down counter and a waveform shaping circuit, to as to perform output of the down count or reverse rotation signal by a signal from the second control circuit.

[0008]

[Work]

 The present invention uses two photodetectors having similar characteristics. When the output of the first photodetector is larger than the output of the second photodetector, the first comparison circuit outputs a detection signal, and this detection If the signal is interrupted several times, the first control circuit passes the detection signal from the first comparison circuit as a fast-forward control signal, and the signal passed through the first control circuit causes the frequency switching circuit to raise the frequency of the reference signal. , It is possible to fast forward the display time by illuminating the detection element of the first photodetector intermittently brighter than the detection element of the second photodetector, and the output of the second photodetector is the first light. When the output of the detector is larger than the output of the detector, the second comparison circuit outputs the detection signal, and if the detection signal is interrupted several times, the second control circuit allows the detection signal from the second comparison circuit to pass, and the second control Frequency switching depending on the signal passed through the circuit Since the frequency of the reference signal is increased on the path and the signal for reversing is output to the waveform shaping circuit, or the up / down counter is down-counted, the second photodetector is intermittently operated more than the first photodetector. By illuminating brightly, you can rewind the time display.

[0009]

【Example】

 An embodiment of the correction circuit according to the present invention is used for an analog timepiece as shown in FIG. 1, in which a frequency dividing circuit 12 divides a reference signal from an oscillation circuit 11 using a crystal oscillator to obtain a frequency. A plurality of reference frequency signals different from each other are formed and a reference frequency signal φ1 of several hertz and a reference frequency signal φ2 of 1 hertz are sent to the frequency switching circuit 15, and normally, a reference frequency signal φ2 of 1 hertz is switched to the frequency switching circuit 15. Output to the drive waveform shaping circuit 21 as a hand movement reference signal. Based on the hand movement reference signal, the drive waveform shaping circuit 21 outputs the duty ratio of the drive reference signal by a plurality of reference frequency signals directly input from the frequency dividing circuit 12. And forms a forward rotation waveform or a reverse rotation waveform and outputs the drive reference signal to the motor drive circuit 23. The motor drive circuit 23 outputs the drive reference signal based on the drive reference signal. A voltage is applied to the drive motor 25 to rotate the drive motor 25 at a predetermined speed, thereby driving the pointer at a predetermined speed, and the photodetectors 31, 35 using CdS cells or the like. Are arranged separately on the left and right sides of the dial plate 29 as shown in FIG. 5, and the outputs of the photodetectors 31 and 35 are input to the first comparison circuit 41 and the second comparison circuit 45, respectively. The output of the circuit 41 is input to the first control circuit 51, the output of the second comparison circuit 45 is input to the second control circuit 71, and both the output of the first control circuit 51 and the output of the second control circuit 71 are frequency switched. In addition to being input to the circuit 15, the output of the second control circuit 71 is also input to the drive waveform shaping circuit 21.

As shown in FIG. 2, the first photodetector 31 has a detection element 32 such as a CdS cell and a detection resistor 33 in series, and the second photodetector 35 also has the same configuration. The detection element 36 and the detection resistor 37 are connected in series, and the detection element 32 of the first photodetector 31 and the detection element 36 of the second photodetector 35 are elements having similar characteristics. The detection resistor 33 of the detector 31 and the detection resistor 37 of the second photodetector 35 are resistors having the same resistance value. When the illuminance of the light radiated to both photodetectors 31 and 35 is equal, both resistors are used. The output values of the detectors 31 and 35 are made equal.

The output terminals of the first photodetector 31 and the second photodetector 35 are connected to the first comparison circuit 41 and the second comparison circuit 45, respectively. As shown in FIG. 2, it is composed of a diode and a comparator. For example, the output terminal of the first photodetector 31 is connected to the reference input terminal of the first comparator 43 via the diode 42 to detect the second photodetector. The output terminal of the comparator 35 is directly connected to the comparison input terminal of the first comparator 43, and the second comparator circuit 45 is also composed of a diode and a comparator like the first comparator circuit 41. The output terminal of 31 is connected to the comparison input terminal of the second comparator 47, and the output terminal of the second photodetector 35 is connected to the reference input terminal of the second comparison detector 47 via the diode 46.

Therefore, when the first photodetector 31 and the second photodetector 35 receive light of the same brightness, the first photodetector 31 and the second photodetector 35 have detection outputs of substantially equal values. Are output to the A signal and the B signal respectively, and in the first comparison circuit 41, the first detection output from the first photodetector 31 receives the forward voltage drop of the diode and is input to the first comparator 43. , The C signal which is the output from the first comparison circuit 41 is set to the L level, and the second detection output from the second photodetector 35 in the second comparison circuit 45 has a slight potential due to the forward voltage drop of the diode. The D signal which is low and is output from the second comparison circuit 45 is also set at the L level.

When the illuminance on the first photodetector 31 becomes larger than the illuminance on the second photodetector 35, the first detection output which is the A signal becomes larger than the second detection output which is the B signal. When the difference between these two signals becomes larger than the forward voltage drop of the diode, the C signal which is the output of the first comparison circuit 41 becomes H level, as shown in FIG. The detection signal is output, and when the illuminance to the second photodetector 35 becomes larger than the illuminance to the first photodetector 31 by a certain amount or more, the D signal output from the second comparison circuit 45 The second comparison circuit 45 outputs the second detection signal of H level.

As shown in FIG. 3, the first control circuit 51 to which the first detection signal is input includes three counters, four D-flip-flops, four AND circuits and one OR circuit. The output terminal of the first comparison circuit 41 is connected to the reset input terminal of the first counter 52 and the reset input terminal of the second counter 53 via the first inverter 55. -Connect the clock input terminal of the flip-flop 59 and the input terminal of the sixth AND circuit 65, and connect the carry output terminal of the first counter 52 to the clock input terminal of the first D-flip-flop 56 and the input terminal of the fourth AND circuit 62. The D input terminal of the first D-flip-flop 56 is connected to the H level power source, and the Q output terminal of the first D-flip-flop 56 is connected to the D-input of the second D-flip-flop 57. The inverted Q output terminal of the first D-flip-flop 56 is connected to the input terminal of the fifth AND circuit 63 and the reset input terminal of the third counter 54, and the Q-output terminal of the second D-flip-flop 57 is connected to the output terminal. Is connected to the input terminal of the fourth AND circuit 62, the output terminal of the fourth AND circuit 62 is connected to the clock input terminal of the third D-flip-flop 58, and the D input terminal of the third D-flip-flop 58 is connected to the H level power supply. The Q output terminal of the third D-flip-flop 58 to the D input terminal of the fourth D-flip-flop 59, the inverted Q output terminal of the third D-flip-flop 58 to the input terminal of the third AND circuit 61, and The output terminal of the 3-AND circuit 61 is connected to the clock input terminal of the third counter 54, and the carry output terminal of the third counter 54 is connected to the third OR circuit 67 and the second D-. It is connected to the reset terminal of the lip flop 57 and the reset input terminal of the fourth D-flip flop 59, the Q output terminal of the fourth D-flip flop 59 is the input terminal of the sixth AND circuit 65, and the second counter. The carry output terminal of 53 is connected to the input terminal of the fifth AND circuit 63 and the reset input terminal of the third D-flip-flop 58, and the output terminal of the fifth AND circuit 63 is the input terminal of the third OR circuit 67. The output terminal of the third OR circuit 67 is connected to the reset input terminal of the first D-flip-flop 56, and the clock input terminals of the first counter 52 and the second counter 53 and the remaining inputs of the third AND circuit 61 are connected. The terminal is connected to the reference signal output terminal of the frequency divider circuit 12, and the output terminal of the sixth AND circuit 65 is used as a fast-forward control signal output terminal to switch the frequency. It is intended to be connected to the input terminal of the second OR circuit 19 at 15.

The count time of the third counter 54 is set as a count time larger than the sum of the set time of the first counter 52 and the set time of the second counter 53, and the count time of the first counter 52 and the second counter 53 is set. The counter 53 is reset by an L-level reset signal, the third counter 54 is a counter reset by an H-level reset signal, and the Q output terminal of the first D-flip-flop 56 is a fifth OR gate. The Q output terminal of the second D-flip flop 57 is connected to the first pilot driver 95 via the circuit 91, the second pilot driver 96 is connected to the second pilot driver 96 via the sixth OR circuit 92, and the Q output terminal of the third D-flip flop 58 is connected to the second pilot driver 96. It is connected to the third pilot driver 97 via the 7-OR circuit 93.

Therefore, the first photodetector 31 is irradiated with light stronger than the second photodetector 35, and as shown in FIG. 4, the first detection output of the A signal is higher than the second detection output of the B signal. When it increases, the H-level first detection signal is output to the C signal, and the reset state of the first counter 52 is released. When the output of the first detection signal is continued for a certain period of time, the first counter 52 outputs a carry signal to the E signal, and the first D-flip-flop 56 sets the F signal, which is its Q output, to the H level. The G signal, which is the inverted Q output, is set to L level to release the reset state of the third counter 54 and close the fifth AND circuit 63.

Next, when the illuminances on the first photodetector 31 and the second photodetector 35 become equal and the output of the first detection signal from the first comparison circuit 41 is stopped, the first counter 52 is turned on. The reset state of the second counter 53 is released and the reset signal of the second counter 53 is released. When the carry signal is output as the I signal from the second counter 53 after the required time set in the second counter 53, the second D-flip-flop The J signal, which is the Q output of 57, becomes H level, and the fourth AND circuit 62 is opened.

In this state, when only the illuminance to the first photodetector 31 becomes high again, the reset state of the first counter 52 is released again by the first detection signal, and the carry signal is output from the first counter 52. Then, the carry signal has the M signal, which is the Q output of the third D-flip-flop 58, at the H level and the N signal, which is the inverted Q output, is at the L level because the fourth AND circuit 62 is opened. The 3-AND circuit 61 is closed and the counting of the third counter 54 is stopped.

Then, once the illuminance difference between the first photodetector 31 and the second photodetector 35 has disappeared, when the illuminance on the first photodetector 31 increases again, the first comparison circuit 41 outputs the illuminance. The O signal, which is the Q output of the fourth D-flip-flop 59, becomes H level by the first detection signal that is generated, the sixth AND circuit 65 is opened, and the detection signal is switched from the sixth AND circuit 65 as a fast-forward control signal by frequency switching. It is sent to the circuit 15, and the first AND circuit 16 in the frequency switching circuit 15 is opened to pass the φ 1 reference frequency signal from the frequency dividing circuit 12, and the frequency of the hand movement reference signal input to the drive waveform shaping circuit 21. To increase the rotation of the drive motor 25 and thus the speed of the pointer.

When the fast-forward control signal is not output from the first control circuit 51, the first OR circuit 16 is closed and the second AND circuit 17 is opened, so that the normal hand movement reference signal is 1 Hz. The reference frequency signal .phi.2 is output from the frequency switching circuit 15 through the first OR circuit 18. Then, if there is no difference in illuminance between the first photodetector 31 and the second photodetector 35 and the state in which the output of the first detection signal from the first comparison circuit 41 is stopped continues for a certain period of time, the second counter 53 To carry signal to I signal, the third D-flip-flop 58 is reset and the N signal becomes H level, the third AND circuit 61 is opened, the third counter 54 restarts counting, and the third counter 54 When the carry signal is output, the first D-flip-flop 56, the second D-flip-flop 57 and the fourth D-flip-flop 59 are reset, and the first control circuit 51 returns to the initial state.

As described above, the first control circuit 51 causes the difference in illuminance between the two photodetectors 31 and 35 so that the illuminance to the first photodetector 31 becomes large, and the first comparison circuit 41 outputs the first illuminance to the first photodetector 31. After the detection signal is output and this state continues for a certain period of time, the difference in illuminance to both photodetectors 31 and 35 disappears, and the time when the first detection signal is not output is interrupted for a predetermined period of time, and again due to the difference in illuminance. When the output state of the first detection signal continues for a certain period of time, the first detection signal is allowed to pass, and thereafter, the first detection signal is output to the frequency switching circuit 15 as a fast-forward control signal.

The illuminance difference between the first photodetector 31 and the second photodetector 35 is accidentally generated, and the first detection signal is output one-off. When the Q output of the first D-flip-flop 56 becomes H level or the Q output of the second D-flip-flop 57 changes to H level even if it is not output twice intermittently, The carry signal of the counter 54 resets the first D-flip-flop 56 and the second D-flip-flop 57, and the first control circuit 51 does not output the fast-forward control signal.

If the second control circuit 71 also has the same circuit configuration as the first control circuit 51, the first photodetector 31 and the second photodetector 31 are arranged so that the illuminance of the second photodetector 35 is increased. If the second comparison circuit 45 outputs the second detection signal due to an illuminance difference with 35, if the second detection signal output to the D signal is intermittent like the first detection signal, The counter 72 and the fifth counter 73 operate similarly to the first counter 52 and the second counter 53, and the fifth D-flip-flop 76, the sixth D-flip-flop 77, the seventh D-flip-flop 78, and the eighth D-flip-flop. 79 sequentially operates to open and close the seventh AND circuit 81 to the ninth AND circuit 83 as appropriate, and the tenth AND circuit 85 opens to pass the second detection signal, and the second control circuit 71 makes the second detection circuit. Signal The R signal is output as a fast return control signal, the first AND circuit 16 of the frequency switching circuit 15 is opened, and the second AND circuit 17 is closed to increase the frequency of the hand movement reference signal and at the same time shape the drive waveform. The drive reference signal output from the circuit 21 is used as a signal for reverse rotation, and the drive motor 25 can be reversely rotated to quickly return the pointer.

The illuminance difference between the first photodetector 31 and the second photodetector 35 is accidentally generated, and the second detection signal is output sporadically. If the fifth counter 74 carries out no output twice, the fifth D-flip-flop 76 and the sixth D-flip-flop 77 are reset by the carry signal of the sixth counter 74, and the seventh counter 74 is also stored in the second control circuit 71. Similarly, the fast-reverse control signal is not output by the action of, and the operation does not occur.

Further, as shown in FIG. 3, the Q output terminal of the fifth D-flip-flop 76, the Q output terminal of the sixth D-flip-flop 77, and the Q output terminal of the seventh D-flip-flop 78 in the second control circuit 71. Are also connected to the fifth OR circuit 91, the sixth OR circuit 92, and the seventh OR circuit 93, respectively, and the first pilot lamp 101 to the third pilot lamp 103 are arranged on the dial plate 29 as shown in FIG. That is, when an illuminance difference is provided between the first photodetector 31 and the second photodetector 35 so as to make the first photodetector 31 or the second photodetector 35 brighter, the first pilot lamp 101 is turned on after the first fixed time elapses. Turn on the lamp to notify the passage of time, and when the specified time has elapsed after eliminating the illumination difference, prompt the second pilot lamp 102 to light up and brighten one photodetector, and set the illumination difference again. Then, after a certain period of time, the third pilot lamp 103 lights up to indicate that the pointer can be corrected, and the light irradiation can be interrupted very easily.

When used for a digital timepiece, as shown in FIG. 6, the output terminals of the first control circuit 51 and the second control circuit 71 are connected to the frequency switching circuit 15, as in the case of an analog timepiece. At the same time, the output terminal of the second control circuit 71 is connected to the up-count-down count switching control terminal of the up-down counter 26 in place of the drive waveform shaping circuit 21, and the first photodetector 31 and the second photodetector 35 are connected. As shown in FIG. 7, and are provided at appropriate positions on both sides of the front face of the watch.

As described above, in this embodiment, the illuminance difference between the first photodetector 31 and the second photodetector 35 provided on the front surface of the timepiece is adjusted so as to brighten one of the first photodetector 31 and the second photodetector 35. Since it is possible to correct the display time with the hands etc. by providing it, it is possible to intermittently repeat illuminating the half face of the dial face such as the dial 29 with a suitable lighting tool from a remote place. The display time can be adjusted, and the time of a clock placed out of reach can be easily adjusted.

[0028]

The correction circuit of the electronic timepiece according to the present invention has two photodetectors arranged separately on the left and right of the front face of the timepiece, and the illuminance of one photodetector is the other photodetector. The first comparison circuit that outputs a detection signal when the illuminance becomes larger than the illuminance of the other, and the detection signal is output when the illuminance to the other photodetector becomes larger than the illuminance of the one photodetector. And a second control circuit, and further has a first control circuit that outputs the detection signal from the first comparison circuit as a fast-forward control signal after the detection signal from the first comparison circuit is intermittent under a predetermined condition. By connecting the fast-forward control signal output terminal of the first control circuit to the frequency switching circuit, the frequency of the reference frequency signal from the frequency switching circuit is increased by the fast-forwarding control signal, thereby enabling the fast-forwarding of the display time. Also, the detection signal from the second comparison circuit Has a second control circuit that outputs the detection signal from the second comparison circuit as a fast-return control signal after being interrupted under a predetermined condition. The fast-return control signal output terminal of the second control circuit has a frequency switching function. Circuit and drive waveform shaping circuit or up / down counter, and uses the fast-return control signal to increase the frequency of the reference frequency signal output from the frequency switching circuit, and the drive reference output from the drive waveform shaping circuit. The signal is switched to the signal for reverse rotation, or the up / down counter is switched to the down count so that the displayed time can be rewound quickly.Therefore, by operating to make one half of the watch brighter, fast forward or fast rewind is performed. The clock can be adjusted, and the time can be adjusted from a distant position without using a dedicated operating device such as an appropriate lighting device. Nau that the electronic timepiece can, a correction circuit which can be a timepiece that enables easy time correction in case necessary disposed at positions such as out of reach.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an analog electronic timepiece incorporating a correction circuit according to the present invention.

FIG. 2 is a diagram showing a specific example of a photodetector and a comparison circuit in a correction circuit according to the present invention.

FIG. 3 is a diagram showing a specific example of a control circuit in a correction circuit according to the present invention.

FIG. 4 is a time chart diagram showing each signal in the control circuit in the correction circuit according to the present invention.

FIG. 5 is a view showing the external appearance of an analog electronic timepiece incorporating a correction circuit according to the present invention.

FIG. 6 is a circuit block diagram of a digital electronic timepiece incorporating a correction circuit according to the present invention.

FIG. 7 is a view showing the external appearance of a digital electronic timepiece incorporating a correction circuit according to the present invention.

FIG. 8 is a circuit block diagram of a conventional digital electronic timepiece.

[Explanation of symbols]

11 oscillator circuit 12 frequency divider circuit 15 frequency switching circuit 21 drive waveform shaping circuit 23 motor drive circuit 25 drive motor 31 first photodetector 35 second photodetector 41 first comparison circuit 45 second comparison circuit 51 first control Circuit 71 Second control circuit 101, 102, 103 Pilot lamp

Claims (1)

[Scope of utility model registration request] 1. A photodetector, which is arranged separately on the left and right of the front surface of a timepiece body and has similar characteristics, and a first photodetector connected to each output terminal of the two photodetectors. A first comparison circuit that outputs a first detection signal when the output is larger than the output of the second photodetector, and an output of the second photodetector that is connected to each output terminal of the two photodetectors. A second comparison circuit that outputs a second detection signal when the output is larger than the output of the first photodetector, and is connected to the detection signal output terminal of the first comparison circuit to input the first detection signal several times. A first control circuit that passes a first detection signal that is input within a predetermined time after that when intermittent,
A second control circuit which is connected to the detection signal output terminal of the second comparison circuit, and which allows the second detection signal input within a predetermined time to pass when the input of the second detection signal is interrupted several times, An electronic device characterized in that the output terminals of the control circuit and the second control circuit are connected to the frequency switching circuit, and the output terminal of the second control circuit is also connected to the control terminal of the up-down counter or the control terminal of the waveform shaping circuit. Clock correction circuit.