JPH0640574B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a structure for reducing coupling between bit lines.

In a semiconductor memory device, as the density and the degree of integration are advanced and the operation speed is improved, performance deterioration and malfunction due to capacitive coupling between wirings are becoming a problem.

In particular, in a dynamic type semiconductor memory device (D-RAM) in which information is stored in a capacitor, the bit line pair used for reading information is an open bit line connected to the left and right of a sense amplifier. Method D
-A high-density and high-density D-RAM in the RAM
A stacked capacitor structure is used as a means for increasing the size of the memory device. In such a structure, the distance between the bit lines arranged in parallel is very narrow, and the coupling capacitance between the bit lines increases so that the memory device is There is a demand for development of means for reducing the coupling between bit lines because the (memory) is apt to malfunction.

[Conventional technology]

FIG. 2 is a plan view (a), AA sectional view (b) and B- showing a conventional structure of an open bit line type D-RAM which uses a stacked capacitor structure to obtain a high degree of integration. B
It is a sectional view (c).

In the figure, 1 is a semiconductor substrate, 2 is an isolation insulating film, 3 is a source diffusion region, 4 is a drain diffusion region, 5 is a gate insulating film, 6
a, 6b, 6c are word lines made of a first-layer polycrystalline silicon layer (PA), 7 is a first interlayer insulating film, and 8a, 8b, 8c are second-layer polycrystalline silicon layers (PB). 1 is a capacitor electrode, 9 is a dielectric film, 10 is a third polycrystalline silicon layer (P
C) second capacitor electrode, 11 is a window portion formed in the second capacitor electrode, 12 is a second interlayer insulating film, 13
a is a contact window that connects the source region to the bit line, 13
Reference numeral b is a contact window connecting the first capacitor electrode and the drain diffusion region, 14a, 14b and 14c are bit lines made of aluminum, and 15 is a cover insulating film.

In such a conventional structure, when the degree of integration is increased and the bit line interval is narrowed, the increased coupling capacitance between the bit lines causes the problems of performance deterioration and malfunction of the storage device (memory) as described above. .

The reason will be described below with reference to FIGS. 3 to 7.

FIG. 3 is a circuit diagram of an open bit line type D-RAM having the above-mentioned stacked capacitor structure.

As described above, in the open bit line type D-RAM, BL ₁ , ▲ are arranged to the left and right of the sense amplifiers SA and SA _i.
A pair of a plurality of bit lines BL, ▲ ▼, such as ▼ ₁ , BL ₂ , ▲ ▼ ₂ , BL _i , ▲ ▼ _i, etc., are connected in parallel and are connected to each other, and WLs that intersect the bit lines in a matrix form,
A memory cell MC having a one-transistor / one-capacitor structure including a transistor Tr and a capacitor C is connected to each intersection with a plurality of word lines such as WL _i .

In the above structure, only a small voltage appears on the bit line during reading. Therefore, by forming the bit line electrically symmetrically, that is, symmetrically in terms of both pattern and layout, a desired cell can be obtained. When you access
Due to the slight charge accumulated in the cell, a very small difference voltage is generated in the bit line as compared with the paired bit lines, and the difference voltage is amplified by the sense amplifier to read the memory information. .

Next, the read operation will be described in more detail with reference to the potential fluctuation diagram shown in FIG. 4 and the schematic circuit diagram of FIG.

In FIG. 4, (a) shows the case of "0" read, and (b) shows the case of "1" read. In the case of "0" read, the V _SS potential is "1" in the cell. In the case of read, the V _CC potential is stored in each cell.

In reading, the bit lines BL and ▲ ▼ are charged up to 1/2 the voltage difference between V _CC and V _SS to bring them into a floating state prior to calling the cell, and then the word line WL is set to high ( High) and the desired cell string is called.

Then, for example, the cell MC selected by the bit line BL _i
When the information on the V _SS potential is stored in the capacitor C _i of _i , the bit which is at the 1/2 V _CC voltage as shown in the potential fluctuation diagram in the case of the “0” lead shown in FIG. 4 (a). Charge flows from the line BL _i into the capacitor C _i at the V _SS potential,
The potential of the bit line BL _i drops slightly by ΔV _BL .

When the information on the V _CC potential is stored in the capacitor C _i of the cell MC _i selected by the bit line BL _i , the potential fluctuation diagram in the case of "1" read shown in FIG. 4 (b) is obtained. Then, charges flow into the bit line BL _i that was at the voltage of 1/2 V _CC from the capacitor C _{i in} which information was stored at the V _CC potential, and the potential of the bit line slightly increased by ΔV _BL .

Then, the change ΔV _BL of these potentials is compared and amplified by the sense amplifier with the potentials of the paired bit lines ( _i ) which do not change, and is read as information of “0” or “1”.

This change in potential is as shown in the following first equation.

ΔV _BL = (1/2) V _CC Cs / (C _BL + Cs) (1) where Cs is the capacitance of the cell capacitor (C _i ) and C _BL is the capacitance of the bit line (BL _i ).

In the actual case, as shown in the schematic circuit diagram of FIG. 5, C _BL is adjacent to and parallel to the coupling capacitance C _BL1 with respect to the fixed electrode such as the electrode wiring or the diffusion layer disposed under the bit line. It is divided into two large coupling capacitances C _BL2 having a plurality of bit lines running at the same time.

The problem is how ΔV _BL changes in reading in such a state. However, when the same information is read from all cells, the potentials of all bit lines change similarly. Therefore, C
_{BL2, that} is, the capacitance with respect to other bit lines becomes invisible, and the amplitude of ΔV _BL ′ is large both in the case of “0” read and in the case of “1” read as shown in the potential fluctuation diagrams of FIGS. 6 (a) and 6 (b). There is no particular problem because it can be taken.

The second formula below represents this state.

ΔV _BL ′ = (1/2) V _CC Cs / (C _BL1 + Cs) (2) However, when only one bit has reverse information, that is, the bit line BL _i is “1” information and the other bit lines are When all the information is “0”, as shown in the potential fluctuation diagram of FIG. 7 (a),
Further, when the bit line BL _i is “0” information and all the other bit lines are “1” information, as shown in the potential fluctuation diagram of FIG. Since the charge accumulated in the capacitor C _i or the bit line BL _i is consumed, the amplitude of the difference voltage ΔV _BL ″ becomes very small, and sometimes the problem of information inversion occurs.

This state is represented by the following third formula.

ΔV _BL ″ = [(1/2) V _CC Cs / (C _BL1 + C _BL2 + Cs)] − [ΔV _BL ′ C _BL2 / (C _BL1 + C _BL2 + Cs)] = [(1/2) V _CC Cs / ( C _BL + C _BL2 + Cs)] × [1-C _BL2 / (C _BL1 + Cs)] (3) where ΔV _BV ′ = (1/2) V _CC Cs / (C _BL1 + Cs) D-RAM Since the capacitance Cs of the cell capacitor is very small, the above equation is used when the coupling capacitance C _BL2 between the bit lines becomes larger than the coupling capacitance C _BL1 between the bit line and the fixed electrode below the bit line. , ΔV _BL ″ becomes negative, indicating that the information may be inverted.

[Problems to be solved by the invention]

For the reasons explained above, in the open bit line type D-RAM having the conventional structure, the coupling capacitance between the bit lines is significantly increased when highly integrated, which causes a problem of deterioration of information detection sensitivity and malfunction. Was occurring.

[Means for solving problems]

The above problems include a memory having a stacked capacitor structure, wherein a pair of electrodes of the stacked capacitor is
An integral-structured conductor layer, which collectively covers the plurality of bit lines and is connected to one potential, is adjacent to the upper portions of the plurality of bit lines arranged side by side above the electrodes connected to the constant potential. This is solved by the semiconductor memory device according to the present invention which is provided as described above.

[Action]

That is, in the semiconductor memory device of the present invention, a fixed potential electrode layer of an integral structure connected to one potential is provided above the bit lines arranged side by side to connect the bit lines. By absorbing most of the generated electric force lines in the fixed potential electrode layer, the coupling capacitance between the bit lines is reduced, which reduces the information detection sensitivity in a highly integrated semiconductor memory device. The problem of malfunction is prevented.

〔Example〕

Hereinafter, the present invention will be specifically described with reference to the embodiments shown in the drawings.

FIG. 1 is a plan view (a), an AA sectional view (b) and a BB sectional view (c) of an embodiment of the present invention in an open bit line type D-RAM having a stacked capacitor structure. is there.

In the figure, 1 is a semiconductor substrate, 2 is an isolation insulating film, 3 is a source diffusion region, 4 is a drain diffusion region, 5 is a gate insulating film, and 6a, 6b and 6c are first-layer polycrystalline silicon layers (PA). A word line, 7 is a first interlayer insulating film, 8a, 8b and 8c are first capacitor electrodes made of a second-layer polycrystalline silicon layer (PB), 9 is a dielectric film, and 10 is a third-layer poly-silicon film. A second capacitor electrode made of a crystalline silicon layer (PC), 11 is a window portion formed in the second capacitor electrode, 12 is a second interlayer insulating film, 13a is a contact window connecting the source region and the bit line, 13b is a contact window connecting the first capacitor electrode and the drain region, 14a, 14b and 14c are bit lines made of aluminum, 15 is a cover insulating film, 16 is a third interlayer insulating film, 17 is an aluminum layer, etc. The fixed potential electrode layer is shown.

As shown in the figure, in the structure of the present invention, the bit lines 14a, 14b, 14c, etc. are parallel to the upper portion of the second capacitor electrode (counter electrode) 10 via the second interlayer insulating film 12 as in the conventional case. It is formed of a conductive layer of aluminum (Al) or the like so as to be formed side by side and collectively cover the bit lines 14a, 14b, 14c and the like below the bit lines with the third interlayer insulating film 16 interposed therebetween. The fixed electrode layer 17 connected to the potential of V _SS , for example, is provided, and the second capacitor electrode (counter electrode) 10 and the fixed electrode 17 to which the bit lines 14a, 14b, 14c and the like are connected to a constant potential. It becomes a structure sandwiched by.

Here, the thickness of the second interlayer insulating film 12 and the third interlayer insulating film 16 is appropriately a fraction of the bit line interval, that is, about 1 μm.

Further, since the fixed electrode layer 17 does not pass an electric current, it is sufficient if the fixed electrode layer 17 has a thickness of about 2000 to 3000Å.

With such a structure, as shown in FIG. 6C, most of the electric force lines e generated from the bit lines 14a, 14b, 14c, etc. except for a part between the adjacent bit lines, Since it is absorbed by the second capacitor electrode (counter electrode) 10 and the fixed electrode 12 which are arranged close to the upper part and the lower part, the coupling between the bit lines is greatly reduced, and the coupling between the bit lines is caused. It is possible to prevent a decrease in information detection sensitivity and malfunction.

The present invention is of course applicable to semiconductor memory devices other than the open bit line type D-RAM having the stacked capacitor structure used in the above description.

〔The invention's effect〕

As described above, according to the present invention, the coupling between the bit lines arranged in parallel can be greatly reduced, so that the high density and high integration can be achieved without lowering the detection sensitivity of the stored information or malfunctioning. It is possible to manufacture the semiconductor memory device having the above structure.

[Brief description of drawings]

FIG. 1 is a plan view (a), an AA sectional view (b) and a BB sectional view (c) of an embodiment of the present invention in an open bit line type D-RAM having a stacked capacitor structure. 2 is a plan view (a), an AA sectional view (b) and a BB sectional view (c) of the conventional structure, FIG. 3 is a schematic circuit diagram of the conventional structure, and FIG. 4 (a). , (B) is a potential fluctuation diagram during a read operation in the conventional structure, FIG. 5 is a schematic circuit diagram showing the coupling state between bit lines in the conventional structure, and FIGS. 6 (a) and 6 (b) are general diagrams in the conventional structure. 7A and 7B are potential fluctuation diagrams when the same information is read from all bit lines, and FIGS. 7A and 7B are potential fluctuation diagrams when the reverse information is similarly read with a 1-bit difference. In the figure, 1 is a semiconductor substrate, 2 is an isolation insulating film, 3 is a source diffusion region, 4 is a drain diffusion region, 5 is a gate insulating film, 6a, 6b and 6c are word lines, 7 is a first interlayer insulating film, 8a, 8b, 8c are first capacitor electrodes made of, 9 is a dielectric film, 10 is a second capacitor electrode, 11 is a window formed in the second capacitor electrode, and 12 is a second interlayer insulating film. , 13a is a contact window connecting the source region and the bit line, 13b is a contact window connecting the first capacitor electrode and the drain region, 14a, 14b, 14c are bit lines, 15 is a cover insulating film, 16 is a third An interlayer insulating film, 17 is a fixed potential electrode layer made of an aluminum layer, and e is a line of electric force.

Claims (1)

[Claims] 1. A memory cell having a stacked capacitor structure, comprising a pair of electrodes of the stacked capacitor, above a plurality of bit lines arranged side by side above an electrode connected to a constant potential. A semiconductor memory device comprising: an electrically conductive layer having an integral structure, which is provided in close proximity to the plurality of bit lines and is connected to one potential.