JPH0638431B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0638431B2 JPH0638431B2 JP14338686A JP14338686A JPH0638431B2 JP H0638431 B2 JPH0638431 B2 JP H0638431B2 JP 14338686 A JP14338686 A JP 14338686A JP 14338686 A JP14338686 A JP 14338686A JP H0638431 B2 JPH0638431 B2 JP H0638431B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resist
- resist layer
- gate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- 239000007789 gas Substances 0.000 description 10
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特に化合物半
導体からなる半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device made of a compound semiconductor.
近年、半導体装置の高性能化が進み、Ka帯（26.5〜40GH
z）やＵ帯（40〜60GHz）で動作する半導体装置が出現
し、半導体装置に寄生するパラメータの制約がきびしく
なっている。特に、近年低雑音化のためゲート長の縮小
がはかられるようになって来ているが、ゲート長の縮小
は半面、ゲート抵抗の増加となり、低雑音化の障害とな
っている。In recent years, semiconductor devices have become more sophisticated, and Ka band (26.5-40GH
With the advent of semiconductor devices that operate in the z) and U-band (40 to 60 GHz), the restrictions on the parameters parasitic on the semiconductor devices are becoming severe. In particular, in recent years, the gate length can be reduced to reduce the noise, but the reduction in the gate length causes an increase in the gate resistance, which is an obstacle to the noise reduction.
以下、説明を簡単にするため半導体としては砒化ガリウ
ム（GaAs）、半導体装置としては、ショットキーゲート
構造のＭＥＳ・ＦＥＴを例にして具体的に説明する。Hereinafter, for the sake of simplicity, gallium arsenide (GaAs) is used as a semiconductor, and a MES-FET having a Schottky gate structure is used as a semiconductor device.
J.M.MoranとD.Maydanは１９７９年発行のジョーナル・
オブ・バキューム・サイエンス・アンド・テクノロジー
（Journal of Vacuum Science and Technology）の１６
２０頁に第２図（ａ）〜（ｃ）に示すように、ゲート寄
生抵抗を低減する工夫をしたGaAs・ＭＥＳ・ＦＥＴのゲ
ート部分の製法を示している。第２図（ａ）に示すよう
に、GaAs基板１１上に樹脂層１２を充分厚く塗布し、つ
いで塗布性SiO2中間層１３を設け、さらにその上にレジ
スト層１４を設ける。次に、第２図（ｂ）に示すよう
に、レジスト層１４を露光現象し、エッチングにより中
間層１３に所定のパターンを形成し、さらにエッチング
により、樹脂層１２を中間層１３のパターンより大きい
開口寸法を有するように除去した後、露呈したGaAs層１
１をエッチングし、前記GaAs基板１１の法線方向からＡ
層１５を蒸着する。次に、第２図（ｃ）に示すよう
に、樹脂層を除去すればゲート電極が形成できる。JM Moran and D. Maydan are Jonal
16 of the Journal of Vacuum Science and Technology
As shown in FIGS. 2 (a) to 2 (c), page 20 shows a method of manufacturing the gate portion of GaAs / MES / FET which is devised to reduce the gate parasitic resistance. As shown in FIG. 2 (a), a resin layer 12 is applied on the GaAs substrate 11 in a sufficiently thick thickness, then a coatable SiO 2 intermediate layer 13 is provided, and a resist layer 14 is further provided thereon. Next, as shown in FIG. 2B, the resist layer 14 is exposed to light and a predetermined pattern is formed on the intermediate layer 13 by etching, and the resin layer 12 is made larger than the pattern of the intermediate layer 13 by etching. Exposed GaAs layer 1 after removal to have opening dimensions
1 is etched and A is drawn from the normal direction of the GaAs substrate 11.
Layer 15 is deposited. Then, as shown in FIG. 2C, the gate electrode can be formed by removing the resin layer.
上述した従来技術では、ゲート長0.2μｍで高さ方向に
高く抵抗の小さいゲート形成が可能であるが、さらにゲ
ート長が0.1μｍ以下のものを形成しようとすると、ゲ
ート金属蒸着時にゲート金属が中間層開口部に付着し、
ゲート長を短くするに従って、ゲート抵抗を小さくする
ことができなくなる。In the above-mentioned conventional technique, it is possible to form a gate having a gate length of 0.2 μm and a high resistance in the height direction and a low resistance. Attached to the layer opening,
As the gate length is shortened, the gate resistance cannot be reduced.
本出願人はこれらの問題点を改善する方法を検討し、Γ
（ガンマ）形の断面のゲート電極を有するＭＥＳ・ＦＥ
Ｔを開発し特願昭６０−０６１３３１号として出願し
た。このゲート電極上部の突出は片側のみとすることが
出来るので、従来問題となっていたゲート寄生抵抗を小
さくすると共にゲート・ソース間フリンジング容量を低
減できる特徴がある。しかし従来の製造方法では片側の
みの突出のゲート電極の形成は困難でソース・ゲート間
の距離をより小さくすることが困難でありフリンジング
容量を大幅に減少させることが出来なかった。The Applicant has examined how to improve these problems,
MES / FE with (gamma) -shaped cross-section gate electrode
T was developed and filed as Japanese Patent Application No. 60-063311. Since the protrusion above the gate electrode can be formed on only one side, there is a feature that the gate parasitic resistance, which has been a problem in the past, can be reduced and the fringing capacitance between the gate and the source can be reduced. However, in the conventional manufacturing method, it is difficult to form the gate electrode protruding only on one side, and it is difficult to further reduce the distance between the source and the gate, so that the fringing capacitance cannot be significantly reduced.
本発明の目的は、このような従来技術の欠点を除去し、
上記従来技術の良い点を保持したままで、ゲート抵抗を
減少させ、ゲート・ソース間のフリンジング容量を減少
させ、なおかつ0.25μｍ以下の微細なゲート長をもつゲ
ート電極を形成し、高周波特性を向上させたところの化
合物半導体からなる半導体装置の製造方法を提供するこ
とにある。The object of the present invention is to eliminate such drawbacks of the prior art,
While maintaining the good points of the prior art, the gate resistance is reduced, the fringing capacitance between the gate and the source is reduced, and a gate electrode having a fine gate length of 0.25 μm or less is formed to improve the high frequency characteristics. An object of the present invention is to provide a method for manufacturing a semiconductor device made of an improved compound semiconductor.
本発明の半導体装置の製造方法は、半導体基板上に順次
有機又は無機絶縁層と、第１のレジスト層と、酸化シリ
コン又は窒化シリコン又は多結晶シリコン又はアルミニ
ウム等の金属の薄い中間層と、第２のレジスト層とを設
ける工程と、前記第２のレジスト層を露光・現像し開口
部を有するパターンを形成し、該パターンを用いてエッ
チングし前記中間層に所定のパターンを設け、さらにエ
ッチングして第１のレジスト層に開口し前記有機又は無
機絶縁層を露出させ、さらにエッチングして半導体基板
表面を露出させる工程と、該露出した半導体基板表面を
エッチング又は表面処理をする工程と、第３のレジスト
層を塗布し、第３及び第１のレジスト層を露光・現像し
パターンを形成している第１のレジスト層より上を片側
除去する工程と、上方より方向性のある被着方法によっ
て電極金属層を露出した前記半導体基板上、有機又は無
機絶縁層および中間層上に被着する工程と、不要な電極
金属層を除去し、次いで中間層と第１のレジスト層及び
有機又は無機の絶縁層を除去する工程とを含んで構成さ
れる。A method of manufacturing a semiconductor device according to the present invention comprises an organic or inorganic insulating layer, a first resist layer, a thin intermediate layer of a metal such as silicon oxide or silicon nitride, polycrystalline silicon, or aluminum, which is sequentially formed on a semiconductor substrate. A step of providing a second resist layer, and exposing and developing the second resist layer to form a pattern having openings, etching using the pattern to provide a predetermined pattern on the intermediate layer, and further etching. Opening the first resist layer to expose the organic or inorganic insulating layer, and further etching to expose the surface of the semiconductor substrate; a step of etching or surface treating the exposed surface of the semiconductor substrate; Coating the resist layer, and exposing and developing the third and first resist layers to remove one side above the first resist layer forming the pattern, On the semiconductor substrate where the electrode metal layer is exposed by a more directional deposition method, the step of depositing on the organic or inorganic insulating layer and the intermediate layer, and removing the unnecessary electrode metal layer and then the intermediate layer. And a step of removing the first resist layer and the organic or inorganic insulating layer.
本発明の半導体装置の製造方法は、多層レジスト構造を
用いて段差などによる前工程のゲート形成への影響を小
さくし、半導体基板表面のエッチングあるいは表面処理
領域と、半導体表面とゲート電極が接する寸法（ゲート
長）を決定し、レジスト層の露光現像による片側除去お
よび金属の方向性被着法により、Γ（ガンマ）形の断面
を有し、しかもその電極上部の突出が片側のみとするこ
とが可能であることに特徴がある。The semiconductor device manufacturing method of the present invention uses a multilayer resist structure to reduce the influence of a step or the like on the gate formation in the previous step, and the etching or surface treatment region of the semiconductor substrate surface and the size at which the semiconductor surface and the gate electrode are in contact with each other. By determining the (gate length) and removing the resist layer on one side by exposure and development and the metal directional deposition method, it is possible to have a Γ (gamma) -shaped cross section and to project only one side of the electrode above the electrode. It is characterized by being possible.
かくして本発明によれば、特に問題となるゲート寄生抵
抗と、ゲート・ソース間フリンジング容量を低減でき、
かつ、0.2μｍ以下のゲート長をもつ半導体装置を得る
ことができる。Thus, according to the present invention, the gate parasitic resistance and the gate-source fringing capacitance, which are particularly problematic, can be reduced,
Moreover, a semiconductor device having a gate length of 0.2 μm or less can be obtained.
次に、本発明の実施例について図面を参照して説明す
る。第１図（ａ）〜（ｆ）は本発明の一実施例の半導体
装置の製造方法を説明するために工程順に示した素子の
ゲート部分の断面図である。Next, embodiments of the present invention will be described with reference to the drawings. 1 (a) to 1 (f) are cross-sectional views of the gate portion of an element shown in the order of steps for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.
本実施例においては説明の都合上GaAs・ＭＥＳ・ＦＥＴ
について説明する。In the present embodiment, for convenience of explanation, GaAs / MES / FET
Will be described.
まず第１図（ａ）に示すように、半導体GaAs基板１の上
に厚さ１０００Åの樹脂層２（例えばホトレジストを塗
布し、２５０℃で窒素ガス中にて１時間ベークしたも
の）を設け、次に厚さ１μｍの第１のレジスト層３（例
えばＰＭＭＡ）を設け、次に厚さ１０００Å程度の塗布
性SiO2層４（例えばケイ素化合物をアルコール等の有機
溶剤に溶解したものを回転塗布し、ベークしたもの）を
設け中間層とし、さらに、その上にパターニングのため
の第２のレジスト層５（例えば、ＰＭＭＡ）を設ける。First, as shown in FIG. 1 (a), a resin layer 2 having a thickness of 1000Å (for example, photoresist coated and baked in nitrogen gas at 250 ° C. for 1 hour) is provided on a semiconductor GaAs substrate 1. Next, a first resist layer 3 (for example, PMMA) having a thickness of 1 μm is provided, and then a coatable SiO 2 layer 4 (for example, a silicon compound dissolved in an organic solvent such as alcohol) having a thickness of about 1000Å is spin-coated. , Baked) is provided as an intermediate layer, and a second resist layer 5 (for example, PMMA) for patterning is further provided thereon.
次いで、第１図（ｂ）に示すようにレジスト層５を露
光，現像処理して0.25μｍ幅の細長いパターンを形成
し、そのレジストパターンをマスクにして四弗化炭素
（CF4）ガスと水素（H2）ガスの混合ガスを用いた反応
性スパッタエッチングを行なうことにより、SiO2層４を
エッチングし、次いで酸素ガスを用いた反応性エッチン
グの手段を用いてレジスト層３及び樹脂層２をエッチン
グし、同時にレジスト層５をエッチング除去する。この
レジスト層３及び樹脂層２のエッチングで用いた酸素ガ
スによるドライエッチングでは、SiO2層４はほとんどエ
ッチングされない。Then, as shown in FIG. 1 (b), the resist layer 5 is exposed and developed to form an elongated pattern having a width of 0.25 μm, and the resist pattern is used as a mask to form carbon tetrafluoride (CF 4 ) gas and hydrogen. The SiO 2 layer 4 is etched by performing reactive sputter etching using a mixed gas of (H 2 ) gas, and then the resist layer 3 and the resin layer 2 are removed by means of reactive etching using oxygen gas. The resist layer 5 is etched and simultaneously removed. The SiO 2 layer 4 is hardly etched by the dry etching using the oxygen gas used for etching the resist layer 3 and the resin layer 2.
次いで、第１図（ｃ）に示すように、中間層４上全面に
第３のレジスト６（例えばシップレイ社製ホトレジスト
ＡＺ−２４００）を塗布し、開口部を端に含まないよう
に第３のレジスト層６を露光現像し、中間層４を露呈し
CF4ガスとH2ガスの混合ガスによる反応性ガスあるいは
プラズマエッチングにより前記中間層４を除去し、さら
に現像することによりレジスト層３が除去され、結果と
して片側の、この場合、右側の第１のレジスト層３中間
層４が除去される。ついで、先に露出した半導体表面を
ウェットエッチングあるいはドライエッチングで溝を形
成するか、又は表面処理を行なう。Then, as shown in FIG. 1C, a third resist 6 (for example, photoresist AZ-2400 manufactured by Shipley Co., Ltd.) is applied on the entire surface of the intermediate layer 4, and the third resist 6 is applied so that the opening is not included in the end. The resist layer 6 is exposed and developed to expose the intermediate layer 4.
The intermediate layer 4 is removed by reactive gas or plasma etching with a mixed gas of CF 4 gas and H 2 gas, and the resist layer 3 is removed by further development, and as a result, the first layer on one side, in this case, on the right side, is removed. The resist layer 3 and the intermediate layer 4 are removed. Next, a groove is formed on the previously exposed semiconductor surface by wet etching or dry etching, or surface treatment is performed.
次いで、第１図（ｄ）に示すように上面からＡ層７を
垂直方向から全面被着（厚さは任意だが第１のレジスト
層３より薄くする。この場合、１μｍ以下）する。Then, as shown in FIG. 1 (d), the A layer 7 is entirely deposited from the upper surface in the vertical direction (though the thickness is arbitrary but thinner than the first resist layer 3. In this case, 1 μm or less).
次いで、第１図（ｅ）に示すように、全面に第４レジス
ト層８（例えばホトレジストシップレイ社製ＡＺ−１４
００−１７）を塗布し、露光現像し、ゲート部以外のＡ
層７を露出させた後、６０℃のリン酸によりＡ層７
をエッチング除去する。Then, as shown in FIG. 1 (e), a fourth resist layer 8 (for example, AZ-14 manufactured by Photoresist Shipley Co., Ltd.) is formed on the entire surface.
00-17), exposed and developed, and A
After exposing layer 7, A layer 7 was exposed to phosphoric acid at 60 ° C.
Are removed by etching.
次いで、第１図（ｆ）に示すように、O2ガスにより第３
のレジスト層６を、そしてCF4とH2の混合ガスにより中
間層４を除去し、ついでO2ガスによる反応性エッチング
及びプラズマエッチングにより第１及び第３のレジスト
層３，６と樹脂層２が除去され、同時に不要部のゲート
金属Ａ層７も除去されることにより、図示のようなGa
As・ＭＥＳ・ＦＥＴのゲート部断面構造が得られる。Next, as shown in FIG. 1 (f), the third by O 2 gas
Of the resist layer 6 and the intermediate layer 4 with a mixed gas of CF 4 and H 2 and then the first and third resist layers 3 and 6 and the resin layer 2 by reactive etching and plasma etching with O 2 gas. Is removed, and at the same time, the unnecessary portion of the gate metal A layer 7 is removed.
A gate section cross-sectional structure of As.MES.FET can be obtained.
以上の工程により得られた本実施例のＭＥＳ・ＦＥＴは
GaAs基板１の上にゲート電極７が断面としてΓ（ガン
マ）形をし、そのゲート電極の突出が片端のみの構造を
有している。なおゲート電極のＡ層とGaAs基板１が接
している部分がショットキー接合をしており、ゲート電
極の左側にソース電極が形成されることにより目的を達
成できる。なお上記実施例の説明の中で、特定の物質、
厚さを述べた。これは説明の便宜のためであり、たとえ
ばゲート金属はＡ層７でなくとも半導体基板と良好な
ショットキー特性をもつ金属あるいは多層構造が使用可
能である。また第１のレジスト層３の厚さもゲート金属
となるＡ層７より厚く制御されたものであればよい。
又、中間層４も塗布性SiO2でなくとも、薄い金属膜であ
ってもよく、このときは、樹脂層２に樹脂の代わりに塗
布性SiO2を使用することもできる。The MES • FET of this example obtained by the above steps is
The gate electrode 7 has a Γ (gamma) shape in cross section on the GaAs substrate 1, and the projection of the gate electrode has only one end. The object can be achieved by forming a source electrode on the left side of the gate electrode because the Schottky junction is formed in the portion where the A layer of the gate electrode is in contact with the GaAs substrate 1. In the description of the above examples, specific substances,
Mentioned the thickness. This is for convenience of explanation. For example, the gate metal may be a metal having a good Schottky characteristic with the semiconductor substrate or a multi-layer structure, instead of the A layer 7. Further, the thickness of the first resist layer 3 may be controlled to be thicker than the A layer 7 serving as the gate metal.
Further, even intermediate layer 4 is also not coatability SiO 2, may be a thin metal film, this time, it is also possible to use a coating of SiO 2 in the resin layer 2 in place of the resin.
又、Ａ層７を蒸着する際に斜目蒸着法を用いれば（第
２図ｄ）、ゲート長をさらに小さくすることも可能であ
る。Further, if the oblique deposition method is used when depositing the A layer 7 (FIG. 2D), the gate length can be further reduced.
以上、詳細説明したとおり、本発明によれば上記構成に
より、短いゲート長（0.2μｍ以下）でもΓ型となって
いるためゲート抵抗の増大を抑止することができるばか
りでなく、ゲート・ソース電極間のフリンジング容量を
減少させることができ、結果として高周波特性として重
要な利得，低雑音特性，高出力特性にすぐれた化合物半
導体からなる半導体装置を製造することができる。As described above in detail, according to the present invention, since the structure is Γ type even with a short gate length (0.2 μm or less), it is possible to suppress not only an increase in gate resistance but also the gate / source electrode. It is possible to reduce the fringing capacitance between them, and as a result, it is possible to manufacture a semiconductor device made of a compound semiconductor having excellent gain, low noise characteristics, and high output characteristics which are important as high frequency characteristics.
第１図（ａ）〜（ｆ）は、本発明の一実施例を説明する
ために工程順に示した素子のゲート部分の縦断面図、第
２図（ａ）〜（ｃ）は従来のGaAs・ＭＥＳ・ＦＥＴの製
造方法を説明するために工程順に示したゲート部分の縦
断面図である。 １，１１……GaAs基板、２，１２……樹脂層、３……第
１レジスト層、４，１３……中間層（SiO2）、５……第
２レジスト層、６……第３のレジスト層、７，１５……
Ａ層、８……第４のレジスト層、１４……レジスト
層。1 (a) to 1 (f) are vertical sectional views of the gate portion of the device shown in order of steps for explaining one embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are conventional GaAs. FIG. 6B is a vertical cross-sectional view of the gate portion shown in the order of steps for explaining the method for manufacturing the MES • FET. 1, 11 ... GaAs substrate, 2, 12 ... Resin layer, 3 ... First resist layer, 4, 13 ... Intermediate layer (SiO 2 ), 5 ... Second resist layer, 6 ... Third Resist layer, 7, 15 ...
A layer, 8 ... Fourth resist layer, 14 ... Resist layer.
Claims (1)
と、第１のレジスト層と、酸化シリコン又は窒化シリコ
ン又は多結晶シリコン又はアルミニウム等の金属の薄い
中間層と、第２のレジスト層とを設ける工程と、前記第
２のレジスト層を露光・現像し開口部を有するパターン
を形成し、該パターンを用いてエッチングし前記中間層
に所定のパターンを設け、さらにエッチングして第１の
レジスト層に開口し前記有機又は無機絶縁層を露出さ
せ、さらにエッチングして半導体基板表面を露出させる
工程と、該露出した半導体基板表面をエッチング又は表
面処理をする工程と、第３のレジスト層を塗布し、第３
及び第１のレジスト層を露光・現像しパターンを形成し
ている第１のレジスト層より上を片側除去する工程と、
上方より方向性のある被着方法によって電極金属層を露
出した前記半導体基板上、有機又は無機絶縁層および中
間層上に被着する工程と、不用な電極金属層を除去し、
次いで中間層と第１のレジスト層及び有機又は無機の絶
縁層を除去する工程とを含むことを特徴とする半導体装
置の製造方法。1. An organic or inorganic insulating layer, a first resist layer, a thin intermediate layer of a metal such as silicon oxide or silicon nitride, polycrystalline silicon, or aluminum on a semiconductor substrate, and a second resist layer. And forming a pattern having an opening by exposing and developing the second resist layer, etching using the pattern to provide a predetermined pattern on the intermediate layer, and further etching to form the first resist. A step of opening the layer to expose the organic or inorganic insulating layer, and further etching to expose the surface of the semiconductor substrate; a step of etching or surface treating the exposed surface of the semiconductor substrate; and applying a third resist layer. And then the third
And a step of exposing and developing the first resist layer to remove one side above the first resist layer forming the pattern,
On the semiconductor substrate exposing the electrode metal layer by a directional deposition method from above, a step of depositing on the organic or inorganic insulating layer and the intermediate layer, and removing the unnecessary electrode metal layer,
Next, a method of manufacturing a semiconductor device, including a step of removing the intermediate layer, the first resist layer, and the organic or inorganic insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14338686A JPH0638431B2 (en) | 1986-06-18 | 1986-06-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14338686A JPH0638431B2 (en) | 1986-06-18 | 1986-06-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62299033A JPS62299033A (en) | 1987-12-26 |
| JPH0638431B2 true JPH0638431B2 (en) | 1994-05-18 |
Family
ID=15337564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14338686A Expired - Lifetime JPH0638431B2 (en) | 1986-06-18 | 1986-06-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0638431B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2667250B2 (en) * | 1989-06-15 | 1997-10-27 | 松下電子工業株式会社 | Method for manufacturing semiconductor device |
| US11119405B2 (en) * | 2018-10-12 | 2021-09-14 | Applied Materials, Inc. | Techniques for forming angled structures |
-
1986
- 1986-06-18 JP JP14338686A patent/JPH0638431B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62299033A (en) | 1987-12-26 |
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