JPH0638307B2 - RF signal processing circuit - Google Patents

Description

The present invention relates to an RF signal processing circuit suitable for use in an optical disk device.

[Outline of the Invention] In the present invention, the input of the edge detection circuit is clamped to a predetermined potential during at least a part of the sync signal.

[Conventional technology]

FIG. 3 shows a servo byte pattern of a sample servo in the optical disk device. Each sector of the optical disc is composed of 43 servo blocks, and one servo block is composed of 2 bytes of servo bytes and 16 bytes of data bytes following the servo bytes. The servo bytes consist of two wobbled pits and one clock pit, and the wobbled pits are arranged on the left and right of the track center. When the pickup (light spot for information detection) traces the track center, the amount of decrease in the amount of light in the left and right wobbled pits becomes equal, and when the trace position shifts to the left and right, two amounts of light fall depending on the direction and amount of the shift. The amount of decrease in the amount of light in the wobbled pit changes. Therefore, the difference in the reduction amount at the two positions (the difference in the level of the RF signal)
A tracking error signal is generated from the tracking error signal, and the tracking error signal is held during the subsequent data byte.

Also, the two wobbled pits are changed into a longer interval and a shorter interval every 16 tracks, and by detecting the change in this interval, it is possible to accurately count the number of tracks (16-track counting) even during high-speed search. You can do it.

Further, the distance D between the wobbled pit and the clock pit located later is set to a special length that does not appear in the data byte. Therefore, this distance D can be detected as a synchronization signal. Various timing signals are generated based on the detected synchronization signal. The clock is generated corresponding to the detection signal of the clock pit. The mirror surface portion of the distance D is used as a focus area, in which a focus error signal is detected and held in the section of the following data byte.

In the data byte section following the servo byte section, data is recorded by pits or phase changes. When data is recorded depending on the presence or absence of pits, the level of the RF signal decreases in the portion where pits exist, as described above. On the other hand, in the case of a phase change, the level of the RF signal may increase in a portion where data is recorded (corresponding to a portion having a pit) depending on the recording material. When any type of disc can be recorded or reproduced, the potential of the servo bite portion is not fixed, so that the RF signal is amplified by the DC amplifier.

[Problems to be solved by the invention]

However, when a wide band DC amplifier is used as described above, it is vulnerable to noise, and drift changes due to temperature are likely to occur, and the cost is increased.

Therefore, the present invention makes it possible to process an RF signal by an AC amplifier.

[Means for solving problems]

According to the present invention, in an RF signal processing circuit, an amplification circuit for AC-amplifying an input RF signal, an edge detection circuit for detecting an edge from the output of the amplification circuit, and a synchronization signal corresponding to the output of the edge detection circuit are detected. A synchronization signal detection circuit, a generation circuit that generates a predetermined timing signal corresponding to the output of the synchronization signal detection circuit, and at least a part of the synchronization signal corresponding to the output of the generation circuit, and an input of the edge detection circuit. And a clamp circuit that clamps to a predetermined potential.

[Action]

The amplifier circuit AC-amplifies the input RF signal. The output of the amplifier circuit is input to the edge detection circuit. The edge detection circuit detects the edge of the input RF signal. The sync signal detection circuit detects the sync signal from the edge information input from the edge detection circuit. The generation circuit generates a predetermined timing signal corresponding to the detection signal input from the synchronization signal detection circuit. This timing signal is input to the clamp circuit. The clamp circuit clamps the input of the edge detection circuit to a predetermined potential during at least a part of the sync signal.

〔Example〕

FIG. 1 is a block diagram of an RF signal processing circuit of the present invention. The photodetector 1 irradiates the optical disc and receives the reflected light. The RF signal output from the photodetector 1 is input to the amplifier circuit 3 via the capacitor 2 and is AC-amplified.
The RF signal output from the amplifier circuit 3 is input to the edge detection circuit 6 via the capacitors 4 and 5. This RF signal is
The level of the wobbled pit and the clock pit in the servo byte section shown in FIG. 2 (a) decreases as shown in FIG. 2 (b). The edge detection circuit 6 differentiates the input RF signal and detects the zero cross of the differential output to detect the center position (edge) of the pit. This detection signal is input to the synchronization signal detection circuit 7. The sync signal detection circuit 7 detects this section (sync signal) by paying attention to the fact that the length of the second wobbled pit and the clock pit is the longest section (sync signal) that does not appear in the data byte section. . The detected synchronization signal is input to the generation circuit 8. The generation circuit 8 generates various timing signals with the detection signal of the input synchronization signal as a reference.

The generation circuit 8 outputs a timing signal (FIG. 2 (c)) corresponding to at least a part of the sync signal to the switches 9 and 22.

When this timing signal is input, switch 9
Is turned on. As a result, the input of the edge detection circuit 6 is clamped to the predetermined potential V ₀ output by the reference voltage generation circuit 10. That is, the switch 9 and the reference voltage generation circuit 10
Constitutes a clamp circuit.

In this way, R is set for each section of each synchronization signal of each servo block.
Since the F signal is clamped to the predetermined potential V ₀ , the edge detection circuit 6 can accurately detect the edge (thus the synchronization signal detection circuit 7 can accurately detect the synchronization signal).

The switch 22 is also turned on when the timing signal output from the generation circuit 8 is supplied. As a result, the input of the A / D conversion circuit 26 is clamped to the predetermined reference potential V ₁ or V ₂ output by the reference voltage generation circuit 24 or 25 in at least a part of the sync signal. The control circuit 27 including a microcomputer or the like identifies the type of disc from the identification code read by the reading circuit 28. The switch 2 is used to select the reference potential V ₁ when the disc in which the level of the RF signal is lowered in the data recording portion and the reference potential V ₂ when the disc is increased in the data recording portion.
Switch 3 The reference potential of the A / D conversion circuit 26 is V ₃ , and the level change amount of the RF signal in the data byte section is A
When _one or _{A 2,} reference potential _{V 1 was, V 1 = V 3 + A} 1/2 reference potential _{V 2} is set to _{V 2 = V 3 -A 2/} 2. As a result, the center of the amount of change A ₁ , A _{2 in} the data byte section is the reference potential V in any disk.
Set to ₃ . The A / D conversion circuit 26 uses the reference potential V
_The input RF signal is A / D converted with reference to ₃ . A / D
The data signal converted into the digital signal by the conversion circuit 26 is input to the reading circuit 28 and read.

It is possible to omit the clamp circuit including the switches 22 and 23 and the reference voltage generation circuits 24 and 25. However, in that case, it is necessary to set the dynamic range of the A / D conversion circuit 26 wider than in the case where it is not omitted. In other words, by providing this clamp circuit, the dynamic range of the A / D conversion circuit 26 can be narrowed.

The time constant of the clamp circuit and the amplifier circuit 3 in the low frequency range is set to a value sufficiently larger than the repetition cycle of the servo byte.
As a result, the level of the RF signal can quickly respond to the operation of the switch 9 or 22.

〔effect〕

As described above, according to the present invention, in the RF signal processing circuit, an amplification circuit for AC-amplifying an input RF signal, an edge detection circuit for detecting an edge from the output of the amplification circuit, and a synchronization signal corresponding to the output of the edge detection circuit. Detecting circuit, a generating circuit for generating a predetermined timing signal corresponding to the output of the synchronizing signal detecting circuit, and an edge detection for at least a part of the synchronizing signal corresponding to the output of the generating circuit. Since it is provided with a clamp circuit for clamping the input of the circuit to a predetermined potential, it becomes possible to use an AC amplifier to amplify the RF signal. As a result, it is more resistant to noise and less drift. Also, the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an RF signal processing circuit according to the present invention, and FIG.
The figure is its timing chart, and FIG. 3 is an explanatory view of the servo byte pattern. 1 ... Photodetector 2 ... Capacitor 3 ... Amplifier circuit 4, 5 ... Capacitor 6 ... Edge detection circuit 7 ... Synchronous signal detection circuit 8 ... Generation circuit 9 ... Switch 10 ... Reference voltage generation circuit 21 ... Capacitor 22, 23 ... Switch 24, 25 ... Reference voltage generation circuit 26 ... A / D conversion circuit 27 ... Control circuit 28 ... Reading circuit

Claims (1)

[Claims] 1. An amplifier circuit for AC-amplifying an input RF signal, an edge detection circuit for detecting an edge from the output of the amplifier circuit, and a synchronization signal for detecting a synchronization signal corresponding to the output of the edge detection circuit. A detection circuit, a generation circuit that generates a predetermined timing signal in response to the output of the synchronization signal detection circuit, and at least a part of the synchronization signal corresponding to the output of the generation circuit, the edge detection circuit And a clamp circuit for clamping the input of the input signal to a predetermined potential.