JPH06350460A - Error correction circuit for compression code - Google Patents

Abstract

PURPOSE:To provide an error correction circuit for compression code which prevents the demodulation infeasibility of a compressed code from spreading over a hierarchy even when the incorrectable state of an error correction code due to an error occurs by taking the synchronism of the compressed code with the error correction code when the compressed code is transmitted. CONSTITUTION:This circuit is provided with a synchronizing signal detection circuit 3 which inputs the compression code from a compressed code generation circuit 1 via a FIFO 2 and detects the synchronizing signal of the compressed code, a counter circuit 4 which counts the code quantity of the compressed code, a data stuffing circuit 5 which compares the code quantity at every hierarchy with that of one code word of the error correction code based on the synchronizing signal and the code quantity and inserts dummy data so as to set the code quantity at every hierarchy to a value of integer times the code quantity of one code word of the error correction code, and an error correction code generating circuit 6 which generates parity sequentially on a code inputted sequentially via the data stuffing circuit 5 outputs by generating the error correction code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compression code error correction circuit for obtaining synchronization between an error correction code and a compression code which are configured to cope with a transmission error when transmitting a compression code.

[0002]

2. Description of the Related Art Conventionally, there is a VLC (Variable Length Coding) code as an encoding method used for a compression code. The characteristic of this encoding method is that the code length is determined from the probability of occurrence of an event, so the entropy of the code is high and it is optimal for compressed signals. But V
The code by LC (hereinafter referred to as VLC code) has no correlation between the actual information amount and the encoded code amount, for example, in terms of an image, the number of pixels per frame and the code amount. For this reason, when an error correction code is formed for a compressed code, it is not possible to synchronize the compressed code and the error correction code as a code, and when actually performing error correction. Inconvenience occurs.

The formats of such a compression code and its error correction code will be described. FIG. 3 shows the format of the above-mentioned compression code. The compression code is MPEG (M
otion Picture Expert Group) standard format,
The image format is shown. The compression code is GOP (G
Each layer of roup of picture) picture slice is composed of a header (synchronization signal) and the following VLC code, and the data length of each layer is not constant.

The information of the GOP layer as the uppermost layer is inserted according to the request of the application as needed, and as shown in FIG. 3A, the GOP header, the parameter data and the data of the picture layer. Is provided. Each picture P ₀ , P ₁ , P ₂ , ..., P _n
Consists of a header and its parameter data,
There is a reference number that indicates the playback order of pictures in the picture parameter following the picture header,
This GOP layer is grouped into 1 GOP based on the number determined by the application request, and this 1 GOP is repeated.

The picture hierarchy is shown in FIG.
As shown in (b), each screen has headers (01), (02), ..., (0F) provided along the vertical direction.
15 slices of 1 are configured as one picture, the parameter data of each header is provided along the scanning direction, and the slice header has a number indicating a continuous order. Furthermore, the slice hierarchy of the lowest layer is as shown in FIG.
As shown in (c), 1 line is 8 lines on the screen.
It is configured in a unit called a slice as a group, and includes a 32-bit header and a VLC code.

On the other hand, the error correction code has the format shown in FIG. The error correction code is composed of data to be transmitted and a parity generated from the data, and the data length and the length of the parity in the error correction code, that is, the code length T is constant, and it is difficult to make it variable. For example, in the above-mentioned MPEG standard, a compression code in a slice hierarchy format, that is, each slice (N ₀ ) consisting of a header and a VLC code,
The code lengths T ₁ , T ₂ , ... Of (N ₁ ), ...
While it is different for each slice as shown in (a), the code length T of the error correction code is constant as shown in FIG. 2 (b).

[0007]

Therefore, the above-mentioned variable
Error correction code of fixed length code to compressed code of long code
When configured, it becomes as shown in FIGS. 2 (c) and 2 (e). Figure
2 (c), the slice (N₀) Header H₀ of
Align the position with the beginning of the error correction code
Appropriate data length (predetermined code length T-parity length)
When the error correction code is constructed with, as shown in FIG.
And each header (sync signal) H₀, H₁...
Error correction code ERR (N₀), ERR (N₁), ...
Does not come to the beginning of. Therefore, if the error correction code ER
R (N 1) became uncorrectable on the decoder side and all data
If the error is determined to be an error, the failure due to the error is
Su (N₀) And slice (N₁). For this reason,
Two slices due to uncorrectable error correction code
Data is lost.

As shown in FIG. 2 (e), if the parity of the error correction code is located at the end so that the code length of the slice (N ₀ ) matches the code length of the error correction code. Since the compression code has a different code length for each slice, the formats of the compression code after the slice (N ₁ ) and the error correction code do not match, and the code length cannot be synchronized. That is, for example, the header (synchronization signal) H ₂ does not come to the beginning of the error correction code ERR (N ₂ ), and therefore, as in the case of FIG.
If the error correction code ERR (N ₂ ) becomes uncorrectable on the decoder side and all the data is judged to be in error, the fault due to the error spreads to the slice (N ₁ ) and the slice (N ₂ ). The data of two slices is lost due to the uncorrectability of one error correction code.

The above description has been made in consideration of the slice hierarchy. However, when the same occurs in the error correction code formed at the boundary between the slice hierarchy, the picture hierarchy and the GOP hierarchy, the error failure exceeds the hierarchy. Will be expanded.

The present invention has been made in view of the above-mentioned points, and synchronizes the compression code and the error correction code, and even if the error correction code is uncorrectable due to an error, the decoding of the compression code becomes impossible. It is an object of the present invention to obtain an error correction circuit for a compression code that can prevent it from spreading beyond.

[0011]

A compression code error correction circuit according to the present invention includes a synchronization signal detection circuit for detecting a synchronization signal of a compression code, a counter circuit for counting the code amount of the compression code, and the synchronization circuit. A data stuffing circuit that inserts a predetermined amount of dummy data in the compressed code according to the layer based on the synchronization signal output from the signal detection circuit and the code amount output from the counter circuit,
An error correction code generation circuit that sequentially generates parity for the code output from the data stuffing circuit to generate and output an error correction code.

[0012]

In the compressed code error correction circuit according to the present invention, the data stuffing circuit is used to count the sync signal output from the sync signal detection circuit for detecting the sync signal of the compressed code and the counter for counting the code amount of the compressed code. Based on the code amount output from the circuit, a predetermined amount of dummy data corresponding to the layer is inserted into the compression code, and the error correction code generation circuit sequentially generates parity for the code output from the data stuffing circuit. By generating and outputting the error correction code, the code amount of each layer of the compression code and the code amount of the error correction code are synchronized, and the synchronization signal of the compression code is always error corrected. It is located at the beginning of the code.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a compression code error correction circuit according to the present embodiment. The illustrated configuration is a circuit that follows the circuit that encodes a compressed signal, and the error correction circuit of the illustrated configuration is followed by a signal transmission system or an information recording system. The input compression code is assumed to be standardized as an MPEG format.
It is designed to be applied to a system using codes.

In FIG. 1, a compression code is generated by a compression code generation circuit 1 as a preceding stage of the constituent parts of the present invention. That is, the portion surrounded by the alternate long and short dash line in FIG. 1 corresponds to the error correction circuit. FIFO (first-in first-out)
Reference numeral 2 sequentially outputs the compression code input from the compression code generation circuit 1 in the order of storage. The sync signal detection circuit 3 is a FIFO
The sync signal of the compression code input via 2 is detected.
The counter circuit 4 similarly counts the code amount of the compressed code input via the FIFO 2, the compressed signal is managed by the synchronization signal detection circuit 3 for each layer, and the counter circuit 4 detects the code amount for each layer. To be done.

The data stuffing circuit 5 is a compression code based on the sync signal output from the sync signal detection circuit 3 and the code amount output from the counter circuit 4, and a predetermined amount of dummy data corresponding to the hierarchy. By comparing the detected code amount of each layer with the code amount of one code word of the error correction code that is given in advance, and determines the code amount of each layer by the code of one code word of the error correction code. Insert the necessary number of dummy data that does not pose a problem in decoding considering the compression format so that it becomes an integer multiple of the amount.

Further, the error correction code generation circuit 6 sequentially generates parity from the head for the compression code sequentially input through the data stuffing circuit 5 to generate and output the error correction code. The error correction code output from the error correction code generation circuit 6 and the code amount of each layer of the compression code are synchronized as a code for inserting dummy data. Therefore, the synchronization signal of the compression code is generated. Will always be located at the beginning of the error correction code.

The operation according to the configuration of FIG. 1 will be described in further detail. The sync signal detection circuit 3 detects a sync signal which divides the signal for each layer from the compressed signal input via the FIFO 2. This synchronization signal is a signal that can be detected without actually decoding the VLC code. On the other hand, counter circuit 4
Is reset for each layer based on the synchronization signal detected by the synchronization signal detection circuit 3 in the previous stage, and detects the code amount of each layer.

In the data stuffing circuit 5 to which the sync signal from the sync signal detection circuit 3 and the code amount from the counter circuit 4 are input, the detected code amount is compared with the code amount of one code word of the error correction code. Then, dummy data is inserted so that the code amount of each layer is an integral multiple of the code amount of the error correction code. This dummy data is MPEG so that it will not affect the VLC decoder during decoding.
Insert data based on the format standard.

In the error correction code generation circuit 6, the compression codes sequentially input via the data stuffing circuit 5 are sequentially generated from the beginning to generate and output an error correction code. Between the error correction code output from the error correction code generation circuit 6 and the code amount of each layer of the compression code, synchronization is taken as a code because dummy data is inserted, and the synchronization signal of the compression code always has an error. It comes to be located at the beginning of the correction code.Therefore, the decoder of the compression code performs error correction on the decoder side and extracts the dummy data from the data from which the parity is deleted, even if the dummy data is not extracted. The included compression code can be decoded.

Now, it is assumed that the code amount of each layer of the compression code is not constant. For example, as shown in FIG. 2A, it is assumed that the code lengths T ₀ , T ₁ , T _2, ... Of the slice hierarchy are different for each slice. In this state, as shown in FIG.
As shown in (d), slices (N ₁ ), (N ₂ ),
The headers H ₁ , H ₂ , and H ₃ of (N ₃ ) do not always come to the head position of the error correction code, and the code cannot be synchronized with the error correction code.

However, in the present embodiment, the "quantity" of the compressed signal based on the synchronization signal (header) based on the information from the synchronization signal detection circuit 3 and the output from the counter circuit 4 give the code amount of each layer. Since it has been detected, the data stuffing circuit 5 stuffs the dummy data for each layer so that the code amount of the compressed signal of each layer becomes an integral multiple of the code amount of the error correction code.

That is, regarding the compression code of the slice hierarchy, as shown in FIG. 2D, which is shown in comparison with FIG. 2C in which stuffing (insertion) is not performed, the error correction code E
At the positions of RR (N ₁ ) and ERR (N ₆ ), the code amounts of the slice (N ₀ ) and the slice (N ₂ ) are set to integer multiples of the code amount (code length T) of the error correction code, respectively. By stuffing the dummy data of S ₀ and S ₂ bytes, the headers H ₀ , H ₁ , H ₂ and H ₃ of the compression code always come to the head position of the error correction code, and the compression code and the error correction code The code can be synchronized with and.

Here, the amount of data to be stuffed is
It is obtained by the formula shown below. When the code length (the number of bytes) of the slice (N) is n and the code length of the error correction code is e, the data length S of the dummy data to be inserted is S = e- (n mod e) if (n mod e) then S = 0 The arithmetic expression of (n mod e) is the remainder obtained by dividing n by e. When there is no remainder, it means that the data length S is 0. Can be obtained with.

In this way, by stuffing the dummy data of the amount indicated by S, the compression code and the error correction code can be synchronized with each other, whereby a certain error correction code becomes uncorrectable. Also, although the compression code including it includes an error, it is possible to prevent the error from spreading beyond the hierarchy of the compression code. For example,
Even if ERR (N ₁ ) becomes uncorrectable due to an error, an error occurs only in the data of the slice (N ₀ ) and does not extend to the slice (N ₁ ) as in the conventional example.

Therefore, according to the above embodiment, between the code amount of each layer of the compression code and the code amount of the error correction code,
Since dummy data is inserted, synchronization can be achieved as a code, and the synchronization signal of the compression code is always located at the beginning of the error correction code, so a data error occurs in the error correction code for the compression code. However, the error does not spread beyond the compression code hierarchy. The error correction code generation according to the embodiment is not limited to the MPEG standard format, and can of course be widely applied to systems having a synchronization signal and having different data lengths.

[0026]

As described above, according to the present invention, an error correction code is generated by inserting a predetermined amount of dummy data according to the hierarchy into the compression code based on the synchronization signal of the compression code and the code amount. As a result, the synchronization signal of the compression code can be positioned at the head of the error correction code, and the code amount of each layer of the compression code and the code amount of the error correction code can be synchronized as a code. Even if a data error occurs, there is an effect that the error does not spread beyond the hierarchy of the compression code.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an error correction circuit for a compression code according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of formats of a compression code and an error correction code and an error correction code when the compression code is generated.

FIG. 3 is a format diagram of an image compression code according to the MPEG standard.

[Explanation of symbols]

 3 sync signal detection circuit 4 counter circuit 5 data stuffing circuit 6 error correction code generation circuit

Claims (1)

[Claims] 1. A sync signal detection circuit for detecting a sync signal of a compressed code, a counter circuit for counting the code amount of the compressed code, a sync signal output from the sync signal detection circuit, and an output from the counter circuit. A data stuffing circuit that inserts a predetermined amount of dummy data into the compressed code according to the layer based on the code amount, and an error correction code by sequentially generating parity for the code output from the data stuffing circuit. And an error correction code generation circuit for outputting the compressed error code.