JPH06349814A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] In a semiconductor integrated circuit device using a polyimide resin as a material for a surface protective film and an interlayer insulating film,
Even when the sealing resin having high adhesion to the semiconductor chip is used, the phenomenon of peeling of the insulating film in the wiring layer is suppressed. [Structure] Package body 2 for encapsulating a semiconductor chip 3
Between the surface protection film 3f made of polyimide resin and
A stress relaxation film 3g for relaxing stress applied to the layer in which the first layer wiring 3c and the second layer wiring 3e are formed is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technique, and more particularly to a technique effectively applied to a semiconductor integrated circuit device using a polyimide resin for a surface protective film and an interlayer insulating film.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device having a multilayer wiring structure, a polyimide resin may be used as a surface protective film or an interlayer insulating film.

Generally, this is because the polyimide resin is
Compared with inorganic insulating films such as PSG (Phospho Silicate Glass), etc., it has excellent temperature cycle characteristics.
This is because it has excellent properties such as suppressing the occurrence of disconnection defects in the through holes.

The structure of the conventional semiconductor integrated circuit device in this case is the same as that of the case where an inorganic insulating film is used. That is, it is as follows.

Wiring is formed on the inorganic insulating film deposited on the semiconductor substrate constituting the semiconductor chip, and an interlayer insulating film made of a polyimide resin is formed so as to cover the wiring. Has been deposited. Wiring is formed on the interlayer insulating film, and a surface protective film made of a polyimide resin is deposited so as to cover the wiring. In this case, the interlayer insulating film and the surface protective film are made of polyimide resin having the same molecular structure.
The surface protective film is in close contact with a sealing resin for sealing the semiconductor chip.

Regarding a semiconductor integrated circuit device using a polyimide resin as a material for the surface protective film and the interlayer insulating film, for example, Ohmsha Co., Ltd., June 20, 1989, "Introduction to Ultrafine Machining" P139-P141 There is a description in.

[0007]

However, the present inventor has found that the above-mentioned conventional technique has the following problems.

That is, in the reflow mounting process for mounting the semiconductor integrated circuit device on the mounting substrate, thermal stress applied to the semiconductor chip from the package body causes peeling in a layer in which wiring is formed in the semiconductor chip. As a result of water, ions, and the like entering through the peeled portion contaminating the wiring and the element, there is a problem that the reliability of the semiconductor integrated circuit device is deteriorated, such as wiring corrosion and element failure.

Such a peeling phenomenon is mainly caused by the fact that the adhesive strength between the sealing resin and the surface protective film is stronger than the adhesive strength between the surface protective film, the interlayer insulating film and the wiring. is there.

[0010] Therefore, such a problem becomes a remarkable problem especially as the package becomes smaller and thinner. In the case of small and thin packages, from the viewpoint of preventing peeling between the encapsulating resin and the semiconductor chip, which is the cause of package cracks during reflow mounting, etc., a material with high adhesion to the semiconductor chip as the encapsulating resin material. This is because

The present invention has been made in view of the above problems, and an object thereof is to adhere to a semiconductor chip in a semiconductor integrated circuit device using a polyimide resin as a material for a surface protective film and an interlayer insulating film. It is an object of the present invention to provide a technique capable of suppressing a peeling phenomenon in a layer in which a wiring of a semiconductor chip is formed, even when a sealing resin having high properties is used.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, a first aspect of the present invention is a semiconductor integrated circuit device having a multilayer wiring structure in which a semiconductor chip has an insulating film between wiring layers made of a polyimide resin and an insulating film for surface protection, and the semiconductor chip is sealed. A semiconductor integrated circuit device structure is provided in which a stress relaxation film for relaxing stress applied to a predetermined insulating film of the semiconductor chip is provided between a sealing resin to be stopped and the insulating film for surface protection. .

A second aspect of the present invention is a semiconductor integrated circuit device having a multilayer wiring structure in which a semiconductor chip has an insulating film between wiring layers made of a polyimide resin and an insulating film for surface protection, and is formed on the semiconductor chip. The structure of the semiconductor integrated circuit device is such that the surface of the wiring is curated.

[0016]

According to the above-mentioned first invention, since the stress applied between the predetermined insulating films of the semiconductor chip can be relieved during the reflow mounting process of the semiconductor integrated circuit device, the sealing with high adhesiveness to the semiconductor chip is achieved. Even when the stopping resin is used, it is possible to suppress the peeling phenomenon between the wiring and the insulating film in contact therewith.

According to the above-mentioned second invention, since the adhesive force between the wiring of the semiconductor chip and the insulating film in contact therewith can be improved, a sealing resin having high adhesion to the semiconductor chip is used. Even in such a case, it is possible to suppress the peeling phenomenon between the wiring and the insulating film in contact therewith.

[0018]

EXAMPLES Examples of the present invention will be described in detail below.

(Embodiment 1) FIG. 1 is an enlarged sectional view of an essential part of a semiconductor integrated circuit device which is an embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor integrated circuit device of FIG.

The semiconductor integrated circuit device according to the first embodiment has a TQFP (Thin Quad Flat Packag) as shown in FIG.
e) It is 1.

Package body 2 constituting TQFP1
Is made of, for example, an epoxy resin, and the semiconductor chip 3 is sealed inside the chip mounting portion 4a in a mounted state.

A logic circuit such as a gate array or a DRAM (Dynamic RA) is provided on the main surface of the semiconductor chip 3.
A semiconductor memory circuit such as M) is formed, and this circuit is electrically connected to the inner lead 4b through the bonding wire 5.

The inner lead 4b is electrically connected to an external circuit (not shown) through an outer lead 4c integrally formed with the inner lead 4b. The outer lead 4c is a lead portion protruding from the package body 2, and is formed in, for example, a gull wing shape.

Next, FIG. 1 shows an enlarged cross-sectional view of the main part of such a TQFP 1. The semiconductor substrate 3a forming the semiconductor chip 3 is made of, for example, silicon (Si) single crystal, and a predetermined semiconductor integrated circuit element (not shown) is formed on the upper surface thereof so as to cover the semiconductor integrated circuit element. An insulating film 3b is deposited on the.

The insulating film 3b is made of, for example, silicon dioxide (Si
O ₂ ), and on its upper surface, for example, aluminum (A
1) or a first layer wiring 3c made of Al alloy is formed, and an interlayer insulating film 3d is deposited so as to cover the first layer wiring 3c. The interlayer insulating film 3d is
For example, it is made of a polyimide resin having a molecular structure represented by the following chemical formula, and in the first embodiment, for example, PIQ is used.

[0026]

[Chemical 1]

A second layer wiring 3e made of, for example, Al or Al alloy is formed on the interlayer insulating film 3d, and a surface protective film 3f is deposited so as to cover the second layer wiring 3e. . The surface protective film 3f is made of a polyimide-based resin having the same molecular structure as the underlying interlayer insulating film 3d.

By the way, in the first embodiment, the stress relaxation film 3g is provided between the package body 2 and the surface protection film 3f.
Are formed. The stress relaxation film 3g is a film for relaxing the thermal stress applied to the semiconductor chip 3 during the reflow mounting process of the TQFP 1.

The stress relaxation film 3g is made of, for example, a polyimide resin having a molecular structure represented by the following chemical formula.
In, for example, L110 is used.

[0030]

[Chemical 2]

That is, in the first embodiment, the stress relaxation film 3g is made of a polyimide resin whose molecular structure is different from that of the surface protection film 3f.

Therefore, the surface protective film 3f and the stress relaxation film 3
The adhesive force with g is weaker than the adhesive force between the stress relaxation film 3g and the package body 2.

Therefore, in the TQFP 1 of the first embodiment, when excessive stress is applied to the semiconductor chip 3 during the reflow mounting process, the stress relaxation film 3g and the surface protection film 3f.
The structure is such that a peeling phenomenon occurs between and.

As a result, between the surface protective film 3f and the interlayer insulating film 3d, or between the interlayer insulating film 3d and the insulating film 3
b, that is, the stress applied to the layer in which the second-layer wiring 3e and the first-layer wiring 3c are formed can be relaxed, so that the peeling phenomenon in that layer can be suppressed. ing.

As described above, according to the first embodiment, the surface protective film 3 is formed on the surface protective film 3f made of polyimide resin.
By providing the stress relaxation film 3g made of a polyimide resin having a molecular structure different from that of f, the following effects can be obtained.

That is, even if an excessive stress is applied to the semiconductor chip 3 during the reflow mounting process of the TQFP 1, the peeling phenomenon occurs between the stress relaxation film 3g and the surface protective film 3f, and as a result, the first layer wiring 3c and Since the stress applied to the layer in which the second layer wiring 3e is formed can be relaxed, it becomes possible to suppress the peeling phenomenon in the layer in which the first layer wiring 3c and the second layer wiring 3e are formed.

Therefore, it is possible to prevent the wiring and the elements from being contaminated by moisture, ions, or the like that have entered through the peeled portion in the layer in which the first layer wiring 3c or the second layer wiring 3e is formed. It is possible to reduce the occurrence rate of wiring corrosion, element failure, and the like. Therefore, TQ
It is possible to improve the yield and reliability of FP1.

(Embodiment 2) FIG. 3 is an enlarged sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, as shown in FIG. 3, the stress relaxation film 3g is provided between the interlayer insulating film 3d and the surface protective film 3f.

However, in Example 2, the molecular structure of the polyimide resin forming the stress relaxation film 3g is the same as that of the polyimide resin forming the surface protection film 3f, and the interlayer insulating film 3d is formed. It has a different molecular structure from that of the polyimide resin.

Therefore, in the second embodiment, when stress is applied to the semiconductor chip 3 during the reflow mounting process,
The peeling phenomenon occurs between the interlayer insulating film 3d and the stress relaxation film 3g.

As a result, the stress applied to the layer in which the second layer wiring 3e and the first layer wiring 3c are formed can be relieved, so that the peeling phenomenon in the layer can be suppressed. Has become.

Therefore, also in the second embodiment, the same effect as that of the first embodiment can be obtained.

(Embodiment 3) FIG. 4 is an enlarged cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the third embodiment, as shown in FIG. 4, the stress relaxation film 3g and the insulating film 3h are sequentially deposited from the lower layer between the surface protective film 3f and the package body 2.

The insulating film 3h is made of a polyimide resin having the same molecular structure as the surface protective film 3f, and is adhered to the package body 2 with a high adhesive force.

In the third embodiment, the stress relaxation film 3g is made of, for example, epoxy resin, and the surface protection film 3f and the insulating film 3 are formed.
It is made of a resin that reduces the adhesiveness with h. That is, in the third embodiment, when stress is applied to the semiconductor chip 3 during the reflow mounting process, a peeling phenomenon occurs between the surface protective film 3f and the insulating film 3h, which results in the first layer wiring 3c and the second layer. The structure is capable of reducing the stress applied to the layer in which the wiring 3e is formed.

Therefore, also in the third embodiment, the same effect as in the first and second embodiments can be obtained.

(Embodiment 4) FIG. 5 is an enlarged sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the present embodiment 4, the first layer wiring 3c and the second layer wiring 3e are curated (heat treated).
Has been applied. The curate process is performed on the semiconductor substrate 3a.
After being stored in the atmosphere, for example, at 350 ° C., about 3
The heat treatment is performed for about 0 minutes.

Then, the insulating film 3 is formed by such a treatment.
b and the interlayer insulating film 3d and between the interlayer insulating film 3d and the surface protective film 3f, the insulating film 3b and the interlayer insulating film 3d, the interlayer insulating film 3d and the surface protective film 3f, the interlayer insulating film 3d and the first layer wiring 3c. Further, the reinforcing layer 6 is formed so as to strengthen the adhesive force between the surface protective film 3f and the second layer wiring 3e.

Therefore, according to the fourth embodiment, the peeling phenomenon in the layer in which the first-layer wiring 3c and the second-layer wiring 3e are formed can be suppressed, and moisture and ions that have penetrated through the peeled portion in the layer can be suppressed. Since it is possible to prevent the wiring and the element from being contaminated by the above, it is possible to reduce the occurrence rate of the wiring corrosion and the element failure. As a result, it becomes possible to improve the yield and reliability of TQFP1.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned first to fourth embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the above-mentioned embodiment, the case where the semiconductor substrate is made of Si has been described, but the present invention is not limited to this, and various modifications are possible.
A compound semiconductor such as arsenic (GaAs) may be used.

In the above description, the invention made by the present inventor is a field of application which is the background of the invention.
However, the present invention is not limited to this and can be applied in various ways. For example, SOP (Small Outline Pa
ckage), SOJ (Small Outline J-Lead Package), and other semiconductor integrated circuit devices.

[0056]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) According to the first aspect of the invention, the stress applied between the predetermined insulating films of the semiconductor chip during the reflow mounting process of the package can be relieved, so that the sealing with high adhesion to the semiconductor chip is achieved. Even when the resin for use is used, it is possible to suppress the peeling phenomenon between the wiring and the insulating film in contact therewith. Therefore, it is possible to suppress the contamination of the wiring or the element by the moisture or the ions that have penetrated through the peeled portion in the layer where the wiring is formed, so that the occurrence rate of the wiring corrosion or the element failure can be reduced. Is possible. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

(2) According to the second invention, since the adhesive force between the wiring of the semiconductor chip and the insulating film in contact therewith can be improved, a sealing resin having high adhesiveness with the semiconductor chip is used. Even when it is used, it is possible to suppress the peeling phenomenon between the wiring and the insulating film in contact therewith. Therefore, it is possible to suppress the contamination of the wiring or the element by the moisture or the ions that have penetrated through the peeled portion in the layer where the wiring is formed, so that the occurrence rate of the wiring corrosion or the element failure can be reduced. Is possible. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

[0059]

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of a main part of a semiconductor integrated circuit device that is an embodiment of the present invention.

2 is a cross-sectional view of the semiconductor integrated circuit device of FIG.

FIG. 3 is an enlarged cross-sectional view of a main part of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 4 is an enlarged cross-sectional view of a main part of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 5 is an enlarged cross-sectional view of a main part of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

 1 TQFP (semiconductor integrated circuit device) 2 package body 3 semiconductor chip 3a semiconductor substrate 3b insulating film 3c first layer wiring 3d interlayer insulating film 3e second layer wiring 3f surface protective film 3g stress relaxation film 3h insulating film 4a chip mounting portion 4b Inner lead 4c Outer lead 5 Bonding wire 6 Reinforcement layer

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having a multi-layered wiring structure, wherein a semiconductor chip has an insulating film between wiring layers made of a polyimide resin and an insulating film for surface protection, and a sealing resin for sealing the semiconductor chip. A semiconductor integrated circuit device, wherein a stress relaxation film for relaxing stress applied to a predetermined insulating film of the semiconductor chip is provided between the insulating film for surface protection. 2. The semiconductor integrated circuit device according to claim 1, wherein the stress relaxation film is made of a polyimide resin having a molecular structure different from that of the insulating film for surface protection. 3. A semiconductor integrated circuit device having a multi-layer wiring structure, wherein a semiconductor chip has an insulating film between wiring layers made of a polyimide resin and an insulating film for surface protection. A semiconductor integrated circuit device comprising a stress relaxation film for relaxing stress applied between predetermined insulating films of a semiconductor chip. 4. A semiconductor integrated circuit device having a multilayer wiring structure, wherein a semiconductor chip has an insulating film between wiring layers made of a polyimide resin and an insulating film for surface protection, wherein the wiring is formed on the semiconductor chip. A semiconductor integrated circuit device characterized by being subjected to a curating process.