JPH06349207A - Information reproducer - Google Patents

Abstract

PURPOSE:To decode data accurately regardless of the change of a temperature, humidity, etc. CONSTITUTION:A regenerative signal regenerated by a recording medium such as a magnetic discs is amplified by a regenerative amplifier 31, and converted to a digital signal by an A/D converter 202. The digital signal output from the A/D converter 202 is equalized by a waveform equalizer 203, and decoded in decoder 116. The decoder 116 is composed of a Viterbi decoder. A level estimation circuit 32 estimates the level of the digital signal output from the waveform equalizer 203, and output to the decoder 116. The decoder 116 utilizes an estimate supplied from the level estimation circuit 32, and Viterbi-decodes the digital signal fed from the waveform equalizer 203.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus suitable for use in decoding information recorded on a magnetic disk, a magnetic tape, an optical disk, a magneto-optical disk, etc. by the Viterbi decoding method.

[0002]

2. Description of the Related Art Partial response is used as a modulation code in a magnetic recording / reproducing apparatus or an optical recording / reproducing apparatus. As a type of partial response, one commonly used is PRS (1, 1) (class I). , PRS
(1, -1), PRS (1, 0, -1) (class IV) and the like. The arithmetic circuit 101 shown in FIG.
(1, 0, -1) is used, and the arithmetic circuits 102 and 103 shown in FIG. 8B use PRS (1, -1). PRS (1, 0, -1) system polynomial G (D) of a G (D) = 1-D 2, PRS
The system polynomial G (D) of (1, -1) is G (D) =
1 + D. Here, D is a delay operator.

The arithmetic circuit 101 is a circuit for sequentially outputting 1, 0, -1 data when an isolated logic 1 is input, and the arithmetic circuits 102 and 103 are provided when an isolated logic 1 is input. , 1, −1 are sequentially output.

The arithmetic circuit 101 (PRS) shown in FIG.
(1,0, -1) in), since it has a system polynomial G (D) = 1-D 2, input data y _k at a certain sampling time k are always two previous to the sample y _k-2 arithmetic To be done. Therefore, the odd-numbered sample and the even-numbered sample are substantially independent, and can be regarded as independent partial response PRS (1, -1) series. That is, in the circuit of FIG. 8A, as shown in FIG. 8B, the switches 104 are switched to the arithmetic circuits 102 and 103 of the partial response PRS (1, -1) to switch the odd-numbered input data. This is equivalent to a circuit in which samples and even-numbered samples are supplied and processed, and the outputs thereof are combined by the switch 105 and output.

That is, the arithmetic circuits 102 and 103 (PRS)
Decoding by using (1, -1)) while interleaving, and the operation circuit 101 (PRS (1,0,-
Decoding by 1)) is essentially the same, and here, the partial response PRS (1, 0, -1) will be described as an example.

Partial response PRS (1,0,-
1) itself has a property of propagating an error, and under certain conditions, 1
Bit errors can cause catastrophic errors. Therefore, in order to prevent this, it is necessary to precode before recording. This precoding can be realized by performing the inverse conversion of the partial response.

In FIG. 9, precoding is performed in this way,
The overall configuration of a system that performs modulation / demodulation of a partial response is shown. In the figure, the precoder 111 is 1 /
The process of (1-D ² ) is executed.

The recording data is converted by the precoder 111 into precode data which changes between the values 1 and -1 of the recording data by the precoder 111, and then the recording channel circuit 112. Is output to.

The recording channel circuit 112 is not a circuit provided specially, but represents the function originally possessed by the magnetic recording / reproducing system as an equivalent circuit. In this circuit (that is, when data is magnetically recorded and reproduced), (1-D) arithmetic processing is performed on the output of the precoder 111 in the arithmetic processing circuit 113.

At this time, the noise generated in the actual magnetic recording channel is treated as being added to this operation result by the adder 114, and the data to which this noise is added (data reproduced after magnetic recording) is recorded in the subsequent stage. Is output to the arithmetic processing circuit 115. The arithmetic processing circuit 115 performs (1 + D) arithmetic processing on the output from the recording channel circuit 112.

The signal output from the recording channel circuit 112 takes one of three levels {-2, 0, +2}, as shown in FIG. 10, when the signal level range is ± 2. For decoding the original binary data (1 or 0) by the decoder 116, a ternary level detection method using a fixed threshold and Viterbi decoding which is a maximum likelihood decoding method can be considered.

In the ternary level detection method, threshold levels having predetermined fixed values are set between 0 and +2 and between 0 and -2, respectively, and whether the sample points are larger or smaller than the threshold level is set. It has the advantage that the circuit is very simple, but has the drawback that the detection capability is relatively low.

On the other hand, the maximum likelihood decoding method (Viterbi decoding) decodes data by using the values of the sample points before and after, and detects the series (path) of the data obtained as a result of decoding, and It is a method of estimating a probable sequence (path) and has a higher detection capability than the ternary level detection method. When the same data is decoded, the bit error rate is 1 digit to 2 digits. Be improved.

Next, a circuit example when the decoder 116 is configured by a Viterbi decoder will be shown. As a preparation for the preceding step, Viterbi decoding will be described. PRS
A system using (1, 0, -1) has a system polynomial of 1-D ² and thus has four states. 1 from this system
If you take out the data bit by bit, one system (that is,
PRS (1, -1)), and the system polynomial is 1
Since it is -D, it has two states.

The state transition diagram of PRS (1, -1) is shown in FIG.
As shown in 1. That is, in PRS (1, -1), when 1 is input when the state is a _k-2 = -1, the state transitions to a _k = + 1 and 2 is output, and When −1 is input, the state transitions to the same state as the original state, that is, a _k = + 1, and 0 is output. Furthermore, when the state is a _k-2 = + 1, 1
Is input, the state transitions to a _k = -1, and -2 is output, and when -1 is input, the state is the same as the original state, that is, a _k = _-1. When it transits to -1, 0 is output.

A trellis diagram (likelihood tracking diagram) (hereinafter referred to as a trellis) corresponding to the state transition diagram of FIG. 11 is as shown in FIG. Here, in this trellis, when a sampled value (in this case, the output of the arithmetic processing circuit 115) y _k is input at a certain sample time k, the branch metric that transits from the state a _{k -2} to the state a _k value (corresponding to the instantaneous measure of the likelihood) is multiplied by -1 to the square error of the sample value y _k (- (y ₂ -
0) ² ,-(y ₂ -2) ² ,-(y ₂ +2) ² , ...).

Viterbi decoding is to find a path that maximizes the sum of these branch metrics. State a _k = up to a certain sample time k
For the path metrics (corresponding to the path integral of the likelihood) L _k ⁺ and L _k ^{− at} +1 and a _k = −1, the path metric value L _{k-2 up} to the previous sample time _k-2 is used. hand,
It can be expressed as in the following equations (1) and (2).

L _k ⁺ = max {L _k-2 ⁺ + [− (y _k −0) ² ], L _k−2 ⁻ + [− (y _k −2) ² ]} (1) L ^{_{k - = max {L k-}} 2 + + [- (y _k +2) ^2], L _k-2 ^- + [- (y _k -0) ^2]} (2)

Here, max {A, B} means that the larger one of A and B is selected.

In order to detect the optimum path while calculating this metric, normally three squarers and six adders are used.
Two and two comparators are required. Therefore, instead of faithfully calculating the path metric, the algorithm using the differential metric reported by Wood et al. Can be used in order to simplify the circuit.

Now, consider the Viterbi algorithm when there are only two states. The Viterbi algorithm determines data for each state at a certain time k while narrowing down one path having the largest likelihood to reach that state. The decoding circuit (decoder 116) described above is for realizing it faithfully.

That is, the path metric difference (differential metric) in each of the states a _k = + 1 and −1 can be expressed by the following equation. ^{_{ΔL k = L k + -L k}} - ··· (3)

[0023] from equation (1), path metric L _k ⁺ is, L _k-2 ^{+ +} [- (y _k -0) ^2]> L _k-2 ^- + [- (y _k -
2) ² ] (when the likelihood of transition from the state a _k-2 = + 1 to the state a _k = + 1 is large), L _k-2 ⁺ + [− (y _k −0) ² ], and L _k-2 ⁺ + [- (y _k -0) ^2] ≦ L _k-2 ^- + [- (y _k -
2) ² ] (when the likelihood of making a transition from the state a _k-2 = -1 to the state a _k = + 1 is large), L _k-2 ⁻ + [− (y _k −2) ² ]. .

[0024] On the other hand, from equation (2), path metric L _k ^-
Is L _k-2 ⁺ + [− (y _k +2) ² ]> L _k-2 ⁻ + [− (y _k −
0) For ^2] (state a _k-2 = + 1, when the likelihood of transition to state a _k = -1 is large), L _k-2 ^{+ +} [- (y _k +2) ^2] becomes, L _k-2 ⁺ + [- (y _k +2) ^2] ≦ L _k-2 ^- + [- (y _k -
0) ² ] (when the likelihood of transition from the state a _k-2 = −1 to the state a _k = −1 is large), L _k−2 ⁻ + [− (y _k −0) ² ] Become.

That is, to summarize, the path metric L
_k ⁺ is in the case of 4> 4y _k −ΔL _{k −2} (C ⁺ 1) (when the likelihood of transition from the state a _{k −2} = + 1 to the state a _k = + 1 is large), In the two cases of 4 ≦ 4y _k −ΔL _{k −2} (C ⁺ 2) (when the likelihood of making a transition from the state a _k−2 = −1 to the state a _k = + 1 is large). When the values are different and the path metric L _k ⁻ is −4> 4y _k −ΔL _k−2 (C ⁻ 1) (from state a _k−2 = + 1 to state a _k = −1). When the likelihood of transition to is large) and -4 ≦ 4y _k −ΔL _{k −2} (C ⁻ 2) (from state a _k−2 = −1 to state a _k = −1). The value is different in two cases (when the likelihood of transition is large).

Therefore, the differential metric ΔL _k represented by the equation (3) is (C ⁺ 1) and (C ^- 1), (C ⁺ 2) and (C ^- 2), (C ⁺ 1). and ^(C - 2), and (C ⁺ 2)
And there are 4 (= 2 × 2) cases of (C ^- 1).

[0027] That is, _{first, 4> 4y k - △ L} k-2, and -
When 4> 4y _k −ΔL _{k −2} (the surviving path is in the state <+
1> → state <+1> and state <+1> → state <-1>), that is, -4> 4y _k −ΔL _k-2
In the case of, the differential metric ΔL _k is ΔL _k = {L _k−2 ⁺ + [− (y _k −0) ² ]} − {L _k−2 ⁺ + [− (y _k +2) ² ]. ^{_{} = L k-2 + -y}} k 2 -L k-2 - + a ^{_{y k 2 + 4y k +4 =}} 4y k +4.

_{Furthermore, 4 ≦ 4y k - △ L} k-2, and -4 ≦
In the case of 4y _k −ΔL _{k −2} (the surviving path is in the state
→ state <−1> and state <−1> → state <+1> pattern), that is, 4 ≦ 4y _k −ΔL _k−2 ,
The differential metric ΔL _k is ΔL _k = {L _k−2 ⁻ + [− (y _k −2) ² ]} − {L _k−2 ⁻ + [− (y _k −0) ² ]} = L ^_k-2 - a ^{_{+ y k 2 = 4y k -4}} - -y k 2 + 4y k -4-L k-2.

_{Further, 4> 4y k - △ L} k-2, and -4 ≦ 4
In the case of y _k −ΔL _k−2 (the surviving path is in the state <−1> →
In the case of the pattern of state <−1> and state <+1> → state <+1>), that is, in the case of −4 ≦ 4y _k −ΔL _k-2 <4, the differential metric ΔL _k is ΔL ^{_{k = {L k-2 +}} + [- (y _k -0) ^{_{2]} - {L k-2 -}} + [- (y _k -0) ^{_{2]} = L k-2 + -y}} k 2 - L _k-2 ⁻ + y _k ² = ΔL _k-2 .

[0030] _{Then, 4 ≦ 4y k - △ L} k-2, and -4>
In the case of 4y _k −ΔL _{k −2} (the surviving path is in the state
→ state <-1> and state <+1> → state <+1> pattern), if this equation is rearranged, 4≤4y _k
It is impossible because −ΔL _k−2 <−4.

From the above, the equation (3) can be classified according to the size of 4y _k -ΔL _k-2 , and the following (4)
It becomes like a formula.

[0032]

[Equation 1]

Therefore, there are two states (a _k = + 1 or a _k).
= -1), there are only three surviving path patterns as shown below. State <-1> → state <-1> and state <-1> → state <+1> state <-1> → state <-1> and state <+1> → state <+1> state <+1> → state <+1> and state <+1> → state <-1>

Here, three types of possible survivor path patterns will be represented by three types of two-letter symbols such as → ↑, →→, → ↓.

In the inequality of the case of the equation (4),
Since 4y _k −ΔL _k-2 is included as a common comparison element, by comparing this value with 4 or −4 and judging the magnitude thereof, the pattern of the surviving path is determined as the surviving path. It can be determined which one of the patterns. That is, even if the path metric itself is not calculated, if the differential metric is calculated, it is possible to determine the surviving path in the process and decode the data.

That is, y _p is a point (loc) when a path other than the parallel path (→→), that is, upward divergence (→ ↑) or downward divergence (→ ↓) appears in the trellis.
ation p) and β as
If a variable conversion is performed with a correction term of ΔL _k = 4y _p -4β, the expression (4) can be expressed as the following expression (5).

[0037]

[Equation 2]

Here, by comparing the left side and the right side of the equation (5), when the equality holds in the upper or lower stage, that is, upward divergence (→ ↑) as the pattern of the surviving path.
Or, when downward divergence (→ ↓) appears, β is 1 or -1, respectively.

Therefore, β is the direction of the divergence (that is, that point) at the point (location p) where the first upward divergence (→ ↑) or downward divergence (→ ↓) appears, dating back from the current point. (Location p)
Pattern of surviving path in diverging upward (→ ↑)
And which was the downward divergence (→ ↓)).

For example, if the divergence that first appears retroactively from the current point is an upward divergence (→ ↑), that is, β = + 1, the pattern of the surviving path at the current point is By substituting 1 into β of the case inequalities in the equation (5), when 0 ≦ y _k −y _p , upward divergence (→ ↑), and when −2 ≦ y _k −y _p <0, When parallel path (→→) and y _k −y _p <−2, it is determined to be downward divergence (→ ↓) (FIG. 13).

[0041] Further, in this case, by (5) comparing the left and right sides of the equation, beta and y _p, when the _{0 ≦ y k -y p, y} p ← y k, β ← + 1, -2 ≦ When y _k −y _p <0, it is updated as y _p ← y _p , β ← β, and when y _k −y _p <-2, y _p ← y _k , β ← −1 (FIG. 13). ).

Similarly, if the divergence that first appeared from the current point is the downward divergence (→ ↓), that is, β = −1, the survival path of the current point is The pattern is β in the inequality in equation (5).
The by substituting -1, when 2 ≦ y _k -y _p, the upward divergence (→ ↑), when _{0 ≦ y k -y p <2} , parallel path (→→), y _k -y when _p <0, it is determined that the downward divergence (→ ↓), beta and y _p, by comparing the left and the right side of formula (5), when _{2 ≦ y k -y p, y} p ← y _k , β ← + 1, when 0 ≦ y _k −y _p <2, y _p ← y _p , β ← β, and y _k −y _p <0, y _p ← y _k , β ← −1 To be updated.

Therefore, it can be seen that the meaning of β plays a role of adding an offset to the threshold value for judgment in the above formula (for this point, see Tables 1 and 2). See below).

When upward divergence (→ ↑) or downward divergence (→ ↓) appears as a survivor path pattern,
It is possible to determine the path from the point (location p) where the divergence before the point (location k) appeared to that point (location k), and it is possible to decode the data by repeating this. Becomes

FIG. 14 is a block diagram of the decoder 116 for decoding data based on the Viterbi algorithm.
Shown in. The reproduction data from the recording channel circuit 112 (FIG. 9) is input to the processing circuit 120 or 130, and the even-numbered column sample or the odd-numbered column sample is individually processed, and then, in the synthesizing circuit 141, the switching circuit 1 The original order is restored and output based on the timing of the output switching signal.

Although FIG. 14 shows the configuration of the processing circuit 120 for processing the even column samples in detail, the processing circuit 130 for processing the odd column samples has the same configuration.

In the processing circuit 120, the reproduction data from the recording channel circuit 112 is passed through the switch 14 which is turned on / off at the timing of even-numbered column sample / odd-numbered column sample in response to the switching signal output from the switching circuit 1. And is supplied to the subtraction circuit 11 and the register 12b.
That is, the even number column samples of the reproduced data are supplied to the subtraction circuit 11 and the register 12b.

The register 12b stores the sample value y _p in the previous divergence point subtraction circuit 11 subtracts the value y _p from even columns sample y _k inputted is stored in the register 12b (Calculate (y _k −y _p )),
Output to the comparison circuit 13.

The comparison circuit 13 has threshold values of +2, 0,-.
2, Table 1 and Table 2 corresponding to the output (y _k −y _p ) of the subtraction circuit 11 and β stored in the register 12a.
The arithmetic processing shown in Table 1 is performed, and the output data shown in Tables 1 and 2 is output according to the arithmetic result. Details of this calculation will be described later with reference to FIGS. 16 and 17.

[0050]

[Table 1]

[0051]

[Table 2]

As shown in FIG. 15, the shift register 121 has N selectors Sp _{1 to} Sp _N and flip-flops Dp _{1 to} Dp _N alternately connected in cascade, and is connected to the front stage of the frontmost selector Sp ₁ . A serial shift register to which the flip-flop Dp ₀ is connected, N selectors Sm _{1 to} Sm _N, and a flip-flop Dm ₁
It is configured as a parallel load / serial shift register in which a serial shift register in which No. Dm _N is alternately connected in cascade and a parallel shift register are connected.

Here, N is a processing unit length (the number of bits) for Viterbi decoding the reproduction data (even column samples).

For the selector Sp ₁ or Sm ₁ at the front stage,
0 is input as the signal B or D, and the surviving path pattern signal (merge) from the comparison circuit 13 is transmitted through the flip-flop Dp ₀ to the signal A or C.
And one of them (one of the signals A and B, or one of the signals C and D) is similarly input to the survivor path pattern signal (merge) and data (data) from the comparison circuit 13. ) Corresponding to the flip-flop Dp ₁ or Dm ₁
Are output respectively.

Here, in the comparison circuit 13, as shown in Tables 1 and 2, when the upward divergence or the downward divergence occurs, it is set to merge = 1, and in the case of the parallel path, The merge is set to 0.

The selector Sp _n or Sm _n (n = 1, 2, ..., Except the selectors Sp ₁ and Sm ₁ at the frontmost stage)
In (N), the data latched in the previous flip-flop Dp _n-1 is input as the signal A or C, and the data latched in the previous flip-flop Dm _n-1 is input as the signal B or D. Any one of them (one of the signals A and B, or one of the signals C and D) that has been input is used as a surviving path pattern signal (merge) and data (data) from the comparison circuit 13. It is correspondingly selected and output to the next-stage flip-flop Dp _{n + 1} or Dm _{n + 1} .

[0057]

[Table 3]

That is, the selector Sp _n (Sm _n ) is a survivor path pattern signal (merge) from the comparison circuit 13.
And, as shown in Table 3, either one of the input signals A and B (C and D) is selected and output corresponding to the data (data).

The flip-flop Dp _n or Dm _n outputs the output from the previous stage selector Sp _n or Sm _n to the PLL.
Each is latched in synchronization with a PLL clock output from (not shown).

If the configuration shown in FIG. 14 is used, the squarer is not required, and only one adder and two comparators are required.

Next, the operation when a certain signal is input to the circuit of FIG. 14 will be described with reference to FIGS. 16 and 17.
The timing chart will be described.

Now, when a signal as shown in FIG. 16 is input to the decoder 116 of FIG. 14, the comparison circuit 13 follows the table 1 and the table 2 and shift register 121 (see FIG. 1).
5) operates as follows according to Table 3.
However, the initial values of y _p and β are y _p = -2 and β, respectively.
= -1.

<K = 0: input y _k = y ₀ = 1.6; y _p =
-2; when β = -1> y _k -y _p = 1.6-(-2) =
Since 3.6> 2, the input corresponds to the condition pattern F in Table 2. In other words, upward divergence (hereinafter, as appropriate
Therefore, according to Table 2, β of the register 12a is updated to +1 and y of the register 12b is updated.
_p (sample value at the time of the last divergence)
Is set as y _p = y ₀ = 1.6.

At the same time, according to Table 2, the comparison circuit 13
Outputs the surviving path pattern signal (merge = 1) and the data (data = 1) to the shift register 121.

Therefore, the shift register 121 (FIG. 15)
Then, merge = 1 is latched in the flip-flop Dp ₀ (FIG. 17).

<K = 1: input y _k = y ₁ = 0.2; y _p =
1.6; β = + 1; when p = 0> -2 ≦ y _k −y _p =
Since 0.2-1.6 = -1.4≤0, the input corresponds to the condition pattern B in Table 1. In other words, it means that parallel paths, beta registers 12a and 12b, y _p is as it is _{(β = 1, y p =} y 0), the shift register 121 from the comparator circuit 13, the survivor path pattern signal (m
edge = 0) and data (data = 0) are output.

[0067] In the shift register 121, merge = 0 is latched in the flip-flop Dp _0, further me
Since rge = 0, according to Table 3, the selector Sp
_n or Sm _n , signals A and B or signals C and D
The signal A or D among them is selected and output to the flip-flops Dp _n or Dm _n of the next stage and latched.

That is, in the case of the parallel path pattern, the signal (bit) latched in the upper flip-flop Dp _n is the upper flip-flop Dp of the next flip-flop Dp _n.
The signal (bit) latched by _{n + 1} and the lower flip-flop Dm _n is also latched by the next lower flip-flop Dm _{n + 1} . However, in this case, the lower flip-flop Dm
₁ latches 0, which is always input to the selector Sm ₁ as the signal D.

Therefore, when k = 1, ₀ and 1 are latched in the upper flip-flops Dp ₀ and Dp ₁ , respectively,
0 is latched in the lower flip-flop Dm ₁ (FIG. 14).

<K = 2: input y _k = y ₂ = −0.2; y _p
= 1.6; β = + 1; when p = 0> -2 ≦ y _k −y _p =
Since −0.2−1.6 = −1.8 ≦ 0, the input corresponds to the condition pattern B in Table 1. In other words, it means that parallel paths, beta registers 12a and 12b, y _p is as it is, the shift register 121 from the comparator circuit 13
Then, the surviving path pattern signal (merge = 0) and the data (data = 0) are output.

In the shift register 121, merge = 0 is latched in the flip-flop Dp _0, and the merge = 0
= 0, the signal (bit) latched by the upper flip-flop Dp _n according to Table 3 is also latched by the upper flip-flop Dp _{n + 1} of the next stage, and the lower flip-flop Dp _{n + 1.} The signal (bit) latched by Dm _n is latched by the flip-flop Dm _{n + 1} of the next lower stage, which is also the lower stage.

Therefore, when k = 2, ₀ , ₁ , ₁ are respectively latched in the upper flip-flops Dp ₀ , Dp ₁ , Dp ₂ , and ₀ , ₀ in the lower flip-flops Dm ₁ , Dm _2. Are respectively latched (FIG. 17).

<K = 3: input y _k = y ₃ = 2.0; y _p =
1.6; β = + 1; when p = 0> y _k −y _p = 2.0−
Since 1.6 = 0.4> 0, the input corresponds to the condition pattern C in Table 1. That is, upward divergence
Therefore, the previous candidate y _p lost to the current value y _k (y _p <
It was y _k ). That is, when k = 0 (p = 0), the upward divergence (β = + 1) was determined, but this time (at k = 3), the upward divergence (β = +).
Since 1) occurred, the previous time was a parallel path of the upward divergence (if an upward transition occurs at k = 0, the path becomes discontinuous at k = 3). End).

Therefore, according to Table 1, the register 12
β of a is set to +1 and the stored value y _p of the register 12b is
It is y _p = y ₃ = 2.0. Further, the survivor path pattern signal (merge = 1) and data (data = 0) are output from the comparison circuit 13 to the shift register 121.

In the shift register 121, the flip-flop Dp ₀ is latched with merge = 1, and further, me
Since rge = 1 and data = 0, the signal B or D of the signals A and B or the signals C and D is selected by the selector Sp _n or Sm _n according to Table 3, and the flip-flop Dp of the next stage is selected. It is output to _n or Dm _n and latched.

That is, when the divergence that occurred immediately before is the upward divergence (β = + 1) and the current divergence is the upward divergence, it is latched as a decoded data candidate in the upper flip-flop Dp _n. signals (bits) becomes possible is lost, the signal being latched in the lower part of the flip-flop Dm _n (bits), the upper and lower, are latched into the next stage flip-flop Dp n _{+ 1} and Dm n _{+ 1} It However, in this case, the upper flip-flop Dp
₁ latches 0 which is always input as the signal B to the selector Sp ₁ .

Therefore, when k = 3, the flip-flops Dp ₀ , Dp ₁ , Dp ₂ and Dp ₃ in the upper stage have ₁ , ₀ , ₀ , ₀
Are each latched, and the lower flip-flop D
0, 0 and 0 are latched in m ₁ , Dm ₂ and Dm ₃ respectively (FIG. 17).

<K = 4: input y _k = y ₄ = 0.2; y _p =
2.0; β = + 1; when p = 3> -2 ≦ y _k −y _p =
Since 0.2−2.0 = −1.8 ≦ 0, the input corresponds to the condition pattern B in Table 1. In other words, it means that the parallel path, the register 12a, 12b, beta, y _p is left alone, the shift register 12 from the comparator circuit 13
The survivor path pattern signal (merge = 0) and the data (data = 0) are output to 1.

In the shift register 121, merge = 0 is latched in the flip-flop Dp ₀ and the merge
= 0, the signal (bit) latched by the upper flip-flop Dp _n is latched by the upper flip-flop Dp _{n + 1} and the lower flip-flop Dm _n as well. The signal (bit) that has been generated is latched in the flip-flop Dm _{n + 1} of the next stage, which is also the lower stage.

<K = 5: input y _k = y ₅ = −0.4; y _p
= 2.0; β = + 1; when p = 3> y _k −y _p = −0.
Since 4-2.0 = −2.4 <−2, the input corresponds to the condition pattern A in Table 1. That is, the downward diverg
Since it is ence, the previous candidate was correct (that is, there was an upward transition of the upward divergence at k = 3 (p = 3)).

Therefore, according to Table 1, the register 12
β of a is set to -1, and the stored value y _p of the register 12b is
are y _p = y ₅ = -0.4. Furthermore, the survivor path pattern signal (merge = 1) and data (data = 1) are output from the comparison circuit 13 to the shift register 121.

In the shift register 121, the flip-flop Dp ₀ is latched with merge = 1, and further, me
Since rge = 1 and data = 1, the signal A or C of the signals A and B or the signals C and D is selected by the selector Sp _n or Sm _n according to Table 3, and the flip-flop Dp of the next stage is selected. It is output to _n or Dm _n and latched.

That is, when the divergence that occurred immediately before is the upward divergence (β = + 1) and the current divergence is the downward divergence, it is latched by the upper flip-flop Dp _n as a decoded data candidate. signals (bits) becomes possible correct, signals latched by the upper stage flip-flop Dp _n (bits), upper and lower,
It is latched by the flip-flops Dp _{n + 1} and Dm _{n + 1} in the next stage.

<K = 6: input y _k = y ₆ = −0.2; y _p
= −0.4; β = −1; when p = 5> 0 ≦ y _k −y _p =
Since −0.2 − (− 0.4) = 0.2 ≦ + 2, the input corresponds to the condition pattern E in Table 2. In other words, it means that parallel paths, beta, y _p is left alone, the shift register 121 from the comparator circuit 13, the survivor path pattern signal (merge = 0) and the data (data
= 0) is output.

In the shift register 121, the flip-flop Dp ₀ latches the merge = 0, and the merge = 0.
= 0, the signal (bit) latched by the upper flip-flop Dp _n is latched by the upper flip-flop Dp _{n + 1} and the lower flip-flop Dm _n as well. The signal (bit) that has been generated is latched in the flip-flop Dm _{n + 1} of the next stage, which is also the lower stage.

<K = 7: input y _k = y ₇ = −2.0; y _p
= −0.4; β = −1; when p = 5> y _k −y _p = −
Since 2.0-(-0.4) =-1.6 <0, the input corresponds to the condition pattern D in Table 2. That is, the downward di
Since it is a vergence, the previous candidate has lost. That is, at k = 5 (p = 5), there is not a downward transition but a parallel transition.

Therefore, according to Table 2, the register 12
β of a is set to -1, and the stored value y _p of the register 12b is
are y _p = y ₇ = -2.0. Further, the survivor path pattern signal (merge = 1) and data (data = 0) are output from the comparison circuit 13 to the shift register 121.

In the shift register 121, the flip-flop Dp ₀ is latched with merge = 1 and further, me
Since rge = 1 and data = 0, the signal B or D of the signals A and B or the signals C and D is selected by the selector Sp _n or Sm _n according to Table 3, and the flip-flop Dp of the next stage is selected. It is output to _n or Dm _n and latched.

[0089] That is, (be beta = -1) is the divergence is a downward divergence occurs just before, if further now divergence is a downward divergence, is latched as the decoded data candidates in the upper part of the flip-flop Dp _n they were signals (bits) becomes possible is lost, the signal being latched in the lower part of the flip-flop Dm _n (bits), the upper and lower, the next stage flip-flop Dp n _{+ 1} and Dm n _{+ 1} to the latch To be done. However, in this case, the upper flip-flop Dp
₁ latches 0 which is always input as the signal B to the selector Sp ₁ .

<K = 8: input y _k = y ₈ = 0.2; y _p =
−2.0; β = −1; when p = 7> y _k −y _p = 0.2
Since-(-2.0) = 2.2> +2, the input corresponds to the condition pattern F in Table 2. In other words, since it is an upward divergence, the previous data was correct.
That is, at k = 7 (p = 7), a downward transition has occurred.

Therefore, according to Table 2, the register 12
β of a is set to 1, and the stored value y _p of the register 12 b becomes y _p
= Y ₈ = 0.2. Furthermore, the survivor path pattern signal (m
edge = 1) and data (data = 1) are output.

In the shift register 121, the flip-flop Dp ₀ is latched with merge = 1, and further, me
Since rge = 1 and data = 1, the signal A or C of the signals A and B or the signals C and D is selected by the selector Sp _n or Sm _n according to Table 3, and the flip-flop Dp of the next stage is selected. It is output to _n or Dm _n and latched.

[0093] That is, (be beta = -1) is the divergence is a downward divergence occurs just before, if further now divergence is the upward divergence, is latched as the decoded data candidates in the upper part of the flip-flop Dp _n it was signals (bits) becomes possible correct, signals latched by the upper stage flip-flop Dp _n (bits), upper and lower,
It is latched by the flip-flops Dp _{n + 1} and Dm _{n + 1} in the next stage.

Thereafter, the data is similarly decoded. At the end of the bit string, a bit that causes condition A or C in Table 1 or condition D or F in Table 2 is added.
Alternatively, when the condition D or F in Table 2 occurs, the stored values of the upper flip-flops Dp _{1 to} Dp _N and the lower flip-flops Dm _{1 to} Dm _N match, so the upper flip-flop Dp _N The Viterbi-decoded data can be obtained by sequentially receiving the data (bit) latched by any one of the flip-flops Dm _N and the flip-flops Dm _{N in} the lower stage (for example, the flip-flop Dp _{N in the} upper stage). .

[0095]

As described above, in order to perform the Viterbi decoding by the decoder 116, information on the amplitude value of the reproduction signal is necessary. However, the amplitude value (reproduction level) of the reproduction signal is the recording medium. As a result of a change in magnetic characteristics of the magnetic disk or the recording / reproducing head as described above, or a change in the flying height between the head and the magnetic disk, as shown in FIG. However, the level will change. If the level, which should be constant, changes in this way, it becomes difficult to read the data accurately. Therefore, in order to control the reproduction level, conventionally, for example, a configuration as shown in FIG. 19 has been used.

That is, in the example of FIG. 19, after the reproduction signal from the magnetic disk is controlled to a predetermined level by the AGC amplifier 201, the A / D converter 202 performs A / D conversion.
To be converted. Then, the digital signal converted by the A / D converter 202 is input to the waveform equalization circuit 203,
After equalization, it is supplied to the decoder 116.

Alternatively, as shown in FIG. 20, the amplitude of the data output from the waveform equalization circuit 203 is detected by the amplitude detection circuit 204, and the gain of the AGC amplifier 201 is adjusted according to the detection result. It was supposed to be done.

However, in the case of the configuration shown in FIGS. 19 and 20, since the AGC amplifier 201 is an analog circuit, the characteristics may change due to changes in humidity, temperature, etc., or changes over time. . Therefore, there is a problem that it is difficult to read the data accurately.

The present invention has been made in view of such a situation, and makes it possible to read data more accurately.

[0100]

The information reproducing apparatus of the present invention is an information reproducing apparatus which reproduces predetermined recording data recorded on a recording medium from the recording medium by using the partial response method, and is reproduced from the recording medium. A / D converter 202 as an analog-digital conversion means for converting the signal level of the reproduction signal into a digital signal, and A / D converter 2
A level estimation circuit 32 as an amplitude estimation means for estimating and outputting the amplitude value of the digital signal output from
Decoder 1 as decoding means for decoding the digital signal output from the / D converter 202 by maximum likelihood decoding corresponding to the amplitude value output from the level estimation circuit 32.
And 16 are provided.

The level estimation circuit 32 estimates at least one of the positive and negative amplitude values of the digital signal, independently estimates the positive amplitude value and the negative amplitude value, and outputs the difference value thereof. The amplitude value of 0 and the amplitude value of 0 are independently estimated and the difference value is output, or the amplitude value of 0 and the negative amplitude value are estimated independently and the difference value is output. You can

As a partial response system,
The partial response (1, -1) is used, the partial response class IV is used, and the decoder 116
In addition, a pair of circuits for partial response (1, -1) code reproduction can be used.

[0103]

In the information reproducing apparatus having the above structure, the level estimating circuit 32 estimates the level of the digital signal, and the decoder 116 performs decoding in accordance with this estimated value. As a result, the data can be read accurately.

[0104]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an embodiment of the information reproducing apparatus of the present invention, in which parts corresponding to those in FIG. That is, in this embodiment, a reproduction signal reproduced by a magnetic head from a recording medium such as a magnetic disk is amplified by the reproduction amplifier 31 and then input to the A / D converter 202 to convert an analog signal into a digital signal. It is designed to be converted. Then, the digital signal output from the A / D converter 202 is input to the waveform equalization circuit 203, equalized, and then supplied to the decoder 116.

This decoder 116 is constructed as shown in FIG. That is, also in this embodiment, recording / reproduction of data is performed using the partial response class IV. The level estimation circuit 32 includes a waveform equalization circuit 203.
The level of the digital signal output by the decoder 1
It is designed to output to 16.

The waveform equalizing circuit 203 is composed of, for example, an FIR filter, and the output thereof is a signal string y of sample points which changes between A- and A + as shown in FIG.
_k . A + represents the positive signal level of the digital signal after equalization, and A- represents the negative signal level. In the above description of the partial response, A + and A− are fixed values of +2 and −2, respectively. However, in practice, this value changes the flying height of the head from the disk, changes in magnetic characteristics, Further, it changes with time due to the influence of the charge of the input stage at the moment when the reproduction amplifier 31 is turned on. So this A + and A
The value of − is changed (tracked) in accordance with the output of the level estimation circuit 32.

The level estimation circuit 32 is constructed, for example, as shown in FIG. In this embodiment, the digital signal supplied from the waveform equalization circuit 203 is input to the IIR filter 42 and also to the comparison circuit 41. The comparison circuit 41 compares the level of the input digital signal with a predetermined reference value T +. As shown in FIG.
The reference value T + is set to a predetermined value between the maximum level A + and the 0 level of the digital signal output from the waveform equalization circuit 203.

The comparison circuit 41 controls the IIR filter 42 to be in an operating state when the level of the digital signal input from the waveform equalization circuit 203 is larger than the reference value T +, and when it is smaller than the reference value T +, IIR filter 4
2 is controlled so as to be in a non-operating state (a state in which the previous value is held). As a result, the IIR filter 42 outputs a signal corresponding to the amplitude level when it is determined that the level of the digital signal input from the waveform equalization circuit 203 is higher than the reference value T + (when estimated to be A +). To do.

The IIR filter 42 executes a process for calculating a new output in accordance with the difference between the newly input data and the currently output data, for example.

The signal A + output from the IIR filter 42
Is input in place of the absolute value (2) of the +2 and −2 values of the comparison circuit 13 of FIG. That is, in the process of comparing y _k −y _p with the value 2 in Table 2, instead of the value 2, the IIR
The output of the filter 42 is used. In addition, y _k − in Table 1
In the process of comparing the y _p and the value (-2), the value (-
The output of the IIR filter 42 is used instead of the absolute value (2) of 2). In other words, the signal in which the polarity of the output signal A + is made negative is used instead of the value (-2).

In the embodiment shown in FIG. 3, the comparison circuit 4
Although the value is compared with the reference value T + in 1, the value may be compared with T-. In this case, the comparison circuit 41
When the level of the digital signal input from the waveform equalization circuit 203 is smaller than the reference value T-, the IIR filter 42 is activated, and when it is larger than the reference value T-, II
The internal state of the R filter 42 is retained as it is. Thus, in Table 1 and Table 2, the signal A- is generated to replace the value -2 comparison with y _k -y _p. A signal obtained by inverting the polarity of the signal A- is used instead of the value 2.

In this way, even if the level of the digital signal output from the waveform equalization circuit 203 changes as shown in FIG. 18, the influence can be removed and the data can be reproduced accurately. Become. Moreover, since all of this processing is performed in the state of digital signals, it is possible to prevent the characteristics from changing due to changes in temperature, humidity, etc., or changes over time. It is also advantageous for circuit integration.

In the embodiment of FIG. 3, it is assumed that only the amplitude (AC component) of the reproduced signal fluctuates. However, if the reproduced signal has a DC component as shown in FIG. 4, for example, the embodiment of FIG. Then, the amplitude value may be erroneously estimated. If the amplitude value is erroneously estimated, the decoder 116 operates on the basis of the erroneous estimated value, which makes it difficult to decode the correct value. Therefore, the level estimation circuit 32 can be configured as shown in FIG. 5, for example.

In FIG. 5, the level estimation circuit 32
From the output A + of the first estimating circuit 51, the second estimating circuit 52, the first estimating circuit 51 to the output A− of the second estimating circuit 51.
And a division circuit 54 that divides the output of the subtraction circuit 53 by 2 by shifting the output of the subtraction circuit 53 by 1 bit, for example.

The first estimation circuit 51 includes a comparison circuit 41 and I
It is composed of an IR filter 42. That is, the first estimating circuit 51 has the same configuration as that shown in FIG. 3 and outputs the signal A +.

Further, the second estimation circuit 52 includes the comparison circuit 6
1 and the IIR filter 62. The comparison circuit 61 compares the digital signal supplied from the waveform equalization circuit 203 with a reference value T-, and when the level of the digital signal is smaller than the reference value T-, sets the IIR filter 62 in the operating state and sets the reference value T-. IIR filter 6 when larger
2 is made inactive. As a result, the IIR filter 62
Outputs the signal A- corresponding to the amplitude value only when the level of the digital signal output from the waveform equalization circuit 203 is smaller than the reference value T-.

The subtraction circuit 53 subtracts the output A- of the second estimation circuit 52 from the output A + of the first estimation circuit 51 ((A +)-(A-)) and supplies it to the division circuit 54. For example, a division circuit 54 including a bit shifter
Shifts the input digital signal by 1 bit to the lower order (halves it) and outputs it (((A +)-(A-))
/ 2). Since A- has the opposite polarity to A +, ((A +)-
(A−)) has a value about twice that of A +. Therefore, this value is halved to substantially obtain the value of A +. This signal is supplied to the comparison circuit 13 in FIG.

According to this embodiment, even in the case where the fluctuation of the DC component as shown in FIG. 4 is included, the A- that also includes the DC fluctuation is subtracted from the A + that includes the DC fluctuation. Therefore, by removing this, correct decoding becomes possible.

FIG. 6 shows still another embodiment,
In this embodiment, the level estimating circuit 2 includes the first estimating circuit 51, the second estimating circuit 52 and the subtracting circuit 53.
Is configured. The first estimation circuit 51 is configured similarly to the case in FIG.

In the second estimation circuit 52, the comparison circuit 61 compares the digital signal with the reference value T + and the reference value T-. Comparison circuit 6
1 indicates that when the level of the digital signal supplied from the waveform equalization circuit 203 is larger than the reference value T- and smaller than the reference value T +, the IIR filter 62 is activated and the reference value T
When it is larger than + or smaller than the reference value T-, the IIR filter 62 is made inoperative. That is, the IIR filter 62 has three reference values of (−A, A ₀ , + A)
The reference value A ₀ corresponding to ₀ is output.

On the other hand, since the first estimating circuit 51 outputs A +, as in the case of FIG. 5, the output of the subtracting circuit 53 becomes ((A +)-(A ₀ )). Since A ₀ is almost 0, this value is substantially A +. The output of the subtraction circuit 53 is supplied to the comparison circuit 13 of FIG.

FIG. 7 shows still another embodiment.
In this embodiment, the first estimating circuit 51 is constructed in the same manner as the second estimating circuit 52 in the embodiment of FIG. That is, the comparison circuit 41 compares the level of the digital signal with the two reference values T- and T +,
When the level of the digital signal is between the reference values T- and T +, the IIR filter 42 is activated. As a result, the IIR filter 42 outputs A ₀ .

The second estimating circuit 52 is constructed similarly to the case in FIG. Therefore, the output of the second estimation circuit 52 is A-. The subtraction circuit 53 has a first
Since the output A- of the second estimation circuit 52 is subtracted from the output A ₀ of the estimation circuit 51 of, the output is ((A ₀ )-(A
-)). Since A ₀ is almost 0, this value is substantially the value obtained by reversing A-.

[0124]

As described above, according to the information reproducing apparatus of the present invention, the digital signal outputted from the analog-digital converting means is decoded by the maximum likelihood decoding corresponding to the amplitude value outputted from the amplitude estimating means. Therefore, the data can be accurately decoded. Further, since the output of the analog-to-digital conversion means is estimated by the amplitude estimation means, the amplitude estimation means can be configured digitally, and due to changes in temperature, humidity, etc., or secular changes, It is possible to prevent the reproduction characteristic from being deteriorated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an information reproducing apparatus of the present invention.

FIG. 2 is a diagram illustrating an output of the waveform equalization circuit 203 in FIG.

3 is a block diagram showing a configuration example of a level estimation circuit 32 in FIG.

FIG. 4 is a diagram illustrating a state in which the output signal of the waveform equalization circuit 203 in FIG. 1 has a DC component fluctuation.

5 is a block diagram showing another configuration example of the level estimation circuit 32 of FIG.

6 is a block diagram showing the configuration of still another embodiment of the level estimation circuit 32 of FIG.

7 is a block diagram showing the configuration of still another embodiment of the level estimation circuit 32 of FIG.

FIG. 8 is a block diagram illustrating partial response modulation.

FIG. 9 is a block diagram showing a configuration of a recording / reproducing system using a partial response.

FIG. 10 is a diagram showing a change in signal level.

FIG. 11 is a state transition diagram of a partial response PR (1, -1).

12 is a trellis diagram of the state transition diagram of FIG.

FIG. 13 is a diagram illustrating a Viterbi algorithm.

FIG. 14 is a decoder using the Viterbi algorithm.
It is a block diagram which shows the structure of an example.

15 is a shift register 1 of the decoder 116 of FIG.
21 is a block diagram showing a more detailed configuration of 21. FIG.

16 is a timing chart explaining the operation of the decoder 116 in FIG.

17 is a timing chart explaining the operation of the shift register 121 of FIG.

18 is a diagram for explaining changes in the amplitude of the reproduction signal input to the decoder 116 in FIG.

FIG. 19 is a block diagram showing a configuration of an example of a conventional information reproducing apparatus.

FIG. 20 is a block diagram showing another configuration example of a conventional information reproducing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 switching circuit 11 subtraction circuit 12a, 12b register 13 comparison circuit 14 switch 31 reproduction amplifier 32 level estimation circuit 41 comparison circuit 42 IIR filter 51 first estimation circuit 52 second estimation circuit 53 subtraction circuit 54 division circuit 61 comparison circuit 62 IIR filter 116 Decoder 201 AGC amplifier 202 A / D converter 203 Waveform equalization circuit 204 Amplitude detection circuit

Claims (7)

[Claims] 1. An information reproducing apparatus for reproducing from a recording medium predetermined recording data recorded on a recording medium by using a partial response system, wherein a signal level of a reproduced signal reproduced from the recording medium is converted into a digital signal. An analog-to-digital conversion means for estimating the amplitude value of the digital signal converted by the analog-to-digital conversion means and outputting the amplitude value; and a digital signal converted by the analog-to-digital conversion means from the amplitude estimation means. An information reproducing apparatus comprising: a decoding unit that performs maximum likelihood decoding in accordance with an output amplitude value. 2. The information reproducing apparatus according to claim 1, wherein the amplitude estimating means estimates at least one of positive and negative amplitude values of the digital signal. 3. The information reproducing apparatus according to claim 1, wherein the amplitude estimating means independently estimates a positive amplitude value and a negative amplitude value of the digital signal and outputs a difference value thereof. . 4. The information reproducing apparatus according to claim 1, wherein the amplitude estimating means independently estimates a positive amplitude value and a zero amplitude value of the digital signal and outputs a difference value thereof. . 5. The information reproducing apparatus according to claim 1, wherein the amplitude estimating means independently estimates an amplitude value of 0 and a negative amplitude value of the digital signal and outputs a difference value thereof. . 6. The information reproducing apparatus according to claim 1, wherein a partial response (1, -1) is used as a partial response modulation code. 7. A partial response class IV is used as a partial response type modulation code, and a partial response (1,
-1) The information reproducing apparatus according to any one of claims 1 to 5, wherein a pair of code reproducing circuits are used.