JPH06347520A - Delay test method - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the number of additional circuits dedicated to testing, to prevent an increase in flip-flop area, and to perform a high-performance delay test regardless of the value of the preceding circuit. [Structure] The master and slave of the front-stage flip-flop and the rear-stage flip-flop are simultaneously held in the hold mode,
The initial value of the delay test is set on each slave side, and the changed value is set on each master side. Next, in order to make only the latter stage flip-flop the same state as in actual operation,
After releasing the hold mode, a clock is input to the subsequent flip-flop after a predetermined time. As a result, "1" is latched if the path is normal, and "0" is latched if there is a delay defect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay test method for testing the delay time of an integrated circuit with high performance.

[0002]

2. Description of the Related Art Conventionally, there are two known methods for testing an integrated circuit, a parametric test and a functional test. Among them, the parametric test is a method for testing the performance of an integrated circuit input / output pin such as the voltage and current of an electronic circuit. The other functional test is a method for checking whether or not a false output value is output for a combination of input values applied to the integrated circuit. However, the latter method
Logical simulation in essence, and in order to perform this test, it is important to create a set of input values that can detect all possible failures in the integrated circuit.
However, recently, as integrated circuits have become larger in scale, it has become extremely difficult to create a combination of these input values. Therefore, in addition to the original operation circuit of the editing circuit (actual operation = actual operation), a circuit equipped with an additional circuit called a scan circuit for testing has appeared. This scan circuit is capable of setting and observing states of flip-flops inside the integrated circuit independently of those for actual operation. However, when a test is performed using this scan circuit, the test is performed from a path different from the actual operation, so a false operation that is different from the actual operation will be tested. Will essentially be impossible to test. Considering a failure in a logic circuit that causes a failure only in a test of actual operation timing, there is a failure in which a signal transmission time exceeds a specification allowable value, that is, a delay failure. Therefore, a method of inspecting this delay time by measuring the time of signal transfer between flip-flops has been considered.

2 and 3 are explanatory views of a conventional method for inspecting the delay time between flip-flops.
Is a configuration diagram thereof, and FIG. 3 is an operation time chart of the inspection method in the circuit of FIG. In FIG.
002 is a flip-flop, 2004 and 2005 are clock signals, and 2003 is a flip-flop 2001 data.
Data signal 1000 is an inspected path whose delay time is to be measured. When measuring the transfer time between the flip-flops 2001 and 2002, that is, the delay time of the inspected path 1000, the delay when the signal rises and the delay when the signal falls can be considered. First, regarding the rise time inspection, the scan circuit flips the flip-flop 200.
After setting the contents held in 1, 2002 to "0", the contents of the flip-flops in the preceding stage are set so that the data 2003 of the preceding-stage flip-flop 2001 becomes "1". Next, the clock 2 of the previous flip-flop 2001
The clock signal is added to 004 only once. at the time,
The content held in the flip-flop 2001 changes from "0" to "1", and the output signal of the preceding-stage flip-flop 2001 rises (see the output point of 2001 in FIG. 3). The rising signal reaches the data input of the post-stage flip-flop 2002 after the delay time of the inspected path 1000 has elapsed. Then, after a predetermined time has passed since the clock was applied to the front-stage flip-flop 2001, the rear-stage flip-flop 20
A clock signal is applied to the No. 02 clock 2005. At this time, if the path to be inspected is normal, the content of the front-stage flip-flop 2001 has reached the data input of the rear-stage flip-flop 2002, so the content of the rear-stage flip-flop 2002 is rewritten to '1'.

Next, when a defect with an increased delay time is detected in the path under test, for example, when the resistance in the path under test is changing, a signal is output until the clock is input to the subsequent flip-flop 2002. Since it has not arrived, the content of the subsequent flip-flop 2002 remains "0".
As a result, if the contents of the post-stage flip-flop 2002 are output by the scan circuit and the contents are examined, the path 100
A rising delay defect of 0 can be detected. Also,
Even when measuring the fall delay time, "0" is changed to "1".
You can measure in exactly the same way, just by replacing When the method of FIG. 2 is actually carried out, the problem is that the combination of input values applied to the integrated circuit (that is,
Since the number of test patterns is large, the number of steps and time for generating the test patterns is extremely large. Because, it is the front stage flip-flop 2001 of the inspection path.
This is because it is necessary to consider the value given to the data 2003 of. That is, the partial circuit targeted for generating the test pattern is the flip-flop 2001, 20
This is because it is necessary to consider not only the combination circuit including the path to be inspected surrounded by 02 or the input / output pins but also the combination circuit connected to the data of the previous stage flip-flop 2001. Then, as a method for solving this, for example, there is a method described in Japanese Patent Laid-Open No. 4-118570. 4 and 7 are configuration diagrams for realizing the conventional method described in the above publication. In FIG. 4, a test latch 4006 for providing a value to the data of the preceding flip-flop 4001 is provided. Further, in FIG. 7, the front-stage flip-flop 70
The inverted value of the output of 01 is returned to the data of the previous stage flip-flop 7001.

In FIG. 4, reference numerals 4001 and 4002 denote front and rear flip-flops incorporating an additional test circuit, 4003 an OR circuit, 4004 a NOT circuit, 4
005 is an AND circuit, 4006 is a test latch, 40
Reference numeral 07 is a scan address decoder, 4008 is a clock for actual operation, 4009 is a test mode pin, 4010 is a scan address, 4011 is scan data, 401
Reference numeral 2 is a scan clock for a test latch, 4013 is a scan clock for a flip-flop, and 4014 is abbreviated with a broken line, and an internal description is omitted, but it is a combinational circuit. FIG. 5 is a detailed block diagram of the flip-flop with a built-in test additional circuit in FIG.
FIG. 6 is a diagram showing a truth table of the flip-flop of FIG. 5. The front-stage flip-flop 5001 in FIG. 5 operates like the truth table shown in FIG. In FIG. 5, 5
002 is a test mode pin TM, which is set to "1" during the actual operation and set to "0" during the test. 5003
Is a clock CK for actual operation, 5004 is a scanning clock SC, 5005 is data D for actual operation, 5006 is data SD for scanning, and 5007 is an output Q of the flip-flop 5001. After all, the flip-flop 5001 of FIG. 5 fetches the data D by the clock CK during the actual operation of TM = '1', and scan data SD by the clock CK or the scan clock SC during the test of TM = '0'. Take in.

The procedure of the delay test in FIG. 4 will be described. First, in order to set initial values to the flip-flops 4001 and 4002, the scan address decoder 400
7. Scan clock 401 of test latch 4006
2. Using scan data 4011, a value is set in the test latch 4006 connected to the scan data pin of each flip-flop 4001, 4002. After that, the initial value of each flip-flop is set by using the scan clock 4013 of the flip-flops 4001 and 4002. Next, the scan address decoder 400
7. Using the scan clock 4012 and scan data 4011 of the test latch, the changed value is set in the test latch 4006 connected to the scan data pin of each required flip-flop 4001, 4002. Next, by using the scan address decoder 4007, only the TM of the post-stage flip-flop 4002 is set to "1".
, The normal operation mode is set, and the value of the test latch 4006 is set to the flip-flop. After that, the delay time is tested by applying the normal clock 4008.

Next, the operation of the method of returning the inverted value of the output value of the front-stage flip-flop to the data of the front-stage flip-flop will be described with reference to FIG. The configuration of FIG. 7 is different from that of FIG. 4 in that the test latch 4006 is omitted and that the flip-flop is composed of flip-flops 7001 and 7002 with an output value inverting function. FIG. 8 is a detailed configuration diagram of the flip-flop in FIG. The characteristic of the circuit of FIG. 8 is that when TM = '0', the flip-flop 5001 with an additional circuit outputs its own output value to the inverting circuit 40 by the clock of the normal clock 5003.
The value inverted in 04 is taken in. The delay test procedure in the circuit of FIG. 7 will be described. First, the flip-flops 7001 and 7002 are scanned by the scan address decoder.
This is designated by the data 4007 and initialized by using the scan clock 4013 and the scan data 4011. After this,
By designating the subsequent flip-flop 7002 by the scan address decoder 4007, TM of the flip-flop 7002 becomes "1" and other flip-flops become "0". Next, by applying the actual operation clock 4008, a change signal is generated and a delay test is performed.

[0008]

As described above, as a conventional delay test method, there are methods shown in FIGS. 4 and 7. However, the method of providing the test latch as shown in FIG. 4 has a problem that the area of the flip-flop becomes large because the latch is required for the additional circuit. That is, even if the additional circuits other than the latch are ignored for simplification, if the flip-flop body is a D-type master slave flip-flop, the area of the added test latch is about 1 of the master slave flip-flop.
Therefore, the number of logic circuits mounted on the integrated circuit needs to be reduced. On the other hand, as shown in FIG.
The method of returning the inverted value of the output of the front-stage flip-flop as the data of the front-stage flip-flop causes a problem in the performance of the delay test. FIG. 9 is a diagram showing an example of a circuit in which the delay test cannot be performed, and FIG. 10 is an operation time chart of FIG. In FIG. 9, 9001, 9002, 90
Reference numeral 03 denotes a front-stage flip-flop of FIG. 7, that is, a flip-flop 900 provided with an additional circuit for returning the inverted value of the output of the front-stage flip-flop to the data of the front-stage flip-flop, 900
Reference numeral 4 is an OR circuit, 9012, 9014 and 9018 are outputs of flip-flops, and 9010 and 9011 are separate clocks. Here, the delay time of the signal rising from the front stage flip-flop 9001 to the rear stage flip-flop 9002 is tested. First, each flip-flop 9001 to 9003 is set to "0", and the subsequent flip-flop 9002 is designated by the scan address decoder (not shown). At this point (timing T0 in FIG. 10), all signals except the clock are low level. Next, when the clock 9010 is applied, the outputs 9012 and 901 of the preceding flip-flops 9001 and 9003 are output.
4 is inverted to "1" (timing T1). The output signals of the preceding flip-flop 9001 are 9012 to 901.
Due to the delay time required up to 3, the input point 9013 of the OR circuit 9004 arrives at the timing T2. Also, the output signals of the front-stage flip-flop 9003 are 9014 to 9014.
Due to the delay time up to 015, the input point 9015 of the OR circuit 9004 is reached at the timing T3. As a result, OR
The output 9016 of the circuit 9004 has a signal rising at timing T2. Thereafter, due to the delay time from the OR circuit output 9016 to the input 9017 of the post-stage flip-flop 9002, the signal reaches the post-stage flip-flop 9002 at the timing T4. Clock 9 for delay test
Clock 90 at timing T6 after a specified time from 010
When 11 is applied, the output 9018 of the post-stage flip-flop 9002 becomes "1", so the test passes.

Next, consider a case where the delay time from the output 9012 of the preceding flip-flop 9001 to the input 9013 of the OR circuit becomes large and a defect occurs. In this case, if the operation in the same process as described above is performed, O in FIG.
The waveform of the input point 9013 of the R circuit should rise at T2, but it rises at T7 because of an abnormal delay. However, since the waveform of the other input point 9015 of the OR circuit is normal operation, it rises at T3, and O
Since the output of the R circuit 9004 is determined by the earlier input, the output 9016 rises at T3. As a result, the waveform of the input point 9017 of the post-stage flip-flop 9002 rises at T5. Therefore, when the clock 9011 is applied at the timing T6, the output value of the post-stage flip-flop 9002 becomes "1", and therefore the inspection passes. This is the delay time from the output point 9012 of the preceding flip-flop 9001 to the OR circuit input point 9013 and the output time 9014 of the preceding flip-flop 9003 to the OR circuit input point 901.
This is because the difference from the delay time up to 5 is small, and therefore the clock cannot be inserted at the timing between T4 and T5 in terms of test accuracy. In this way, in the test of the integrated circuit alone, if it passes even though there is a defect in the circuit, the defect will not be detected before the shipment inspection of the device, so a failure will occur after actual operation, and it will be discovered. It takes time and labor, and there is a problem that the cost for replacing the integrated circuit is high. An object of the present invention is to solve such a conventional problem, delay the performance of the delay test without adding an additional circuit such as a test latch, and delay without increasing the area of the flip-flop. It is to provide a delay test method capable of performing a test.

[0010]

In order to achieve the above object, the delay test method of the present invention comprises a plurality of sets of master slaves.
A flip-flop circuit (1100, 1200) and a scan circuit (1
In the delay test method of the integrated circuit having the (001) mounted therein, the scan circuit (1001) is connected to the master side of the master slave flip-flops (1100, 1200) and the slave side.
Independent test data are stored in the master side and are held independently, so that the master side (1101, 12) of the master slave flip-flops in the front and rear stages is stored.
01) and then reset both the slave side (1102, 1202) of the front-stage and rear-stage flip-flops to perform initial setting, and then set the master side (1101) of the front-stage flip-flop. To set the value after the change, and only the flip-flop (1200) in the latter stage
After releasing the lock state, the previous flip-flop (11
The clock (1111) is applied to 00) and then the clock (1211) is applied to the post-stage flip-flop (1200) after a predetermined time, so that the output of the post-stage flip-flop is observed.

[0011]

In the present invention, both the master and the slave of each master slave flip-flop can be simultaneously put in the HOLD mode, and the delay test is performed on each slave flip-flop. In addition to setting the initial value for, the changed value can be set in each master flip-flop. Also, only the post-stage flip-flop can be in the same state as in actual operation,
Thereby, the changed value can be arbitrarily set for each flip-flop. For this purpose, a scan circuit for holding the master flip-flop independently of the clock for actual operation and a scan circuit for setting independent values to the master and slave flip-flops are provided.
As a result, it becomes possible to perform the delay test equivalent to the test method using the test latch without increasing the flip-flop area by making the additional circuit such as the test latch unnecessary.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a basic structural diagram of a delay test circuit showing an embodiment of the present invention. In FIG. 1, 1001 is a scan circuit, 1100 and 1200 are master flip-flop hold type D-type master slave flip-flops, 1101 and 1201 are master flip-flops, and 1102 and 1202 are slave flip-flops.
1103 and 1203 are NOT circuits, and 1105 and 1205.
Is data (D), 1106 and 1206 are master flip-flop set signals (MS), 1107 and 1207 are master flip-flop reset signals (MR), 11
08 and 1208 are set signals (SS) for the slave flip-flops, 1109 and 1209 are reset signals (SR) for the slave flip-flops, and 1110 and 1210 are control signals (for holding the master flip-flop in the hold mode). MCH), 1111 and 1211 are clocks (C
K), 1104 and 1204 are OR circuits, 1112 and 12
12 is the output (Q) of the master slave flip-flop,
Reference numeral 1000 is a route for which a delay test is desired. Here, the master slave flip-flops 1100 and 120
When 0 is the high level clock (CK) during actual operation, the master side is the through side, and the slave side is the hold.

In FIG. 1, when the rise delay test of the path 1000 is performed, first, the hold mode control signal (MC) of all the flip-flops 1100 and 1200 is used.
H) is set to low level and the master flip-flop 11
Hold 01, 1201. Next, the scan circuit 1001 uses the reset signal 1109 (SR) to reset the slave side 1102 of the front-stage flip-flop 1100 and set it to "0". Similarly, the reset signal 1209 (S
R) is used to reset the slave side 1202 to "0".
Set (default setting). Next, the master flip-flop 1101 of the front-stage flip-flop 1100 is set to "1" using the set signal 1106, and the changed value is set. Then, the rear flip-flop 1200
Only the control mode control signal 1210 (MCH) is returned (released) to the high level, and the actual operation state is set. Here, since the clock is applied to the flip-flop 1101 by inputting the clock 1111 (CK) to the preceding flip-flop, the content “1” of the master flip-flop 1101 is output and the slave flip-flop 110 is output.
Transferred to 2. At the same time, the front-stage flip-flop 110
The output of 0 is inverted ('1') and is transmitted through the path 1000. The master flip-flops 1101 and 1201
AND circuit 1 connected to the clock input (CK) of
104 is actually a two-stage connection N as shown in FIG.
It is composed of an AND circuit, and the hold mode control signal 1210 (MCH) is input to the subsequent NAND circuit. Therefore, in FIG. 1, the hold state continues even after the clock input, and the data input 1105 (D)
It becomes irrelevant to the state of. This is an important function in the operation of the present invention. The inverted signal is the measured path 100.
After passing 0, the delay test can be performed by reaching the subsequent flip-flop 1200 and inputting the clock 1211 (CK) after a predetermined time.

FIG. 11 is an operation time chart of the present invention according to FIG. 9 and 11 illustrate that the present invention can be tested without degrading the performance of the delay test. Now, flip-flops 9001, 9002 and 9003 in FIG. 9 are assumed to be composed of master flip-flops 1101 and 1201 and slave flip-flops 1201 and 1202 like flip-flops 1100 and 1200 in FIG. Now, the delay time of the signal rising from the front stage flip-flop 9001 to the rear stage flip-flop 9002 is tested. First, the master flip-flop is held, and "0" is set on the slave side of each flip-flop. Next, after the inverted value “1” is set on the master side of the front-stage flip-flop 9001, the front-stage flip-flop 9
'0' is set on the master side of 003 so that the value is fixed. Next, the hold of the second-stage flip-flop 9002 is released. The waveform at timing T0 in FIG. 11 is the signal of each part at this time. Next, when the clock 9010 is input to the preceding flip-flops 9001 and 9003, the output 9012 of the flip-flop 9001 is inverted to “1”. On the other hand, the output 9014 of the flip-flop 9003 is "0" as shown at the timing T1.
It remains fixed to. That is, the operation of the present invention is characterized in that 9001 of the preceding flip-flops is in the "10" state, whereas 9003 is "00".
Is to be in the state of.

The output signal of the flip-flop 9001 has an input point 901 of the OR circuit 9004 at timing T2 due to the delay time from the output 9012 to the input 9013.
Reach 3. As a result, the output point 9 of the OR circuit 9004
At 016, the signal rises at the timing T2. Thereafter, due to the delay time from the output 9016 to the input 9017, the signal is output at the subsequent flip-flop 90 at the timing T4.
Reach 02. At this point, the rear flip-flop 9
Since the output 9018 of 002 becomes '1', the test passes. Next, the output 90 of the flip-flop 9001
A case where the delay from 12 to the input 9013 of the OR circuit 9004 is abnormally large and the path is defective will be described. In this case, by performing the same operation as above, the waveform of the input 9013 point should rise at the timing T2, but the rising point of the output 9012 rises at the timing T7 due to an abnormal delay of the path. As a result, the waveform at the input 9017 points of the post-stage flip-flop 9002 is
It will rise at timing T8. Therefore, even if the clock 9011 is input at the timing T6 after the stipulated time, the value at the output 9018 point of the post-stage flip-flop 9002 becomes “0”. In this case, the normal value (expected value)
And the test fails.

FIG. 12 is a block diagram showing the details of the scan circuit in FIG. In FIG. 12, 1100,1
Reference numeral 200 designates a D-type master slave flip-flop 110 with a master flip-flop hold mode in FIG.
0, 1200, and the other circuits show the detailed configuration of the scan circuit 1001 in FIG. That is, 40
14 is a combinational circuit, 4008 is a clock, 4010 is a scan address, and 4007 is a scan address decoder.
And can be independently addressed to each of the master and slave sides of the master slave flip-flop. Reference numeral 4011 denotes scan data (S
D), 4013 are scan clocks (SC), 1200
3 is a set / reset signal generation circuit, 12001 is a hold mode signal (HOLD), 12002 is a test mode signal (TEST), 12004 is a master flip-flop hold signal generation circuit, and the AND circuit 1 of FIG.
Equivalent to 104. The procedure of the delay test in FIG. 12 will be described below. First, a hold mode signal 12001
To "1" and the test mode signal 12002 to "0"
Further, the outputs of all master flip-flop hold signal generation circuits 12004 are set to "0". As described with reference to FIG. 1, when the hold mode signal (MCH) of the flip-flops becomes "0", the master flip-flops are held and all the flip-flops are in the hold state.

Next, the scan address decoder 4007
Is used to select the slave side of each flip-flop 1100, 1200. At the same time, scan data (SD) 4
By inputting 011 and the scan clock (SC) 4013 to the set / reset generation circuit 12003, a set signal or a reset signal is generated and an initial value of the delay test is written. Here, "0" is set on the slave side.
It is initialized by writing. Further, the scan address decoder 4007 is used to select the master side of each flip-flop 1100, 1200, and the changed value is written. Here, scan data (SD) 4011
By inputting "1" to the scan clock (SC) 4013, "1" is written to the master side. And
The post-stage flip-flop 1200 is selected by using the scan address decoder 4007. Here, when the master side of the post-stage flip-flop 1200 is selected and the test signal 12002 is set to “1”, only the output of the master flip-flop hold signal generation circuit 12004 connected to the post-stage flip-flop 1200 is set to “1”. ', And only this flip-flop becomes the same as the actual operating state. The delay test can be performed by inputting the clock 4008 after performing the above setting.

FIG. 13 is a block diagram of a flip-flop showing a modification of FIG. That is, FIG. 13 shows an example in which the set-reset circuit is removed from the slave side of the D-type master slave flip-flop with master flip-flop hold mode shown in FIG. That is, since the slave set signal (SS) 1108 and the slave reset signal (SR) 1109 in FIG. 1 are unnecessary,
The scan circuit 1001 is simplified. Where 130
Reference numeral 01 is a master slave flip-flop, 1101 is a master flip-flop, 13002 is a slave flip-flop, and the other circuits are the same as in FIG. According to this circuit, since the scan address on the slave side is unnecessary, the shape of the scan address decoder 4007 can be reduced. In this case, the procedure for setting the initial value is changed as follows. That is, the thread
Since the value cannot be set directly in the flip-flop, the initial value is first set on the master side and the clock is input. As a result, the value is transferred to the slave side. Then, the changed value is set on the master side. Below that, a test is performed using the procedure described in FIGS. When the master slave flip-flops and the D latches coexist, the delay test can be similarly performed by adding the test latch 4006 in FIG. 4 to the D latch.

[0019]

As described above, according to the present invention,
In the delay test of the path whose both ends are flip-flops, the logic of the previous stage can be ignored and the change signal can be created in the previous stage flip-flop by using the clock for actual operation without adding the test latch. Since the signal for the actual operation clock can be stored in the post-stage flip-flop, it is possible to perform the delay test with high performance without increasing the area of the flip-flop by the additional circuit dedicated to the test.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a delay test circuit showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining a conventional delay test.

FIG. 3 is an operation time chart of FIG.

FIG. 4 is a configuration diagram of a conventional delay test circuit (No. 1).

5 is a diagram showing a structure of a flip-flop used in the circuit of FIG.

6 is a diagram showing a truth table of the flip-flop shown in FIG. 5;

FIG. 7 is a configuration diagram of a conventional delay test circuit (No. 2).

8 is a diagram showing a structure of a flip-flop used in the circuit of FIG.

9 is a configuration diagram for explaining a problem of the circuit of FIG. 7. FIG.

10 is an operation time chart of the circuit in FIG.

FIG. 11 is an operation time chart in the circuit of the present invention (FIG. 1).

12 is a diagram showing details of a scan circuit in the delay test circuit of FIG.

13 is a configuration diagram showing a modification of the delay test circuit of FIG.

[Explanation of symbols]

1100, 1200 Master flip-flop Hold type D-type master slave flip-flop 1101, 1201 Master flip-flop 1102, 1202 Slave flip-flop 1103, 1203 NOT circuit 1105, 1205 Data (D) 1106, 1206 Master Flip-flop set signal (MS) 1107, 1207 Master flip-flop reset signal (MR) 1108, 1208 Slave flip-flop set signal (SS) 1109, 1209 Slave reset signal (SR) 1110, 1210 Master Control signal (MCH) 1000 for holding the flip-flop in the hold mode 1000 Path to be subjected to delay test 1001 Scan circuit 1111, 1211 Clock (CK) 1104, 1204 R circuit 1112, 1212 Output of master slave flip-flop (Q) 2001, 2002 Flip-flop 2003 Data signal of flip-flop 2001 2004, 2005 Clock signal 4001 Pre-stage side of flip-flop with built-in additional circuit 4002 For test Rear side of flip-flop with built-in additional circuit 4003 OR circuit 4004 NOT circuit 4005 AND circuit 4006 Test latch 4007 Scan address decoder 4008 Clock in actual operation 4009 Test mode pin 4010 Scan address 4011 Scan data 4012 Test latch Scan clock 4013 Flip-flop scan clock 4014 Combination circuit 9001, 9002, 9003 Flip-flop 004 OR circuit 9012, 9014, 9018 Output point of flip-flop 9013, 9015 Input point of OR circuit 9016 Output point of OR circuit 9010, 9011 Clock 12001 Hold mode signal 12002 Test mode signal 12003 Set reset signal generation circuit 12004 Master flip-flop hold signal generation circuit 13001 Master slave flip-flop 13002 Slave flip-flop

Claims (1)

[Claims] 1. A delay test method for an integrated circuit comprising a plurality of sets of master-slave flip-flop circuits and a scan circuit for scanning the flip-flop circuits, wherein the scan circuit comprises a master side and a slave side of the master-slave flip-flop. -Independent test data is stored on the slave side and held independently, and after holding the master side of the master slave flip-flops of the front stage and the rear stage, the next stage and The slave side of the latter-stage flip-flop is reset together to perform the initial setting, then the master side of the former-stage flip-flop is set to set the changed value, and the hold state of only the latter-stage flip-flop is released. After applying the clock to the front-stage flip-flop, the clock is applied to the rear-stage flip-flop after a predetermined time. A delay test method characterized by observing the output of a post-stage flip-flop by applying.