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JPH0634431B2 - Ceramics circuit board - Google Patents

Ceramics circuit board

Info

Publication number
JPH0634431B2
JPH0634431B2 JP62189953A JP18995387A JPH0634431B2 JP H0634431 B2 JPH0634431 B2 JP H0634431B2 JP 62189953 A JP62189953 A JP 62189953A JP 18995387 A JP18995387 A JP 18995387A JP H0634431 B2 JPH0634431 B2 JP H0634431B2
Authority
JP
Japan
Prior art keywords
circuit board
corner
ceramic
copper plate
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62189953A
Other languages
Japanese (ja)
Other versions
JPS6433989A (en
Inventor
信幸 水野谷
裕 小森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP62189953A priority Critical patent/JPH0634431B2/en
Publication of JPS6433989A publication Critical patent/JPS6433989A/en
Publication of JPH0634431B2 publication Critical patent/JPH0634431B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass

Landscapes

  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、セラミックス基板に銅板を直接接合してなる
セラミックス回路基板に関する。
DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a ceramic circuit board obtained by directly bonding a copper plate to a ceramic substrate.

(従来の技術) 近年、パワートランスモジュール用基板やスイッチング
電源モジュール用基板等の回路基板として、セラミック
ス基板上に銅板等の金属板を接合させたものがよく用い
られている。
(Prior Art) In recent years, as a circuit board such as a board for a power transformer module or a board for a switching power supply module, a board in which a metal plate such as a copper plate is bonded to a ceramic substrate is often used.

このようなセラミックス回路基板の製造方法として、所
定形状な打ち抜かれた銅回路板を、例えば酸化アルミニ
ウム焼結体や窒化アルミニウム焼結体からなるセラミッ
クス基板上に接触配置させて加熱し、接合界面にCu- Cu
Oの共晶液相を生成させ、この液相によりセラミック
ス基板の表面を濡らし、次いで冷却固化してセラミック
ス基板と銅回路板とを直接接合させる、いわゆるDBC
法(ダイレクト・ボンディグ・カッパー法)が多用され
るようになってきている。
As a method of manufacturing such a ceramics circuit board, a punched copper circuit board having a predetermined shape is placed in contact with a ceramics board made of, for example, an aluminum oxide sintered body or an aluminum nitride sintered body, and heated to form a bonding interface. Cu- Cu
A so-called DBC in which a eutectic liquid phase of 2 O is generated, the surface of a ceramic substrate is wetted by this liquid phase, and then cooled and solidified to directly bond the ceramic substrate and the copper circuit board.
The method (direct bondig copper method) is becoming popular.

このDBC法により形成されたセラミックス回路基板
は、セラミックス基板と銅回路板との接合強度が強く、
単純構造なので小型高実装化が可能であり、また作業工
程も短縮できる等の長所を有している。
The ceramic circuit board formed by the DBC method has a strong bonding strength between the ceramic board and the copper circuit board,
Since it has a simple structure, it can be miniaturized and highly packaged, and it has the advantage that the work process can be shortened.

(発明が解決しようとする問題点) ところで、このようなセラミックツ回路基板に使用する
セラミックス基板は、通常、矩形で各角部をそのままの
形状で使用しているので、加熱処理時やモジュールの実
装等の自動組立て時に搬送ラインにおける搬送レール等
にひっかかり欠けが生じる等、不良の発生率が高いとい
う問題があった。また、場合によってはこれより搬送ラ
インが停止してしまうという問題も発生している。
(Problems to be Solved by the Invention) By the way, since the ceramics substrate used for such a ceramics circuit board is usually rectangular and each corner is used as it is, the ceramics substrate is not used during the heat treatment or the module. There has been a problem that the occurrence rate of defects is high, such as a catch on a carrying rail or the like in a carrying line during the automatic assembly such as mounting and chipping. Further, in some cases, there is a problem that the transportation line is stopped due to this.

本発明はこのような従来の問題点を解決するためになさ
れたもので、各工程における搬送がスムーズに行え、不
良発生率の少ないセラミックス回路基板を提供すること
を目的とする。
The present invention has been made to solve such conventional problems, and an object of the present invention is to provide a ceramics circuit board that can be smoothly transported in each step and has a low failure rate.

[発明の構成] (問題点を解決するための手段) 本発明のセラミックス回路基板は、セラミックス基板上
に所定の形状の銅板を配置し加熱接合してなるセラミッ
クス回路基板において、前記セラミックス基板の各角部
が面取りされていると共に、前記セラミックス基板の各
角部に対応する銅板の各角部も面取りされていることを
特徴としている。
[Structure of the Invention] (Means for Solving Problems) A ceramic circuit board of the present invention is a ceramic circuit board in which a copper plate having a predetermined shape is arranged on a ceramic substrate and heat-bonded to each other. The corners are chamfered, and the corners of the copper plate corresponding to the corners of the ceramic substrate are also chamfered.

本発明に使用するセラミックス基板としては、アルミ
ナ、ベリリア等の酸化物系のセラミックス焼結体や窒化
アルミニウム、窒化ケイ素、窒化チタン、酸化ケイ素等
の非酸化系のセラミックス焼結体等からなるセラミック
ス基板が挙げられる。なお非酸化物系のセラミック基板
を使用する場合には、予め接合表面を酸化処理してから
使用することが好ましい。
The ceramics substrate used in the present invention includes an oxide-based ceramics sintered body such as alumina and beryllia or a non-oxidized ceramics sintered body such as aluminum nitride, silicon nitride, titanium nitride and silicon oxide. Is mentioned. When a non-oxide type ceramic substrate is used, it is preferable to oxidize the bonding surfaces before use.

そして、これらセラミックス基板は、各角部に予め面取
りを施して使用する。この面取りはC面加工でもR加工
でもよく、このC面加工またはR加工の大きさは 0.1〜
1.0mmの範囲が好ましい。C面加工またはR加工の大き
さが 0.1mm未満ではかけ防止の効果が十分に得られず、
1.0mmを超えてもそれ以上の効果が得られないばかり
か、 セラミックス基板の各角部に面取りを施すと、セ
ラミックス基板の角部から接合する銅板までの距離が短
くなって耐電圧が不足するため、使用する銅板の大きさ
を小さくする必要が生じ、部品搭載面積が減少し好まし
くない。
Then, these ceramic substrates are used by chamfering each corner in advance. This chamfering may be C surface processing or R processing, and the size of this C surface processing or R processing is 0.1 ~
A range of 1.0 mm is preferred. If the size of the C surface processing or R processing is less than 0.1 mm, the effect of preventing crossing cannot be sufficiently obtained,
Even if it exceeds 1.0 mm, it is not possible to obtain any further effect, and if chamfering is applied to each corner of the ceramic substrate, the distance from the corner of the ceramic substrate to the copper plate to be bonded becomes short and the withstand voltage becomes insufficient. Therefore, it is necessary to reduce the size of the copper plate used, which is not preferable because the component mounting area is reduced.

本発明では、使用する銅板の大きさを小さくせずに必要
な耐電圧を維持するために、セラミックス基板の各角部
に対応する銅板の各角部にも面取りを施している。銅板
角部の面取り形状は、セラミックス基板と同形状とする
ことが好ましい。
In the present invention, each corner of the copper plate corresponding to each corner of the ceramic substrate is chamfered in order to maintain the required withstand voltage without reducing the size of the copper plate used. The chamfered shape of the corner of the copper plate is preferably the same as the ceramic substrate.

本発明に使用する銅板としては、タフピッチ銅のように
酸素を 100〜3000ppm の割合で含有する銅を圧延してな
るものが好ましい。
The copper plate used in the present invention is preferably a copper plate obtained by rolling copper containing oxygen in a proportion of 100 to 3000 ppm, such as tough pitch copper.

本発明のセラミックス回路基板は、予め各角部の面取り
を施したセラミックス基板上に銅板を接触配置させ、加
熱することにより得られる。この加熱温度は、銅の融点
(1083℃)以下で銅と酸素の共晶温度(1065℃)以上で
ある。また、酸素を含有する銅板を使用する場合は、不
活性ガス雰囲気中で加熱を行うことが好ましく、酸素を
含有しない銅板を使用する場合は、80〜3900ppm の酸素
含有雰囲気中で加熱を行うことが好ましい。
The ceramics circuit board of the present invention can be obtained by placing a copper plate in contact with a ceramics substrate whose corners have been chamfered in advance and heating it. The heating temperature is below the melting point of copper (1083 ° C) and above the eutectic temperature of copper and oxygen (1065 ° C). When using a copper plate containing oxygen, it is preferable to heat it in an inert gas atmosphere, and when using a copper plate that does not contain oxygen, heat it in an atmosphere containing oxygen of 80 to 3900 ppm. Is preferred.

(作 用) 本発明のセラミックス回路基板において、予め各角部に
面取りを施したセラミックス基板を使用しているので、
加熱処理工程や部品実装工程における搬送がスムーズに
行え、角部の破損による不良の発生が著しく減少する。
(Operation) In the ceramics circuit board of the present invention, since the ceramics board in which each corner is chamfered in advance is used,
Transport in the heat treatment process and component mounting process can be performed smoothly, and the occurrence of defects due to breakage of corners is significantly reduced.

(実施例) 次に、本発明の実施例について説明する。(Example) Next, the Example of this invention is described.

実施例 まぜ、第1図に示すように、50mm×25mm×0.635mmのア
ルミナを主成分(96%、他に4%の焼結助剤を含む)と
するセラミックス基板1の各角部1a、1a…に 0.5C
でC面加工を施したものを使用し、その上にセラミック
ス基板1の各角部1a、1a…に対応する各角部2a、
2a…に 0.3C のC面加工を同様施した所定の形状の銅
板2を接触配置し、窒素ガス雰囲気中で1070℃の温度で
10分間加熱し接合させた。
Example As shown in FIG. 1, each corner 1a of a ceramic substrate 1 containing alumina of 50 mm × 25 mm × 0.635 mm as a main component (96% and containing a sintering additive of 4% in addition), 0.5C for 1a ...
Used for the C surface processing, on which the corners 2a corresponding to the corners 1a, 1a ...
A copper plate 2 of a predetermined shape, which has been similarly subjected to C-face machining of 0.3C, is placed in contact with 2a ... and at a temperature of 1070 ° C. in a nitrogen gas atmosphere.
It was heated and bonded for 10 minutes.

このようにして得たセラミックス回路基板は、自動工程
での搬送トラブルの発生率は0.01%以下であった。ま
た、耐電圧も十分に満足するものであった。
In the ceramic circuit board thus obtained, the occurrence rate of transport trouble in the automatic process was 0.01% or less. Moreover, the withstand voltage was also sufficiently satisfied.

一方、本発明との比較のため、実施例におけるセラミッ
クス基板の各角部の面取りを行わない以外は同様にして
作製したセラミックス回路基板の場合は、搬送トラブル
の発生率が 0.1%であった。
On the other hand, for comparison with the present invention, in the case of the ceramic circuit board manufactured in the same manner except that the chamfering at each corner of the ceramic board in the example was not performed, the occurrence rate of the transport trouble was 0.1%.

実施例2 第2図に示すように、実施例1におけるセラミックス基
板1の各角部1a、1a…にC面加工を施す代りに、
0.5R のR加工を施したものを使用し、同様に銅板2の
セラミックス基板1の各角部1a、1a…に対応する各
角部2a、2a…にも0.3R のR加工を施したものを使
用する以外は、実施例1と同一条件でセラミックス回路
基板を作製した。
Example 2 As shown in FIG. 2, instead of performing C-face processing on each corner 1a, 1a ... Of the ceramic substrate 1 in Example 1,
A 0.5R rounded R is used, and a 0.3R rounded is also applied to each corner 2a, 2a ... Corresponding to each corner 1a, 1a ... Of the ceramic substrate 1 of the copper plate 2. A ceramic circuit board was produced under the same conditions as in Example 1 except that

このようなセラミックス回路基板においても、実施例1
と同様な効果が得られた。
Also in such a ceramic circuit board, Example 1
The same effect as was obtained.

[発明の効果] 以上説明したように本発明のセラミックス回路基板は、
各角部に予め面取りを施したセラミックス基板を使用し
ているので、搬送時のトラブルが減り、欠け等の不良の
発生率が大幅に減少する。
[Effects of the Invention] As described above, the ceramic circuit board of the present invention is
Since the ceramic substrate with chamfered edges is used in advance, troubles during transportation are reduced, and the incidence of defects such as chipping is greatly reduced.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例のセラミックス回路基板を示
す平面図、第2図は本発明の他の実施例のセラミックス
回路基板を示す平面図である。 1……セラミックス基板 1a……角部 2……銅板 2a……角部
FIG. 1 is a plan view showing a ceramics circuit board according to an embodiment of the present invention, and FIG. 2 is a plan view showing a ceramics circuit board according to another embodiment of the present invention. 1 ... ceramic substrate 1a ... corner 2 ... copper plate 2a ... corner

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】セラミックス基板上に所定の形状の銅板を
配置し加熱接合したなるセラミックス回路基板におい
て、 前記セラミックス基板の各角部が面取りされていると共
に、前記セラミックス基板の各角部に対応する銅板の各
角部も面取りされていることを特徴とするセラミックス
回路基板。
1. A ceramic circuit board comprising a ceramic board on which a copper plate having a predetermined shape is arranged and heat-bonded, and each corner portion of the ceramic substrate is chamfered and corresponds to each corner portion of the ceramic substrate. Ceramic circuit board characterized in that each corner of the copper plate is also chamfered.
【請求項2】セラミックス基板の各角部に対応する銅板
の各角部が、前記セラミックス基板の各角部と同形状に
面取りされている特許請求の範囲第1項記載のセラミッ
クス回路基板。
2. The ceramic circuit board according to claim 1, wherein each corner of the copper plate corresponding to each corner of the ceramic substrate is chamfered in the same shape as each corner of the ceramic substrate.
【請求項3】面取りの大きさが、 0.1〜 1.0mmの範囲で
ある特許請求の範囲第1項または第2項記載のセラミッ
クス回路基板。
3. The ceramic circuit board according to claim 1 or 2, wherein the chamfer has a size in the range of 0.1 to 1.0 mm.
JP62189953A 1987-07-29 1987-07-29 Ceramics circuit board Expired - Lifetime JPH0634431B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189953A JPH0634431B2 (en) 1987-07-29 1987-07-29 Ceramics circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189953A JPH0634431B2 (en) 1987-07-29 1987-07-29 Ceramics circuit board

Publications (2)

Publication Number Publication Date
JPS6433989A JPS6433989A (en) 1989-02-03
JPH0634431B2 true JPH0634431B2 (en) 1994-05-02

Family

ID=16249959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189953A Expired - Lifetime JPH0634431B2 (en) 1987-07-29 1987-07-29 Ceramics circuit board

Country Status (1)

Country Link
JP (1) JPH0634431B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013232620A (en) 2012-01-27 2013-11-14 Rohm Co Ltd Chip component
JP6626135B2 (en) * 2012-01-27 2019-12-25 ローム株式会社 Chip components

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181060U (en) * 1981-05-14 1982-11-17
JPS6066061U (en) * 1983-10-12 1985-05-10 日本電気株式会社 ceramic substrate
JPS62147526A (en) * 1985-12-23 1987-07-01 Nec Corp Multiplier

Also Published As

Publication number Publication date
JPS6433989A (en) 1989-02-03

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