JPH06337791A - Program converting device and processor - Google Patents

Abstract

PURPOSE:To provide a compiler and a microcomputer which are suitable for application requiring an address space having 16 bits in data bit width and about 16 megabytes. CONSTITUTION:In the program converting device, a code generation part 7 generates an instruction which makes the bit width of data held by a parameter holding means, effective by instructions from a memory control part 9, a register control part 10, and an instantaneous value control part 11 when a variable used by a machine word instruction to be generated is a variable showing data. When the variable is a variable showing an address, a parameter setting part 8 generates an instruction for making the bit width of the held address effective. The microcomputer can utilize the address space of the value obtained by raising 2 to the (N)th power (16 Mbyte) by a program counter with N(24)-bit length, and a executing means performs arithmetic with N(24)-bit length and arithmetic with M(16)-bit length equal to the bit width of the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program conversion device for converting a high level language program into a machine language program, and
The present invention relates to a processor that executes the machine language program.

[0002]

2. Description of the Related Art With the recent development of electronic technology, information processing devices such as microprocessors have become widespread and used in all fields. . As a conventional processor, for example, Izumi Morishita, "Hardware of Microprocessor"
(November 9, 1984, Iwanami Shoten),
There is a segment addressing 16-bit processor.

This segment address type 16-bit processor is provided with a segment register for storing a high-order address including bits higher than 16 bits, so that the bit width of data is 16 bits, but is 6 bits.
It can handle address spaces larger than 4 kilobytes. That is, the entire address space exceeding 64 kilobytes is divided into 64 kilobyte units called segments, and each segment is numbered. The address is managed by the segment number stored in the segment register and the distance (offset) from the beginning of the segment represented by 16 bits which is the same as the bit width of the data. As a result, in a segment address type 16-bit processor, the bit width of data is 16 bits and 6 bits.
It can handle address spaces larger than 4 kilobytes.

As a conventional processor, there is a 32-bit processor shown in the same document. The 32-bit processor can manage a 32-bit width address in the same manner as a 32-bit width data and handle a 4-gigabyte address space. A machine language program executed on such a processor is generated by a program conversion device such as a compiler.

Regarding the address management system, the compiler for the 16-bit processor is classified into a large model system and a near-far model system. A compiler adopting the large model method always sets a pointer variable in pairs with a segment register and a 16-bit offset. For this reason, the processor that executes the object code by this compiler needs to calculate and update the contents of the segment register every time the address is calculated, and the performance is significantly deteriorated as compared with the 16-bit processor that does not adopt the segment address method. It has the disadvantage of

Further, the compiler adopting the near-far model method solves the above disadvantages of the large-model method as follows. In this method, two types of pointer variables can be designated: a near pointer variable for accessing the same segment and a far pointer variable for accessing across a segment boundary. The compiler uses 16 for near pointer variables
Only the bit offset is set, and the far pointer variable is set by pairing the segment register and the 16-bit offset. The programmer selects whether to use the near pointer variable or the far pointer variable.

In this near-far model method, the performance is improved in the case of using the near pointer variable as compared with the large model method, but it is necessary for the programmer to recognize the segment boundary at the time of program creation and properly use two kinds of pointer variables. However, there is a new problem that the program development efficiency is significantly reduced. On the other hand, compilers for 32-bit processors do not have the above problems. That is, since the compiler sets a 32-bit address to a pointer variable as well as a 32-bit data variable, the programmer does not need to recognize the segment boundary, and therefore the program development efficiency is not reduced. In addition, the processor that executes the compiled program does not suffer performance degradation due to address calculation. It can handle a vast address space of 4 gigabytes.

[0008]

However, according to the processor and the program conversion device of the prior art, the data width of 32 bits is not required in the application (application) in the microcomputer for the embedded use, and 4 Most do not require a gigabyte of address space. In many applications,
16 bits is sufficient for the data width, but 64 kilobytes is insufficient for the address space. In view of such a current situation, in an application that requires a data bit width of 16 bits and an address space of 64 kilobytes or more, but does not require a size of 4 gigabytes, an optimum microcomputer and compiler are required. There was a problem that it did not exist.

More specifically, since the 32-bit processor has hardware for processing 32-bit data and addresses, it becomes redundant hardware, resulting in an increase in cost and power consumption. have. In the 16-bit processor, management of the address space is inevitable in terms of address calculation as described in the prior art. In addition, the programmer needs to recognize the boundaries of the segments, which reduces the program development efficiency.

The 32-bit processor compiler selectively uses machine language instructions having a basic word length of 16 bits or 32 bits, and 32-bit addressing is required in the program, which increases the code size of the program. . If the bit width of the data bus connecting the 32-bit processor and the memory is 16 bits, 32
There is also a problem that the performance is significantly deteriorated as compared with the bit.

In view of the above problems, it is an object of the present invention to provide a program conversion device and a processor suitable for applications in which the bit width of data is 16 bits and an address space of about 16 megabytes is required.

[0012]

In order to solve the above-mentioned problems, the program conversion device of the present invention is intended for a processor that handles an address having a bit width longer than the effective bit width in a main data type, and is intended for a high-level language. A program conversion device for generating a machine language instruction based on a program, and a parameter holding means for holding an effective bit width in a main data type and an address bit width,
When the variable used in the machine language instruction to be generated is a variable that represents data, an instruction that validates the bit width of the data held by the parameter holding means is generated, and when it is a variable that represents an address, the parameter holding means And a generation unit that generates an instruction that validates the bit width of the address held by.

The bit width M of the data may be 16, and the bit width N of the address may be 17 or more and 31 or less. Further, when the machine language instruction to be generated is an instruction to access a memory, the generating means stores the correspondence held in the parameter holding means according to whether the variable to be accessed is data or address. Memory management means for instructing that the access width be the bit width to be read, and if the machine language instruction to be generated is an instruction that uses a register, the variable read or written to that register is data or an address. Register management means for instructing that the corresponding bit width held in the parameter holding means should be valid, and if the machine language instruction to be generated is an instruction that uses an immediate value, the immediate value is Immediate value management means for instructing to use the immediate value of the corresponding bit width held in the parameter holding means depending on whether it is data or address Memory management unit, the register managing unit, according to an instruction from the immediate managing means may consist of a code generating means for generating machine after instruction.

The processor of the present invention is a processor for executing the program generated by the program conversion device, and is a program counter having an N-bit length, an operation having an N-bit length, and a data bit width M.
And a means for executing a bit length operation.

Here, N may be 24 and M may be 16.

[0016]

In the program conversion device of the present invention by the above means, the generation means determines the bit width of the data held by the parameter holding means when the variable used in the machine language instruction to be generated is a variable representing data. Generate valid instructions. If it is a variable representing an address, an instruction for validating the bit width of the address held by the parameter holding means is generated.

Further, in the generating means, the memory management means, when the machine language instruction to be generated is an instruction to access the memory, determines whether the variable to be accessed is data or address. The code generation means is instructed that the corresponding bit width held in the parameter holding means should be the access width. The register management means is
When the machine language instruction to be generated is an instruction using a register, the corresponding bit width held in the parameter holding means is set according to whether the variable read or written in the register is data or address. Instructs the code generation means that it should be valid. When the machine language instruction to be generated is an instruction that uses an immediate value, the immediate value management means uses the immediate value of the corresponding bit width held in the parameter holding means according to whether the immediate value is data or an address. Instruct the code generation means what to do.

Further, the processor of the present invention is N (24)
An address space of 2 N (16 megabytes) can be used by a bit-length program counter, and an operation unit executes an operation of N (24) -bit length and an operation of M (16) -bit length, which is the bit width of data. You can

[0019]

FIG. 1 is a block diagram of a microcomputer and a program conversion device (hereinafter abbreviated as a compiler; the microcomputer and the compiler are collectively referred to as an information processing device) according to an embodiment of the present invention. In FIG. 1, the information processing apparatus includes a storage device 1 that stores a C language program, a compiler 2 that translates the C language program into a machine language program, and hardware 3 that executes an object code.

The compiler 2 consists of the following: 5
Is a syntax analysis unit, which analyzes the syntax of the C language program and generates an intermediate file composed of intermediate format statements and intermediate codes in which the program statements are converted into the intermediate format. A code generator 7 generates an object code based on the intermediate file.

A parameter setting unit 8 holds the bit width of the integer type data variable and the bit width of the pointer variable. In this embodiment, it is assumed that the user has previously set the bit width of the integer type data variable to 16 bits and the bit width of the pointer variable to 24 bits. A memory management unit 9 indicates a bit width for reading and writing the memory for the load / store instruction to be generated by the code generation unit 7 according to the type of the variable that is the target of the instruction.

Reference numeral 10 denotes a register management unit, which is a code generation unit 7
Specifies an effective bit width according to the type of the variable read / written in the register for the instruction using the register to be generated. An immediate value management unit 11 indicates the bit width of the immediate value in the instruction code for the instruction using the immediate value that the code generation unit 7 should generate, according to the type of the variable that is the immediate value.

The hardware 3 is composed of the following. A memory 13 stores the object code and data used in the program. An address bus 14 has a bit width of 24 bits. A data bus 15 has a bit width of 16 bits.

A bus control circuit 16 is provided for the address bus 14.
It is connected to the memory 13 via the data bus 15 and the data bus 15, and reads the object code stored in the memory 13 as an instruction one by one and reads / writes data from / to the memory 13. Reference numeral 17 is an instruction control circuit, which is a program counter 1
9 for indicating an instruction address to the bus control circuit 16,
It receives an instruction from the bus control circuit 16 and decodes it.

The program counter 19 outputs a 24-bit instruction address. Reference numeral 18 denotes an arithmetic execution circuit, which includes a register file 20 and an arithmetic unit 21. The register file 20 has a plurality of 24-bit registers. The arithmetic unit 21 uses the value held in the register file 20 to execute a 24-bit wide arithmetic logic operation or the like.

FIG. 2 shows a processing flow of the code generator 7. In step 20, data variables are extracted from the intermediate file and a variable table (symbol table) carrying information on each variable is created. An example of the symbol table is shown in FIG. In the figure, the symbol column assigns the symbol of the data variable, the type column assigns whether the data variable is an integer type or pointer type, the byte number column assigns the byte number of the data variable, and the head address column assigns it to memory. If the register is assigned, the register name indicates the register name when the register is assigned.

In step 21, it is determined whether or not there is an intermediate instruction for which code generation has not been processed from the intermediate file. If so, the process proceeds to step 22, and if not, the code generation ends. Step 22 reads one intermediate instruction in the order to be processed next from the intermediate file. Step 23 selects one or more machine language instructions that implement one intermediate instruction.

In step 24, one machine language instruction to be processed next from the selected machine language instruction is designated. The step 25 performs a process (hereinafter, referred to as an individual process) for generating an instruction code of one designated machine language instruction (hereinafter, referred to as an individual instruction). In step 26, it is determined whether or not there is a machine language instruction to be processed next among the machine language instructions selected in step 23. If so, return to step 24,
If not, the process returns to step 21.

3 to 6 show the flow of the individual processing in step 25 described above. First, step 30 determines whether the individual instruction belongs to a load / store instruction type,
If so, the memory management unit 9 is notified, and if not, the process proceeds to step 31. FIG. 4 shows a processing flow of the memory management unit 9 which receives this notification. In FIG. 4, step 40 is for a variable to be loaded / stored in / from the memory in the individual instruction (load / store instruction),
Look up the symbol table to find out the variable type.

In step 41, it is determined whether the type of the variable is an integer type data variable or a pointer type data variable, and if it is the former, the process proceeds to step 42, and if it is the latter, the process proceeds to step 43. In step 42, the code generation unit 7 is instructed that a load / store instruction having a data width to be accessed of 2 bytes should be generated, and the process proceeds to step 31.

In step 43, the code generator 7 is instructed to generate a load / store instruction having a data width to be accessed of 3 bytes, and the process proceeds to step 31. Second, step 31 determines whether or not the individual instruction uses a register, and if so, notifies the register management unit 10 and otherwise proceeds to step 32. FIG. 5 shows a processing flow of the register management unit 10 when receiving this notification. In FIG. 5, a step 50 refers to the symbol table for the variable stored in the register used by the individual instruction and checks the type of the variable.

In step 51, it is determined whether the type of the variable is an integer type data variable or a pointer type data variable, and if it is the former, the process proceeds to step 52, and if it is the latter, the process proceeds to step 53. In step 52, the code generation unit 7 is instructed to generate an instruction for validating the lower 16 bits of the register to be used, and the process proceeds to step 32.

In step 53, all two registers to be used are used.
The code generation unit 7 is instructed to generate an instruction that enables 4 bits, and the process proceeds to step 32. Thirdly, the step 32 determines whether or not the individual instruction uses the immediate data, and if so, notifies the immediate value management unit 11; otherwise, the process proceeds to step 33. FIG. 6 shows a processing flow of the immediate value management unit 11 when receiving this notification.

In FIG. 6, in step 60, a variable which is immediate data used in the individual instruction is
Look up the symbol table to find out the variable type. A step 61 decides whether the type of the variable is an integer type data variable or a pointer type data variable, and if it is the former, it proceeds to step 62, and if it is the latter, it proceeds to step 63.

In step 62, the code generator 7 is instructed to generate an instruction having an immediate value of 2 bytes, and the process proceeds to step 33. In step 63, the code generation unit 7 is instructed to generate an instruction having an immediate value of 3 bytes, and the process proceeds to step 33. Fourthly, in step 33, if there is an instruction from the memory management unit 9, the register management unit 10, or the immediate value management unit 11, the instruction code of the individual instruction is generated according to the instruction.

The operation of the microcomputer and the program conversion device of the present embodiment configured as described above will be described below. In order to simplify the explanation, the case where the C language program stored in the storage device 1 is as follows is given as an example. The syntax analysis unit 5 takes out a C language program from the storage device 1, analyzes the syntax according to the grammar, and generates an intermediate file described in an intermediate format language. An image of this intermediate file is shown below. However, for convenience here,
The intermediate form description has been rewritten to make sense.

Intermediate format statement 1: (int * a, b, c) Intermediate instruction 1: t1: = * a Intermediate instruction 2: t2: = t1 + b Intermediate instruction 3: t3: = t2 + 1 Intermediate instruction 4: c: = t3 Intermediate format statement 1 corresponds to the declaration statements int * a, b, c, and intermediate instructions 1 to 4 correspond to the arithmetic expression c = * a + b + 1.

These intermediate format statements and intermediate instructions are converted into object codes as follows.
When this intermediate file is input, the code generator 7
Data variables (including those without declaration) in the intermediate file are extracted, the type of each variable is inspected, and if necessary, allocated to memory, and the symbol table shown in FIG. 7 is created (see FIG. 2). Step 20).

In the above example, the variables * a, b, c explicitly declared are extracted from the intermediate format sentence 1. Since the variable * a declared as a pointer variable has the bit width of the pointer variable set to 24 bits in the parameter setting unit 8,
A 24-bit (3 bytes) area is secured and allocated in the memory. Further, the two variables b and c declared as integer type data variables have 16 bits (2 bytes) in the memory because the bit width of the integer type data variable is set to 16 bits in the parameter setting unit 8. Area is secured and allocated. Here, the variables * a, b, c
Are respectively allocated to the areas from the address 1000 to 3 bytes, the address 1004 to 2 bytes, and the address 1006 to 2 bytes. However, 1 byte at address 1003 is an empty area.

Further, the temporary variables t1, t from the intermediate instructions 1 to 4
2, t3 is extracted. The temporary variables t1, t2, t3 are treated as integer type data variables in accordance with the variables to be calculated. Information about these variables is written to the symbol table. The contents of the symbol table are dynamically rewritten whenever the register allocation or the like is changed thereafter. FIG. 7 already shown shows the contents of the symbol table at this point. At this point, the register column and the head address column of the temporary variable are left blank because there is no allocation.

After that, the code generator 7 generates a corresponding machine language instruction for each of the intermediate instructions as follows. << Intermediate instruction 1: t1: = * a >> The code generation unit 7 determines whether or not there is an intermediate instruction to be processed (unprocessed) in the intermediate file (step 21 in FIG. 2). At this point, the intermediate instructions 1 to 4 remain, so the process proceeds to step 22.

Next, the code generator 7 reads one of the unprocessed intermediate instructions at the beginning (step 2).
2) Select one or more machine language instructions that implement the intermediate instruction (step 23). The selection of one or more instructions that realize the intermediate instruction 1 in step 23 will be specifically described.

The intermediate instruction 1 reads "3 bytes from the address 1000 to which the pointer variable * a is assigned,
The contents are read out as 2 bytes and stored in the temporary variable t1. It is the content. Code generator 7
Selects a machine language instruction corresponding to the above items 1 to 3 to realize this content. That is, the address 1000 is stored as immediate data in the first address register.
v instruction, 1st address register is used to read the contents (pointer) of * a to the 2nd address register, mov instruction, 2nd address register is used to read the data pointed to by the pointer to the data register Three instructions, mov instruction, are selected. The first and second
Address registers A0 and A1 are assigned. This is entered in the symbol table.

<Generation of Individual Instruction> Further, the code generator 7 designates one instruction (individual instruction) to be processed from these plural instructions (step 24) and generates an instruction code for the individual instruction. (Step 25). The instruction code generation of the individual instruction in step 25 will be specifically described with reference to the flows of FIGS.

Since the individual instruction designated in step 24 is not the load / store instruction for accessing the memory (step 30 in FIG. 3) but the instruction using the register A0, the code generator 7 informs the register manager 10 of the instruction. To that effect (step 31). The register management unit 10 refers to the symbol table (step 50 in FIG. 5), and the variable to be stored in the register A0 is a pointer (step 5).
1) Instruct the code generation unit 7 to generate an instruction in which all 24 bits of the register are valid (step 53).

Furthermore, since the individual instruction uses immediate data, the code generator 7 notifies the immediate management unit 11 of that (step 32). The immediate value management unit 11 refers to the symbol table (step 60 in FIG. 6), and the immediate value to be stored in the register A0 is a pointer (step 6).
1) Instruct the code generation unit 7 to generate an instruction having 3-byte immediate data (step 6)
3).

In accordance with the instructions from steps 53 and 63,
The code generator 7 generates the following instruction 1 corresponding to the individual instruction (step 33). Instruction 1: MOV # 001000, A0 After that, the code generation unit 7 is to generate the next instruction code among the plurality of instructions selected in step 23,
Remains (step 26), the process proceeds to step 24.

<Generation of Individual Instruction> The code generation section 7
One instruction (individual instruction) to be processed is designated from these plural instructions (step 24), and an instruction code for the individual instruction is generated (step 25). The instruction code generation of the individual instruction in this step 25 is shown in FIGS.
A specific description will be given using the flow.

Since the individual instruction is a load / store instruction for accessing the memory, the code generating section 7 notifies the memory managing section 9 to that effect (step 30 in FIG. 3). The memory management unit 9 refers to the symbol table (step 40 in FIG. 4), and since the variable to be stored in the second register A1 is the pointer (step 41), the access width in memory access is 3 bytes. The code generation unit 7 is instructed that a load instruction should be generated (step 43).

Furthermore, since the individual instruction is an instruction that uses the registers A0 and A1, the code generation unit 7 notifies the register management unit 10 to that effect (step 31). The register management unit 10 refers to the symbol table (step 50 in FIG. 5), and the variable to be stored in the second register A1 is a pointer (step 51).
The code generation unit 7 is instructed to generate an instruction whose bit is valid (step 53).

After that, the code generator 7 proceeds to step 33 because the individual instruction does not use immediate data (step 32). Follow the instructions from steps 43 and 53
The code generator 7 generates the following instruction 2 corresponding to the individual instruction (step 33). Instruction 2: MOV @ A0, A1 After that, the code generation unit 7 proceeds to step 24 because there is an instruction to generate the next instruction code among the plurality of instructions selected in step 23 (step 26). .

<Generation of Individual Instruction> For the individual instruction as well, the code generator 7 generates the next instruction 3 (steps 24 to 26). At this point, the temporary variable
The D0 register is assigned to t1. Instruction 3: MOV @ A1, D0 Hereinafter, in the same manner as above, the processing of each intermediate instruction in the loop of steps 21 to 26 is the processing of each individual instruction in steps 24, 25 (flow of FIGS. 3 and 4), and 26. Therefore, a detailed description is omitted and an outline is shown.

<< Intermediate instruction 2: t2: = t1 + b >> This intermediate instruction reads "2 bytes from the address 1004 to which the variable b is allocated, and adds the content and the temporary variable t1 to the temporary It is stored in the variable t2. " First, the code generation unit 7 generates an instruction 4 for loading an address four addresses away from the address 1000 indicated by the contents of the A0 register, corresponding to an individual instruction. At this time, the memory management unit 9 refers to the symbol table (step 40) and the individual instruction 4 loads the integer type data variable (step 4).
1) Instruct that a load instruction having an access width of 2 bytes should be generated (step 42). Register management unit 10
Refers to the symbol table (step 50) and stores the integer type data in the register (step 5).
1) Instructing that an instruction in which the lower 16 bits of the register are valid should be generated (step 52). At this time, the variable b is stored in the register D1.

Instruction 4: MOV @ (04, A0), D1 Next, the code generator 7 stores a variable b stored in the D1 register corresponding to the individual instruction and a temporary variable t1 indicated by the contents of the D0 register. Is added and the instruction 5 for storing the result in the D1 register is generated. At that time, the register management unit 10
Since the integer type data is stored in the register by referring to the symbol table (step 50) (step 51), it is instructed to generate an instruction in which the lower 16 bits of the register are valid (step 52). At this point, the register D1 is assigned to the temporary variable t2.

Instruction 5: ADD D0, D1 << Intermediate instruction 3: t3: = t2 + 1 >> This intermediate instruction has the content that "1 is added to temporary variable t2 and stored in temporary variable t3". To do. The code generation unit 7 generates the next instruction 6 for storing the result of adding the 2-byte immediate value # 0001 and the register D1 in the D1 register according to the instructions of the register management unit 10 and the immediate value management unit 11. At this point, the register D1 is assigned to the temporary variable t3.

Instruction 6: ADD # 0001, D1 << Intermediate instruction 4: c: = t3 >> This intermediate instruction is to write the temporary variable t3 in the area of 2 bytes from the address 1006 to which the variable c is allocated. Is the content. Code generator 7
In accordance with an instruction from the memory management unit 9, generates the next instruction 7 for storing the contents of the register D1 at an address 6 apart from the address indicated by the contents of the register A1.

Instruction 7: MOV D1, @ (06, A0) As described above, the processing of each intermediate instruction is completed. As a result, the code generator 7 outputs the following object code to the memory 13. On the memory 13, the instruction 1 to the instruction 7 are 100000, 100005,
100007, 100008, 10000a, 10000b, 10
It will be located at address 000f.

Instruction 1: Address 100000 MOV # 001000, A0 Instruction 2: Address 100005 MOV @ A0, A1 Instruction 3: Address 100007 MOV @ A1, D0 Instruction 4: Address 100008 MOV @ (04, A0), D1 Instruction 5: Address 10000a ADD D0, D1 Instruction 6: Address 10000b ADD # 0001, D1 Instruction 7: Address 10000f MOV D1, @ (06, A0) These instructions represent the object code in mnemonic (assembly language) for convenience. , Memory 1
When stored in 3, it is represented by a binary number. All of the above numbers are hexadecimal numbers. The operation executed by the microcomputer for this object code arranged in the memory 13 will be described below.

(Instruction 1: Address 100000 MOV # 001000, A0
The bus control circuit 16 and the instruction control circuit 17 output the value 100000 held by the program counter 19 to the address bus 14 and fetch the instruction 1 via the data bus 15 to decode it. Operation execution circuit 1 according to the decoding result
8 is the immediate value 001000 specified by the operand of instruction 1
Is received from the instruction control circuit 17, and the register file 2
Store in A0 register in 0.

(Instruction 2: Address 100005 MOV @ A0, A1) The bus control circuit 16 and the instruction control circuit 17 similarly fetch and decode the instruction 2. Calculation execution circuit 18
Reads the contents of the A0 register, outputs it to the address bus 14, reads the memory 13, and
The 16-bit data read out via is stored in the lower 16 bits of the A1 register. Subsequently, the arithmetic execution circuit 1
8 is read by the arithmetic unit 21 by adding 2 to the value 001000 of the A0 register, outputting the addition result 001002 to the address bus 14 by the bus control circuit 16, reading the memory 13, and reading via the data bus 15. Store the bit data in the upper 8 bits of the A1 register.

(Instruction 3: Address 100007 MOV @ A1, D0) The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 3. The arithmetic execution circuit 18 reads the contents of the A1 register and outputs it to the address bus 14,
The memory 13 is read. After that, the arithmetic execution circuit 18 sets the 16-bit value read via the data bus 15 to D0.
Store in the lower 16 bits of the register. The D0 register is
It will hold the data pointed to by the pointer variable * a.

(Instruction 4: Address 100008 MOV @ (04, A0), D1
) Bus control circuit 16 and instruction control circuit 17 fetch and decode instruction 4. The arithmetic execution circuit 18 receives the displacement value 04 from the instruction control circuit 17, adds it to the value 001000 of the A0 register read by the arithmetic unit 21, and adds the addition result 001004 to the address bus 14 by the bus control circuit 16.
To the memory 13 for reading. After that, the operation execution circuit 18 uses the lower 16 bits of the D1 register in the register file 20 to read the 16-bit value read on the data bus 15.
Store in 6 bits. The D1 register will hold the variable b.

(Instruction 5: Address 10000a ADD D0, D1) The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 5. The arithmetic execution circuit 18 includes an arithmetic unit 21.
The value of the D0 register read from the register file 20 and the value of the D1 register are added, and the addition result is stored in the D1 register in the register file 20. The arithmetic unit 21 performs this addition with 24 bits, but the lower 16 bits of the D1 register are effective. The D1 register holds the added value of the data indicated by the pointer variable * a and the variable b.

(Instruction 6: Address 10000b ADD # 0001, D1)
The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 6. The arithmetic execution circuit 18 is the arithmetic unit 2
1, the value of the D1 register read from the register file 20 and the immediate value 00 received from the instruction control circuit 17
01 and are added, and the addition result is stored in the D1 register. The D1 register stores the data indicated by the pointer variable * a, the variable b, and the immediate value 0.
The added value with 001 will be retained.

(Instruction 7: Address 10000f MOV D1, @ (06, A0)
The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 7. The arithmetic execution circuit 18 receives the variable position 06 from the instruction control circuit 17, adds it to the value 001000 of the A0 register read from the register file 20 in the arithmetic unit 21, and adds the addition result 001006 to the bus control circuit 1.
6 outputs the lower 16 bits of the D1 register to the data bus 15 and outputs 16 bits of data to the memory 13.
At the address 001006 of the memory 13, the data indicated by the pointer variable * a, the added value of the variable b and the immediate value 0001 will be written.

The object code generated by the C language program being translated by the compiler 2 in this way is
It is executed by hardware 3. As described above, according to the present embodiment, the compiler 2 manages the arrangement of all variables and the generated object code on the memory with the 24-bit address, and the microcomputer manages the 24-bit register file 20 and the arithmetic unit. Since these addresses are calculated by 21 and the memory 13 is accessed by the 24-bit address bus 14, the information processing apparatus of this embodiment can realize a completely uniform 16-megabyte address space which is not divided into segments, and A programmer who writes a C language program does not need to recognize spatial nonuniformity such as segment boundaries, and does not suffer performance degradation in address calculation such as segment register manipulation. Along with that, the development efficiency of the program is improved.

When the bit width of data is 16 bits, 1
For applications requiring an address space of 6 megabytes, the information processing apparatus according to the present embodiment has a 24-bit register file 20 and an arithmetic unit 21 for a microcomputer.
The cost and power consumption do not increase due to excessive hardware unlike the conventional 32-bit processor.

Further, the basic word length of the machine language instruction of the microcomputer is 8 bits, and even when the immediate value of the address is included in the instruction as in the above-mentioned instruction 1, the immediate value is at most 24 bits, so the compiler The object code generated by 2 is extremely small as compared with an information processing device of a 32-bit processor in which the basic word length of a machine language instruction is 16 or 32 bits and the immediate value of an address is 32 bits at maximum. Further, even if compared with a 16-bit processor that can handle only an address space of 64 kilobytes, the cause of the increase in code size is only 1 byte at maximum due to the immediate value of the address associated with the instruction, so the size of the object code does not become large.

The width of the data bus 15 of the microcomputer of this embodiment is 16 bits. Compared with the case where this is 24 bits, the value relating to the 24-bit address stored in the register file 20 is stored in the memory 13. However, the execution time only increases when reading and writing, and this performance degradation occurs when the bit width of the data bus of the information processing device of the 32-bit processor that always reads and writes in 32 bits to the memory is 16 bits. Very small compared to.

In this embodiment, the bit width of the address bus 14, the program counter 19, the register file 20 and the arithmetic unit 21 of the microcomputer is set to 24 bits, and the bit width of the pointer variable of the parameter setting section 8 of the compiler 2 is set to 24 bits. Although it is set to 24 bits, it may be set to an arbitrary bit width of 17 bits to 31 bits corresponding to the width of the required address space. The correspondence is as follows.

Required address space Bit width 128 kilobytes 17 bits 256 kilobytes 18 bits 512 kilobytes 19 bits 1 megabyte 20 bits 2 megabytes 21 bits 4 megabytes 22 bits 8 megabytes 23 bits 16 megabytes 24 bits (this embodiment) 32 megabytes 25 bits 64 megabytes 26 bits 128 megabytes 27 bits 256 megabytes 28 bits 512 megabytes 29 bits 1 gigabyte 30 bits 2 gigabytes 31 bits By doing this, there is no excessive hardware that exceeds the bit width of the address, and cost and The power consumption can be optimized.

Although the width of the data bus 15 of the microcomputer is 16 bits in this embodiment, it may be 24 bits. In addition, the present embodiment is based on the address bus 14 and the program counter 1
9. The bit width of the register file 20 and the arithmetic unit 21 and the setting value of the bit width of the pointer variable of the parameter setting unit 8 of the compiler 2 are set to 24 bits, and the bit width of the data variable of the parameter setting unit 8 of the compiler 2 is set. Although the value is set to 16 bits, these bit widths are not limited. By setting the latter to be equal to the bit width of the type of data mainly handled by the program (denoted by M) and the former by a value larger than M (denoted by N), the information processing apparatus causes the bit width of the type of data primarily handled by the program. 2 that can be expressed by
It is possible to handle an address space of 2 N power bytes that exceeds the space of M power bytes of.

Further, in the present embodiment, the type of the data variable for setting the bit width in the parameter setting unit 8 is an integer type, but this may be any type according to the type of data mainly handled by the C language program. . In addition, this embodiment is
The C language program is compiled and executed, but the language is not limited. By making the compiler 2 correspond to the description language of the program, the information processing device can execute the program of any language.

[0074]

As described above, according to the present invention, since the data width and the pointer width can be set arbitrarily in the parameter setting means, the programmer is made to recognize the spatial nonuniformity such as the segment boundary. It is possible to handle an arbitrary address space that is larger than the space that can be represented by the bit width of the data of the type to be handled, without causing the performance degradation in address calculation such as the operation of the segment register. effective.

In addition, in the application (application) of the microcomputer for embedded use, the data bit width is required to be 16 bits, and the address space is 64 bits.
There is an effect that optimization can be achieved for a device that requires more than kilobytes but does not require a size of 4 gigabytes. Further, according to the present invention, the code size of the program is smaller than that of the conventional 32-bit processor information processing apparatus, and the bit width of the data bus is 16.
Even in the case of bits, there is an effect that it is possible to realize an information processing device with almost no performance degradation.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 shows a processing flow of a code generation unit 7 in the embodiment.

FIG. 3 shows a flow of individual processing in a processing flow of a code generation unit 7 in the same embodiment.

FIG. 4 shows a processing flow of a memory management unit 9 in the embodiment.

FIG. 5 shows a processing flow of a register management unit 10 in the embodiment.

FIG. 6 shows a processing flow of an immediate value management unit 11 in the same embodiment.

FIG. 7 shows a symbol table in the embodiment.

[Explanation of symbols]

 1 storage device 2 compiler 3 hardware 5 syntax analysis unit 7 code generation unit 8 parameter setting unit 9 memory management unit 10 register management unit 11 immediate value management unit 13 memory 14 address bus 15 data bus 16 bus control circuit 17 instruction control circuit 18 operation Execution circuit 19 Program counter 20 Register file 21 Operation unit

Claims (5)

[Claims] 1. A program conversion device for generating a machine language instruction based on a high-level language program for a processor handling an address having a bit width N longer than an effective bit width M in a main data type, When the parameter holding means that holds the effective bit width and the bit width of the address in the main data type and the variable used in the machine language instruction to be generated are variables that represent data, A program conversion, comprising: a generating unit that generates an instruction that validates a bit width, and generates an instruction that validates the bit width of an address held by a parameter holding unit when the variable represents an address. apparatus. 2. The program conversion device according to claim 1, wherein the bit width M of the data is 16, and the bit width N of the address is 17 or more and 31 or less. 3. When the machine language instruction to be generated is an instruction to access a memory, the generating means holds it in the parameter holding means according to whether the variable to be accessed is data or address. If the machine language instruction to be generated is an instruction that uses a register, the variable that is read or written in the register is data. Depending on whether it is an address or an address, register management means for instructing that the corresponding bit width held in the parameter holding means should be valid, and the machine language instruction to be generated is an instruction using an immediate value. Depending on whether the immediate value is data or an address,
An immediate value management means for instructing to use the immediate value of the corresponding bit width held in the parameter holding means, and a code generation means for generating a machine language instruction in accordance with instructions from the memory management means, the register management means and the immediate value management means 3. The program conversion device according to claim 1, comprising: 4. A processor for executing a program generated by the program conversion device according to claim 1, comprising a program counter having an N-bit length, an operation having an N-bit length, and a bit width of data. And an executing means for executing an operation of M bit length. 5. The processor of claim 3, wherein N is 24.