JPH06337763A - Data format controlling controller for disk device - Google Patents

Abstract

PURPOSE:To discriminate whether data is original data or not by detecting an INDEX address mark and then outputting data bits and clock bits, byte by byte. CONSTITUTION:In order to detect an SYNC byte, FFn as the data pattern of the clock bits of an SYNC byte part is written in a comparison register 9 through an internal bus 6, and it is confirmed through a comparing circuit 11 that the data pattern of a shift register 8 where the clock bits are set becomes FFn, thereby confirming an SYNC byte field. After an address mark is confirmed, 8-byte data which are its data bits and clock bits are transferred to a host computer 4 and outputted to an external bus terminal 5, and every time serial data bits are advanced by one byte thereafter, data codes of shift registers 7 and 8 are transferred to the host interface 4 through an internal bus 6 and outputted to the terminal 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a controller for controlling a data format of a disk device, and in particular, data to be read from and written to the disk device is new such as MFM recording system and FM recording system. The present invention relates to a disk device that handles a serial data string with clock data having a certain regularity with respect to data.

[0002]

2. Description of the Related Art Conventionally, two types of recording methods, FM and MFM recording methods, have been mainstream as recording methods for disk devices, particularly floppy disk devices. In the case of the FM recording method, the serial data read and written in the disk device has a data structure in which 1 clock bit is added to 1 bit of new data without fail. That is, as shown in the following figure, 1 byte of new data is (D7, D6, D5,
In the case of D4, D3, D2, D1, D0), the serial data exchanged between the disk devices is 2-byte data in which 1-bit data is embedded between each data.

New data: D7 D6 D5 D4
D3 D2 D1 D0 Serial data: 1 D7 1 D6 1 D5 1
D4 1 D3 1D2 1 D1 1 D0 For example, when the new data of 1 byte is FEh, this serial data becomes 2 bytes of FFFEh.

On the other hand, in the case of the MFM recording system, the serial data to be read from and written to the disk device has a data structure in which 1 clock bit is added to 1 bit of new data as in the FM recording system, and 1 byte. The new data of (D7, D6, D5, D4, D3, D
2, D1, D0), the serial data exchanged between the disk devices is 2-byte data in which 1-bit data is embedded between each data, that is, new data as follows: D7 D6 D5 D4 D3 D2 D
1 D0 Serial data: C7 D7 C6 D6 C5 D5
C4 D4 C3 D3 C2 D2 C1 D1 C
It becomes 0 D0. However, the generation of this clock bit has the following rules.

Cn = Dn-1 * Dn For example, when the new data of 1 byte is A1h, the serial data becomes 44A9h of 2 bytes.

The data format in the disk device using these recording methods is composed of sectors consisting of ID and DATA fields as shown in FIGS. 6 and 7. To identify the beginning of each field, It will be identified by detecting the unique data pattern of the address mark located after the SYNC field for synchronizing the serial data. Particularly, since the data pattern of the clock bits of these address marks is a unique data pattern that does not comply with the data generation rule of the recording method, the head of each address mark is detected by detecting this clock bit.

Here, with regard to the method of reading this data format, particularly as an LSI (hereinafter, abbreviated as FDC) for controlling the data format of the floppy disk device, μPD765A and μP manufactured by NEC Corporation are used.
There is D72065, and writing and reading are performed in the disk device by using the above-mentioned recording method.

FIG. 2 illustrates the case where the data in the data field of one sector is read from the floppy disk drive.

That is, first, a SYNC byte data pattern is detected from serial read data coming from a floppy disk device, and then a clock bit and a data bit forming an address mark of an ID field are detected. Further, after the CRC byte for detecting the presence / absence of a predetermined sector number of a cylinder, a head, a sector, a sector length and their reading is correctly detected, the SYNC byte which is the head of the DATA field following the ID field is detected. Is detected and the address mark of the DATA field is detected in the same manner as the mark byte of the ID field. After this mark byte is correctly detected, a new data bit following this mark byte is transferred byte by byte to the upper host system by a predetermined number of data bytes, and the CRC following this data byte is transferred.
The byte is used to detect the presence or absence of a read error during reading.

[0010]

As described above, the data in the data field is transferred without clock bits.
In the FDC that transfers only data bits, when the developed software is written and stored in the data field of each sector, it is always read and inadvertently copied.

In order to prevent this illegal copying of data, the developer intentionally changes the arrangement of sectors, changes the recording method for each cylinder, and changes the C field of the DATA field.
Only RC byte is destroyed by using a special device and MS
There is a problem that a special format configuration that cannot be easily copied by an OS (operating system) such as DOS must be considered, and a device and software for controlling the special format must be developed. .

[0012]

[Means for Solving the Problems] MFM recording method and FM
In a controller for controlling a data format of a disk device that supports a recording method, a means for identifying an ID field and a DATA field forming a sector, a means for identifying a synchronization byte and an address mark byte forming each field, It is equipped with at least a means for converting serial data input from the disk device into byte units and outputting the byte data. After detecting an INDEX address mark, each data bit and clock bit constituting the data after this mark byte is 1 byte each. It is characterized by outputting.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present application is particularly concerned with the case where the data formatted by the above-mentioned μPD765A which is conventionally used is read as shown in FIG. 8 and particularly, the INDEX address mark following the INDEX signal indicating the rotation start point of the track. The FDC has a function of reading the subsequent data and alternately outputting the data bit and the clock bit of the data located immediately after that in 1-byte units.

Here, as described in the prior art, M
An explanation will be given using a data string recorded in FM. When 1 byte of clock data is read from the floppy disk drive with 1 byte of clock bit generated as follows, the new data: D7 D6 D5 D4 D3 D2
D1 D0 Serial data: C7 D7 C6 D6 C5 D5
C4 D4 C3 D3 C2 D2 C1 D1 C
0 D0 In conventional FDC, 1 byte of new data (D7 D6
Only D5 D4 D3 D2 D1 D0) is output to the host system, whereas the FDC of the present invention is output.
Then, 1 byte of new data (D7 D6 D5 D4
D3 D2 D1 D0) and clock bit data 1 byte (C7 C6 C5 C4 C3 C2 C1 C
The feature is that 0) is output to a host system.

That is, the FDC waits for the input of the INDEX signal indicating the rotation start point of the track, and then detects the SYNC field, which is the synchronous clock signal following the INDEX signal, as shown in FIG. After detecting the INDEX address mark, which is a mark byte consisting of 4 bytes, starts data transfer to the host interface, including the data of this address mark, the data bits and the clock bit described above from the data following this one byte at a time. To do.

The functional configuration of the FDC of the present invention will be described with reference to FIG. 1 is random access memory (RA
M), 2 is a read only memory (ROM), 3 is a central processing unit (CPU) of this FDC, 4 is an interface for receiving and transmitting data with a host system, 1
0 is a data separator for generating a reproduction read data signal 12 and a clock signal 13 synchronized with it for serial read data coming from the floppy disk device,
Numeral 7 designates new data among the reproduction read data output from the data separator 10 by using the synchronous clock signal 13.
Numeral 8 is a shift register for storing bytes, and 8 is a shift register for storing one byte of the clock bit from the reproduction read data output from the data separator 10 by using the synchronous clock signal 13. Reference numeral 9 is a register that stores comparison reference data for comparing the data code of the shift register 8 that stores a clock bit of 1 byte, and these data are compared in byte units by using 14 and 15 signals. The comparison result is output to the comparison circuit 11, and the comparison result is confirmed by the CPU 3 described above.

Next, in the case where the FDC having the above-mentioned function performs the read operation for the data after the address mark byte immediately after the ID field is detected in the control flow chart shown in FIG. 1 will be described with reference to FIG.

I trying to read from the host system
In order to detect the SYNC byte field, which is the sync clock signal located before the NDEX address mark,
First, in order to detect the SYNC byte, FFh which is the data pattern of the clock bit of the SYNC byte portion is written to the comparison register 9 via the internal bus 6, and the data pattern of the shift register 8 in which the clock bit is set becomes FFh. It is possible to confirm the SYNC byte field by confirming the value via the comparison circuit 11. After this confirmation is made, it is confirmed that the data pattern of the shift register 8 in which the data bit at that time is stored is 00h. By confirming this, it can be confirmed that it is a SYNC byte field. Next, detection of the address mark byte following this SYNC byte is started. That is, 14h, which is the first clock bit byte of this first address mark, is set in the comparison register 9, waits until the shift register 8 becomes the same as this data, and the shift register 7 immediately after the same becomes the same. Data, that is, the data code of the first address mark is C
Make sure it is 2h. Similarly, for the second, third address marks following this, it is set in the comparison register 9 that the clock bit byte is 14h for 1-byte unit data from the above detection. By doing so, it is confirmed that the shift register 8 is the same as this data. Similarly, the data of the shift register 7 immediately after that is the data code of the address mark is C
Confirm each for 2 h. Similarly, for the fourth address mark, the shift register 8 is set by setting in the comparison register 9 that the clock bit byte is 01h for the data in 1-byte units from the above detection. Is the same as this data, and similarly, the data of the shift register 7 immediately after that is also confirmed that the data code of the address mark is FCh.

After this address mark is confirmed, it is the data bit and the clock bit (C2h, 14).
h) (C2h, 14h) (C2h, 14h) (FCh,
01h) 8-byte data is transferred to host interface 4
To the external bus terminal 5, and thereafter the serial data bit input from the floppy disk device is 1
The data codes of the shift registers 7 and 8 are transferred to the host interface 4 via the internal bus 6 and output to the external bus terminal 5 each time the byte is advanced.

As described above, the data after the mark byte immediately after the target ID field is detected and the data bit and the clock bit can be output to the host system for each byte.

Although the MFM recording method has been described in the first embodiment, the FM recording method used in the floppy disk device shown in FIG. 9 will be described next.

Also in the second embodiment, as in the first embodiment, in the case of reading the data formatted in advance, in particular,
When the written data is read by changing the data recording method excluding the SYNC byte and the address mark of the DATA field of each sector from the conventional recording method,
It is an FDC having a function of alternately outputting a data bit and its clock bit in 1-byte units including a mark byte following an ID field of a target sector. Here, as described in the related art, the FM-recorded data string reads serial data in which 1-byte clock bit is generated as follows for 1-byte new data as in the MFM recording method. If you do, the new data: D7 D6 D5 D4 D3 D2
D1 D0 Serial data: C7 D7 C6 D6 C5 D5
C4 D4 C3D3 C2D2 C1 D1 C0
D0 In conventional FDC, 1 byte of new data (D7 D6
Only D5 D4 D3 D2 D1 D0) is output to the host system, while the FD of this embodiment is output.
In C, the new data 1 byte (D7 D
6 D5 D4 D3 D2 D1 D0) and clock bit data 1 byte (C7 C6 C5 C4 C3 C
2 C1 C0) is output to an upper host system.

That is, as in the first embodiment of MFM recording, the control flowchart for detecting the target INDEX address mark and transferring the data is the same as that of the MFM recording system shown in FIG.

Next, only the points different from the case of the MFM recording in the FDC having the above-mentioned function will be described.

That is, in the control flow chart shown in FIG. 3, the respective functions of FIG. 1 will be described with reference to FIG. 5 particularly in the case of performing the operation at the time of reading the data after the address mark byte of the DATA field.

I trying to read from the host system
In order to detect the SYNC byte field, which is the sync clock signal located before the NDEX address mark,
First, in order to detect the SYNC byte, FFh which is the data pattern of the clock bit of the SYNC byte portion is written to the comparison register 9 via the internal bus 6, and the data pattern of the shift register 8 in which the clock bit is set becomes FFh. It is possible to confirm the SYNC byte field by confirming the value via the comparison circuit 11. After this confirmation is made, it is confirmed that the data pattern of the shift register 8 in which the data bit at that time is stored is 00h. By confirming this, it can be confirmed that it is a SYNC byte field. Next, detection of a 1-byte address mark byte following this SYNC byte is started. That is, the clock bit byte D7h of this address mark is set in the comparison register 9 and waits until the shift register 8 becomes the same as this data, and the data of the shift register 7 immediately after the same, that is, the data code of this address mark. Is FCh.

After this address mark is confirmed, it is this data bit and clock bit (FCh, D7).
8 bytes DATA of h) is transferred to the host interface 4 and output to the external bus terminal 5, and thereafter, the data of the shift registers 7 and 8 is incremented every time the serial data bit input from the floppy disk device advances by 1 byte. The code is transferred to the host interface 4 via the internal bus 6 and output to the external bus terminal 5.

As described above, similarly to the MFM recording method, the data bit after the mark byte immediately after the target ID field is detected and the data bit and the clock bit thereof are each 1 bit.
It can be output to the host system byte by byte.

[0029]

According to the FDC of the present invention described above,
After detecting the INDEX address mark, the data bit and the clock bit forming the data including the mark byte can be output. Therefore, when only the clock bit is read based on the MFD recording method generation method and the FDD recording method in which the data is generated by the software developer independently based on the FM recording method generation method, the FDC After transferring the data bit and the clock bit to the host system by using, confirm whether the data code of this clock bit matches the data originally generated in advance by the host system to identify whether it is the original data or not. Can do 2
The following functions can be provided.

Further, in the conventional FDC, the data of the clock bit after the address mark of the DATA field is always generated based on the MFM recording method and the generation method of the FM recording method. It cannot be matched with the data of the clock bit that has been created, and in particular, this clock bit has a data length equal to the number of data bytes of a sector, and if one file covers several tens of sectors, an astronomical clock is used. Since the bit data pattern can be obtained, there is an effect that it cannot be copied.

On the other hand, in the conventional FDC read operation, D
The data of the clock bit after the address mark of the ATA field is not verified at the time of reading, no matter what kind of data string it may have. Therefore, even if there is a clock bit that does not match the recording method, the conventional FDC does nothing. In order to lead without problems, MS-D
Since it is possible to record data in a format that matches the format supported by the OS such as the OS, it is special to change the recording method for each cylinder or to interleave sectors discontinuously as in the conventional case. There is no need to consider a different recording method, and it is possible to record original data very easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment.

FIG. 2 is a diagram showing a conventional control flow.

FIG. 3 is a diagram showing a control flow of the first embodiment.

FIG. 4 is a diagram showing a control flow of the second embodiment.

FIG. 5 is a diagram showing a control flow of a third embodiment.

FIG. 6 is a diagram showing a conventional data format.

FIG. 7 is a diagram showing a conventional data format.

FIG. 8 is a diagram showing a data format of the first embodiment.

FIG. 9 is a diagram showing a data format of a second embodiment.

[Explanation of symbols]

1 RAM 2 ROM 3 CPU 4 Interface circuit with host system 5 External bus 6 Internal bus 7 Circuit for stacking data bit coming from disk device 8 Circuit for stacking clock bit coming from disk device 9 Register for keeping expected clock data pattern 10 Data separator 11 Comparison circuit

Claims (1)

[Claims] 1. A controller for controlling an MFM recording system and a data format of a disk device supporting the FM recording system, an interface circuit with a host system, a CPU for controlling the sequence of the entire controller, R for which the sequence is programmed
The OM, the RAM that can be used by the CPU for general purposes, the data separator that outputs the read data and the synchronizing signal in phase synchronization with the serial read data input from the disk device, and the data separator circuit that outputs the data. At least a two register that separates a clock bit and a data bit from two signals and stores each of them, and a comparator circuit that compares the value of the register that stores the clock bit with an expected data value preset by the CPU. IN following the INDEX signal that indicates the track rotation start point
The DEX address mark is detected, and the data bit and the clock bit forming the detected address mark byte and the data bit and the clock bit forming the data subsequent thereto are also set to 1 respectively.
A data format controller for a disk device, which outputs bytes byte by byte to an interface with a host system.