JPH06333928A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To reduce the variation of the shapes and dimensions of wiring layers caused by the roughness and fineness of a pattern and, at the same time, to restore the flatness of the wiring layers lost by the roughness and fineness at the time of forming multilayer interconnections. CONSTITUTION:At the time of patterning polysilicon wiring on a semiconductor substrate 11, a polysilicon wiring layer 12 to be used as actual wiring and dummy polysilicon wiring layer 121 are simultaneously patterned. Similarly, a first and second Al wiring layers 14 and 16 are simultaneously formed with a dummy first and second Al wiring layers 141 and 161, respectively, on an upper wiring layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming multi-layer wiring.

[0002]

2. Description of the Related Art In recent years, multi-layer wiring such as a two-layer Al or three-layer Al process has been adopted due to the demand for higher speed and higher integration of LSI. As shown in FIG. 2, for example, a conventional method of forming a multi-layer wiring is to form a polysilicon wiring layer (2) on a semiconductor substrate (1), and to dispose a first layer via a first interlayer insulating film (3). An Al wiring layer (4) is formed, and a second Al wiring layer (6) is further formed via a second interlayer insulating film (5),
This is done by forming a protective film (7) so as to cover it. All of these wiring layers are LS
It is necessary for the operation of I and is formed for connection between semiconductor elements such as MOS transistors.

However, such multilayer wiring is adopted,
As a result of replacing the polysilicon wiring layer by the upper Al wiring, the pattern density of each wiring layer is lowered, and the pattern density becomes uneven depending on the place. This caused two problems.
First, there is a large variation in the shape and processing dimensions of the wiring layer due to the density of the patterns.

For example, as shown in FIG.
The wiring layer (8A) has a vertical cross-sectional shape where the pattern density is high, but the wiring layer (8B) is low when the pattern density is low.
Has a trapezoidal shape. This is presumably because the ion refraction due to the charge up of the photoresist (9) is affected by the density of the pattern. Further, in the case of plasma mode etching, it has been observed that the wiring layer (10A) where the pattern density is dense has a trapezoidal shape and the wiring layer (10B) where the pattern density is sparse is vertical.

In any case, in the conventional method for forming a multi-layered wiring, since the shape and the dimension are different due to the density of the patterns, it is very difficult to control the process, and a defect such as a short circuit or a disconnection of the wiring is easily caused. There was a point. Second
In addition, the unevenness of the pattern causes a loss of flatness, which makes it difficult to form a multilayer wiring. This is apparent from FIG. 2, but in the case of a memory such as a DRAM, for example, a memory cell region having a dense pattern and a peripheral circuit region having a low pattern density or a peripheral region of a chip have a considerable amount. Absolute level difference (H) occurs. Therefore, the step coverage of the wiring layer is deteriorated, which makes it difficult to form a multilayer wiring.

[0006]

The present invention has been made in view of the above-mentioned two problems, and firstly, the variation of the shape and the processing dimension of the wiring layer due to the density of the pattern is reduced. Is intended. Secondly,
The purpose is to recover the flatness lost due to the sparse and dense patterns and to promote further multilayer wiring.

[0007]

According to the present invention, in a method for forming a multilayer wiring on a semiconductor substrate, when patterning an n-th wiring layer, the pattern density of the wiring layer is set to a certain value or more. It is characterized in that a dummy wiring layer which does not connect semiconductor elements is simultaneously patterned.

[0008]

According to the present invention, since the dummy wiring layer is provided, the amount of the resist serving as the supply source of the deposit can be maintained at a certain value or more during the dry etching. This gives L
It is possible to reduce variations in line width and variations in cross-sectional shape within the SI chip. Further, since the dummy wiring layer is arranged in a place where the pattern density is low, it is possible to recover the flatness lost due to the density of the pattern.

[0009]

EXAMPLE An example of the method for forming a multi-layer wiring according to the present invention will be described with reference to FIG. First, when patterning a polysilicon wiring on a semiconductor substrate (11), a polysilicon wiring layer (1
In addition to 2), dummy polysilicon wiring layer (121)
Are simultaneously patterned. The dummy polysilicon wiring (121) is not used for connection between elements or the like, and is arranged at a place where the pattern density is low (hereinafter,
The same). Then, the polysilicon wiring layer (12, 1
21), a first interlayer insulating film (13) such as a BPSG film is formed, and similarly, the first Al wiring layer (1) is formed.
4) and a dummy first Al wiring layer (141) are formed. Further, a second interlayer insulating film (1) such as a SiO ₂ film is formed so as to cover the first Al wiring layer (14, 141).
5) is formed, and similarly, a second Al wiring layer (16) and a dummy second Al wiring layer (161) are formed. Finally, a protective film (17) such as a SiN film is formed so as to cover the second Al wiring layer (16, 161).

Next, regarding the presence or absence of the dummy wiring layer, Al
The results of a comparative experiment of variations in the line width of the wiring layer within the LSI chip are shown below. The pattern density is LSI
The average density in the chip is shown. The resist line width is 1.2 μ in each case. Pattern density Al line width (average) Al line width (3σ) Without dummy About 15% 1.4μ ± 0.15μ With dummy About 30% 1.25μ ± 0.08μ In this way, the dummy Al wiring layer is provided. In this case, the value of 3σ showing the variation of the line width was as small as ± 0.08 μ, and the cross-sectional shape was almost constant. It is considered that this is because the increased pattern density ensures the amount of resist that is a supply source of deposits during etching. Generally, in the dry etching process, deposition of a polymer or the like is attached to the side wall of the wiring layer to stabilize the etching, but a certain amount of supply source is required for this purpose. Because. The above is an example of the Al wiring layer, but also for the polysilicon wiring, a sufficient effect was obtained when the pattern density was increased to 25% or 45% by introducing the dummy wiring layer. Therefore, in order to stabilize the shape and line width of the wiring layers, it is necessary to provide a considerable amount of dummy wiring layers, but from the above experimental results, it is sufficient to set approximately 30% or more as a standard. it is conceivable that. Further, the dummy wiring layer is inserted in a place where the pattern density is low, so that the pattern density of the entire LSI chip is eliminated.

Further, according to the present invention, as shown in FIG. 1, in each layer, a dummy polysilicon wiring layer (12
1), as a result of forming the first Al wiring layer (141) and the second Al wiring layer (161), the flatness can be secured more anywhere in the chip. This allows
It is possible to stably manufacture an LSI adopting a multilayer wiring structure.

[0012]

According to the present invention, since the dummy wiring layer is provided, the amount of the resist serving as the supply source of the deposit can be maintained at a certain value or more during the dry etching. As a result, it is possible to reduce variations in line width and variations in cross-sectional shape within the LSI chip.

Further, since the dummy wiring layer is arranged in the place where the pattern density is low, it is possible to recover the flatness lost due to the sparse and dense patterns and to further advance the multilayer wiring. Furthermore, according to the present invention, since it is only necessary to insert a dummy wiring layer in pattern design, there is an advantage that it is not necessary to change the manufacturing process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a method for forming a multilayer wiring according to the present invention.

FIG. 2 is a cross-sectional view illustrating a conventional method of forming a multilayer wiring.

FIG. 3 is a cross-sectional view illustrating a conventional method of forming a multilayer wiring.

FIG. 4 is a cross-sectional view illustrating a conventional method of forming a multilayer wiring.

Claims (2)

[Claims] 1. A method for forming a multilayer wiring on a semiconductor substrate, wherein when patterning an n-th wiring layer, a pattern density of the wiring layer is set to a certain value or more,
A method for forming a multi-layer wiring, which comprises simultaneously patterning a dummy wiring layer which does not connect semiconductor elements. 2. The method for forming a multilayer wiring according to claim 1, wherein the dummy wiring layer is provided so that the pattern density of the wiring layer on the semiconductor substrate is about 30% or more.