JPH06326992A - Video signal correcting device - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to reduce the circuit scale of a retouching circuit when an uncorrectable error occurs in a variable length coded video signal after orthogonal transformation. [Configuration] When an uncorrectable error occurs in the recording / reproducing device 1, the error correcting device 2 supplies the error position information EN to the error code inserting device 3. The error code inserter 3 replaces the DC signal (9 bits) of the DCT block in which an error exists with "-256" which does not normally occur, and replaces the variable length code word with the block end code first after the DC signal. The modifying unit 9 outputs the output signal of the inverse orthogonal transformer 6 (8 bits).
Detect a sample value of "-128" that does not usually occur in and modify the sample value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal retouching device used for high efficiency coding of a video signal for recording / reproduction or transmission / reception.

[0002]

2. Description of the Related Art In recent years, D1, D2 and D3 video tape recorders (hereinafter abbreviated as VTR) for digitizing and recording and reproducing video signals have been developed. Further, as a consumer device, a video floppy capable of recording and reproducing a digital still image and a VTR capable of recording a digital moving image are being developed. An example of the development of a consumer digital VTR is the Journal of the Television Society (Vol. 45 No. 7 p.
p813 to 819 1991). In this consumer digital VTR, the redundancy of a video signal is recorded by compressing the data amount to about ⅕ using high efficiency coding.

A conventional video signal modifying device will be described below. FIG. 5 is a block diagram of a video signal recording device. FIG. 2 is a block diagram of a conventional video signal adjusting device. FIG. 7 is a diagram for explaining the operation of the blocker in FIG.
8 is a diagram for explaining the output signal of the orthogonal transformer in FIG. 1, and FIGS. 9 and 10 are diagrams for explaining the operation of the arrayer in FIG.

In FIG. 5, reference numeral 50 denotes an input terminal to which a digitized video signal is input, 51 denotes a video signal input to the input terminal 50 temporarily stored in a memory 52, and five locations where the video signal of one frame is different. To 6 DCT blocks (1 DCT block is composed of adjacent 8 × 8 pixels) to form one video segment. Reference numeral 53 is an orthogonal transformer for performing a two-dimensional discrete cosine transform (hereinafter abbreviated as DCT) on the output signal of the blocker 51, 54
Is a variable-length encoder that assigns the zero-run number of 63 AC components output from the orthogonal transformer 53 and the subsequent amplitude value to a predetermined variable-length codeword, and 55 is the output of the variable-length encoder for each video segment An arrayer for re-storing the signal in the prescribed sync block format, 56 is an error correction code calculator for adding an error correction code to the output signal of the arrayer, 57
Is a recording and reproducing device.

In FIG. 6, reference numeral 58 denotes an error corrector for correcting an error occurring in the recording / reproducing system existing in the signal output from the recording / reproducing device 57. When the error exceeds the correction capability (uncorrectable). If not), the error position is output. 59
Is an EOB inserter that inserts a block end code (hereinafter abbreviated as EOB) when an uncorrectable error occurs.
Is an inverse arrayer for organizing the variable length code of one video segment stored in the sync block format into variable length code words for each DCT block. The output signal of the inverse array device 60 is converted into the original zero run and amplitude value by the variable length decoder 61. 62 is an inverse orthogonal transformer that performs two-dimensional inverse DCT, and 63
Is a modifier that modifies the sample value of the DCT block in which the error indicated by the error corrector 58 exists. Reference numeral 64 denotes an inverse blocker that stores the sample values supplied from the modifier 63 in the memory 65 and then rearranges the video signals. The signal restored to the original video signal by the deblocker 64 is an output terminal. It is output to 66.

The operation of the conventional video signal modifying device constructed as described above will be described below.

First, the recording operation will be described. Entering
The video signal input to the input terminal 50 is stored in the memory 52.
Be done. The signal stored in the memory 52 is an 8-bit sample
Luminance sampled at a ring frequency of 13.5 MHz
Degree signal (Y signal) and also sampling with 8 bits
Two types of frequencies sampled at 3.375 MHz
Difference signal (C_RAnd C_BSignal). Quantization value is 2
Shown in complement -127 (binary 10000001) to 126 (0111111
It is a value in the range of 0). The blocker 51 has a memory 52
The video signal stored in the
Block into locks. And horizontal 7 as shown in FIG.
One frame image composed of 20 pixels x 480 vertical pixels
6 DCT blocks (Y signal is
4DCT block and C_RSignal and C_BSignal is 1 DCT each
1 video segment (30DCT block)
)). The blocker 51 is one video segment
Video signal in increments of Y → Y → Y → Y → C _R→ C_BDC
It outputs to the orthogonal transformer 53 in order of T block. Orthogonal transformation
The converter 53 extends horizontally to the input DCT block.
And two-dimensional DCT in the vertical direction. The orthogonal transformer 53 is 2
Dimensional DCT result is a DC signal with low horizontal and vertical frequency components
No. (Indicated in 2's complement, 9-bit value in the range -255 to 254
Value) to high frequency AC component (polarity 1 bit and amplitude)
Variable length encoder 54 in the order of 8 bits (total 9 bits)
Output to. Figure 8 shows the output order of the two-dimensional DCT results.
You

The AC component supplied to the variable length coder 54 counts the number of consecutive zero runs of the input signal for each DCT block, and combines the number of zero runs and the non-zero value (amplitude value) after that to the variable length code. Converted to words. This variable-length code word is a code in which a zero-run number and an amplitude value are assigned to shorter code words for combinations with higher occurrence probabilities. By using this variable length code, it is possible to reduce the entropy of the transmission signal. The variable-length codeword has a minimum of 3 bits and a maximum of 16 bits, and the EOB indicating the end of the DCT block is 4
It is a code word of bits. Each variable-length codeword is a code that can be uniquely restored when viewed from the LSB. The EOB is added when the values of the DCT block are all zero, or after the last AC value (non-zero value) is converted into a variable length codeword and is connected to the codeword. The variable-length coded codeword is output to the arrayer 55.

The signals input to the array unit 55 are rearranged in a signal arrangement of a prescribed sync block format in units of one video segment. This sync block format will be described in detail. The 30 DCT blocks No. 0 to No. 29 supplied to the array unit 55 are 6DC.
A sync block is formed for each T block. This is shown in FIG. 5 sync blocks have a data width of eight bits, each sync block consists of the region of 14 bytes of Y signal area 4 and 10 bytes of color difference signals (C _R, C _B signals) region two 76 bytes. The variable-length codeword encoded by the variable-length encoder 54 is the five sync blocks (sy
It is written separately in ncblock0 to syncblock4). The sync blocks are numbered as shown in FIG. 9, and the blocks 4, 5, 10, 11, 16, 17, 22, 23, 28,
29 is a 10-byte block (fixed area), and the other is a 14-byte block (fixed area). In this block, the code word data of the DCT block corresponding to the number is written preferentially. Figure 1
Reference numeral 0 is a block diagram of each block. Data (10 bits) of the DC signal of the DCT block corresponding to the number is written at the beginning of each block, and subsequently, variable length codewords of AC components are written in order from the LSB. In the example of FIG. 10, the variable-length codeword data amount of the AC component is 102 bits or more in DCT0 and DCT2, and therefore overflows from the fixed area. In the write procedure to the sync block, first, the DC signal of DCT0 is written in the block 0, and subsequently the variable length codeword data of the AC component of DCT0 is written in order. At this time, when the area of the block 0 is full, the writing of the data of DCT0 is temporarily suspended, and then the data of the DCT1 is written in the block 1. Even if all the code word data of DCT1 is written and there is still an empty area in block 1, this empty area is skipped and the next DC
The data of T2 is written from the beginning of block 2. In this way, first, all blocks belonging to the sync block are filled with the variable length code word data of the DCT block corresponding to the number. Then, since all the data of DCT0 has not yet been written, the remaining codeword data (high-frequency data) is written in the empty area of block 1.
When all the data of DCT0 has been written, the data processing of DCT2 in which all the codeword data has not been written yet is started. As shown in FIG. 10, if the block 1 still has an empty area, the remaining codeword data is written from that area. Write the data. By repeating these operations, the data of each DCT block is written in the sync block (in the order of DCT numbers, the data is written in order from the vacant area of the block with the smallest number). High frequency data of the same macroblock is preferentially written in each sync block. Then, if there is still an area to be written, the high frequency data of another sync block is written. As shown in FIG. 10, the code word data of the DCT block having the same number as the block number is converted into the low-frequency data (L
AC), codeword data written in blocks of other numbers are called high frequency data (HAC).

The signal arranged in the signal array of the predetermined sync block format by the array unit 55 is the error correction code calculator 5
At 6, an error correction code is added. Error correction code calculator 5
In 6, the error correction code is added with 135 sync blocks as one unit (correction block). An error correction code is added to 8 bytes for a horizontal 76 byte signal, and an 11 byte error correction code is added to a vertical 135 byte signal.
Further, the error correction calculator 56 adds 1 byte of a flag indicating whether or not there is an error in the supplied signal of 1 sync block (77 bytes). Normally, this flag is recorded with all "0" indicating that there is no error during recording. However, when the data is directly input to the error correction code calculator 56 in a compressed state (not shown in the figure), an error may occur in the transmission system. In this case, the flag is recorded with a value indicating that an error exists. The output signal of the error correction calculator 56 is recorded in the recording / reproducing device 57.

Next, the operation during reproduction will be described. The signal reproduced from the recording / reproducing device 57 is supplied to the error corrector 58. The error corrector 58 detects an error portion generated in the recording / reproducing system from the error correction code added at the time of recording and corrects the error. If the number of errors is within the correction capability, all the errors generated in the recording / reproducing system are corrected and output to the EOB inserter 59. At this time, the flags are all output as "0" indicating that no error exists. If the error occurrence frequency exceeds the error correction capability and cannot be corrected, the position in the sync block in which the error occurs and the position in the frame of the image signal are calculated, and the EOB inserter 59 and the modifier 6
Output to 3. At this time, the flag is rewritten to the content indicating that an error exists.

If there is an uncorrectable error, the EOB inserter 59 performs the following processing using the error position information supplied from the error corrector 58. (1) EOB is added to the last variable length codeword in the DCT block in which an error exists. However, the error is DC
If it is at the signal position, no processing is performed. (2) EOB is added to the low frequency band data of the DCT block in which no error exists.

When there is no error, the EOB inserter 59 outputs the input signal as it is to the inverse arrayer 60.

If there is an error even with one bit in the variable length code word, it becomes impossible to decode the variable length code after the error. However, although the high frequency data is discarded (the high frequency component of the video signal is lost) by the above processing, the variable length codewords of all DCT blocks can be decoded. The output signal of the EOB inserter 59 is supplied to the reverse arrayer 60. The inverse arrayer 60 connects the DC signals of 30 DCT blocks stored in the five sync blocks and the variable length codewords of the AC components for each DCT block to which the variable length decoder 61 is connected.
Output to. The variable length decoder 61 converts this signal into the original zero value and the amplitude value, and outputs it to the inverse orthogonal converter 62. The inverse orthogonal transformer 62 performs a two-dimensional inverse DCT on the input signal, and the modifier 6
Output to 3. Based on the uncorrectable error position information supplied from the error corrector 58, the modifying unit 63 replaces the sample value of the DCT block in which the error exists with the sample value of the same position one frame before to realize the modification. . Then, the modification result is output to the deblocking unit 64. The deblocking unit 64 stores the input signal in the memory 65, resynthesizes the video signal of one frame, and outputs it to the output terminal 66.

[0015]

However, in the above configuration, the uncorrectable error position information detected by the error corrector is supplied to the retouching device to realize the retouching. for that reason,
The position of the video signal of the DCT block in which an uncorrectable error has occurred is obtained, and further, the processing delay of the inverse array device, variable length decoder, and inverse orthogonal transform device sandwiched by the position information is calculated and the correction device Had to be transmitted to. As a result, there has been a problem that the circuit configuration of the modifier is complicated, and eventually the circuit scale is increased.

The present invention solves the above-mentioned problems of the prior art, and it is easy to eliminate the need to newly add a signal line to a post-stage reconditioner to transmit the position information of the DCT block in which an uncorrectable error has occurred, and it is simple. It is an object of the present invention to provide a video signal modification device having a configuration capable of realizing modification with various circuits.

[0017]

To achieve this object, a video signal adjusting device of the present invention determines an uncorrectable error position for each recording area from an error correction code added to a signal reproduced from a recording / reproducing device. An error corrector that detects and outputs error position information, and at the same time changes the flag to a code indicating that an error remains, and if an uncorrectable error exists, the DC component of the recording area where the uncorrectable error exists is detected. The error code inserter that replaces the code word with a value that does not normally occur and at the same time corresponds to the first AC component the variable length code word to the block end code word, and the flag output from the error corrector has an error in the recording area. If this is the case, variable length decoding is performed using the AC component up to the first block end codeword that appears in the recording area, or there is no block end codeword in the recording area. In case of variable length decoding using only the code word for the AC component contained in the recording area, if the error does not exist, the code word stored in the gap of the recording area corresponding to another block is also used. Variable-length decoder for variable-length decoding, an inverse orthogonal transformer for converting the output signal of the variable-length decoder into a sample value, and detection of whether the output signal of the inverse orthogonal transformer has a value that does not normally occur It has a configuration with an error code detector and a modifier that corrects the sample value by replacing it with an adjacent sample value in the past or in the future when the error code detector detects that the sample value does not normally occur. is doing.

[0018]

With the above-described structure, the present invention replaces the DC signal of the DCT block containing the uncorrectable signal with a value that does not normally occur, and at the same time, first replaces the variable length code word with the block end code following the DC signal. The other DCT blocks add a block end code to the low frequency data. As a result, in the output signal of the inverse orthogonal transform, all the sample values of the DCT block containing uncorrectable errors become sample values that do not normally occur. That is, by detecting this value, it is not necessary to directly transmit the error position information from the error corrector, and the circuit scale can be reduced.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a video signal modifying device according to an embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the error code inserter. 3 and 4 are block diagrams of the modifying unit.

In FIG. 1, reference numeral 2 denotes an error corrector for correcting an error generated in a recording / reproducing system by using an error correction code added to a signal output from the recording / reproducing device 1. When the error cannot be corrected. Outputs the error position information. Reference numeral 3 is an error code inserter for inserting an error code and EOB when an uncorrectable error occurs, and 4 is an inverse array for rearranging the variable length code of one video segment stored in the sync block format for each DCT block. The output signal of the inverse array unit 4 is converted into the original zero run and amplitude value by the variable length decoder 5. Reference numeral 6 is an inverse orthogonal transformer that performs two-dimensional inverse DCT, 7 is an error code detector, and 8 is a modifier. Reference numeral 9 is a correction unit composed of the error code detector 7 and the correction unit 8. An inverse blocker 10 stores the signal modified by the modifying unit 9 in the memory 11 and rearranges it into a video signal in units of one frame. The output signal of the deblocker 10 is supplied to the output terminal 12.

In FIG. 3, reference numeral 20 designates an input terminal of the modifying section, 2
1 is an error flag detector, 22 is an error flag detector 2
A switch that is switched by the output signal of 1, a pixel memory 23, and an output terminal of the retouching unit.

In FIG. 4, reference numeral 30 denotes an input terminal of the modification section, 3
1 is an error flag detector, 32 is an error flag detector 3
A switch that is switched by the output signal of 1, 33 is a one-frame memory, and 34 is an output terminal of the modifying unit.

The operation of the video signal modifying device of this embodiment having the above-mentioned structure will be described below.

Since the operation at the time of recording is the same as the conventional example, it is omitted here. The operation during reproduction will be described in detail.

The signal reproduced from the recording / reproducing device 1 is supplied to the error correcting device 2. The error corrector 2 detects an error portion generated in the recording / reproducing system from the error correction code added at the time of recording and corrects the error. If the errors are within the correction capability, all errors occurring in the recording / reproducing system are corrected and output to the error code inserter 3. At this time, the flags are all output as "0" indicating that no error exists. If the number of errors exceeds the error correction ability and cannot be corrected,
The position information EN in the sync block in which the error has occurred is output to the error code inserter 3. At this time, the flag is rewritten to the content indicating that an error exists and is output.

When the flag indicates that an error remains, the error code inserter 3 performs the following processing using the error position information EN supplied from the error corrector 2. (1) Set the DC signal of the DCT block in which an error is present to "-25
6 "(binary number 100000000) and at the same time replace the first variable length codeword following the DC signal with EOB. (2) EOB is added to the low band data of the DCT block in which no error exists.

The variable-length code word cannot be decoded if there is an error even with one bit, but the above processing discards the high-frequency data of the DCT block in which no error exists (the high-frequency component of the video signal is lost). However, it becomes possible to decode variable length code words of all 30 DCT blocks. The output signal of the error code inserter 3 is supplied to the reverse arrayer 4.
Inverse arrayer 4 stores 30D stored in 5 sync blocks
The DC signals for the CT blocks and the variable length codewords of the AC components are connected to each other for each DCT block and output to the variable length decoder 5. The variable length decoder 5 converts this signal into the original zero value and amplitude value, and outputs it to the inverse orthogonal converter 6. The inverse orthogonal transformer 6 performs a two-dimensional inverse DCT on the input signal and outputs it to the modifying unit 9.

As a result of the above, if the flag indicates that an error exists, the DCT block in which the error exists is DC.
Only the signal (error code) is decoded and the other DCT
The block performs decoding using LAC only. If the flag indicates that there is no error, the variable length code is also decoded using the HACs assigned to other DCT blocks.

The input signal to the inverse orthogonal transformer 6 of the DCT block whose error cannot be corrected is 63 when the DC signal is "-256".
All AC components are "0". Therefore, the inverse orthogonal transformer 6
The output signal of is all "-128" in 8x8 pixels. Because there are no horizontal and vertical high frequency components, the DC signal components are all sampled values. The DC signal after orthogonal transformation is 9 bits, but the sample value of the video signal is 8 bits, so the input signal "-256" of the inverse orthogonal transformer 6 is the output value "-128" of the inverse orthogonal transformer 6. Equivalent to. This "-128" value is not assigned to the sample value at the time of recording.

FIG. 3 shows a first configuration example of the modifying unit 9. The signal input to the correction unit 9 is supplied to the error code detector 21 and the switch 22. The error code detector 21 is "-
This is a circuit that detects 128 "(binary number 10000000). Since the negative maximum value" -128 "is not assigned to the sample value of the video signal, the value in the signal supplied to the retouching unit 9 during reproduction is" -128 "
Can be judged as the signal of the DCT block to be modified. When "-128" is detected by the error code detector 21,
The switch 22 is switched to the N side. As a result, output terminal 2
Through 4, the deblocking unit 12 is supplied with the sample value one pixel before on the same line instead of the incorrect sample value. If the error is continuous, the switch 22 remains switched to the N side while the error code (-128) is continuously detected, so that the latest sample value that is not an error is continuously output. .

FIG. 4 shows a second configuration example of the modifying section 9. The signal input to the correction unit 9 is supplied to the error code detector 31 and the switch 32. Error coat detector 31
When 128 "is detected, the switch 32 switches to the N side.
As a result, the sample value at the same position one frame before is supplied to the deblocking unit 12 via the output terminal 34, instead of the incorrect sample value. Non-erroneous sample values are supplied to the deblocker 10 via the output terminal 34. At the same time, the sample value at the same position in the frame memory 33 is overwritten in the stored address. When errors occur successively at the same position by this processing, sample values that have not been output in the past are output. One pixel memory 23 for still images is better to modify using frame memory 33.
It has the characteristic of less deterioration than the modification using, but the circuit scale increases.

The deblocker 10 stores the input signal in the memory 1
The original 1-frame video signal is reconstructed by storing in 1 and rearranging the signals, and output to the output terminal 12.

As described above, the video signal modifying apparatus of the present invention detects the uncorrectable error position for each recording area from the error correction code added to the signal reproduced from the recording / reproducing device, and outputs the error position information, At the same time, an error corrector that changes the flag to a code indicating that an error remains, and if there is an uncorrectable error, replaces the DC component of the recording area where the uncorrectable error exists with a code word of a value that does not normally occur. At the same time, the error code inserter that replaces the variable length code word with the block end code word corresponding to the first AC component and the flag output from the error corrector indicates that an error exists in the recording area. Variable length decoding is performed using the AC component up to the first appearing block end codeword, or if the block end codeword does not exist in the recording area, it is included in the recording area. A variable-length decoder that performs variable-length decoding using only the codewords for the stream components, and also performs variable-length decoding using the codewords stored in the gaps in the recording areas corresponding to other blocks if it indicates that no error exists. , An inverse orthogonal transformer that converts the output signal of the variable length decoder into a sample value, an error code detector that detects whether the output signal of the inverse orthogonal transformer has a value that does not normally occur, and an error code detection If the sampler detects that the sampled value is a value that does not normally occur, replace the adjacent sampled value in the past or in the future to adjust the sampled value. It is possible to increase the number and eliminate the need for transmission from the error corrector to the modifier. As a result, the configuration of the modifying circuit can be greatly simplified. Further, it becomes possible to make the timing control circuit for modifying the modified sample points based on the error position information very simple.

Although the DC signal of the DCT block including the uncorrectable signal is replaced with "-256" in this embodiment, another signal not actually used as the DC signal, for example, "25" is used.
6 ", etc. may be used. Also, the modifier configuration does not replace the sample value one frame before, but replaces the sample value one frame after or one field after, or the average value of sample values before and after the frame or field. And so on.

[0035]

As described above, according to the present invention, the uncorrectable D
The error DCT block can be detected without directly transmitting the position information of the CT block to the modifier. as a result,
The timing generator circuit of the modifier is very simple, and the circuit scale of the modifier circuit can be reduced. Its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video signal modifying device according to an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the error code inserter of the embodiment.

FIG. 3 is a block diagram showing a first internal configuration example of a modifier 8 in the same embodiment.

FIG. 4 is a block diagram showing a second internal configuration example of the reconditioner 8 in the same embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional video signal recording device.

FIG. 6 is a block diagram showing a configuration of a conventional video signal modifying device.

FIG. 7 is an operation explanatory diagram of the blocker 51 in FIG.

8 is an explanatory diagram showing the order of output signals of the orthogonal transformer 53 in FIG.

FIG. 9 is an explanatory diagram showing the structure of a sync block.

FIG. 10 is an explanatory diagram showing a sync block format.

[Explanation of symbols]

 1 Recorder / Reproducer 2 Error Corrector 3 Error Code Inserter 4 Inverse Aligner 5 Variable Length Decoder 6 Inverse Orthogonal Transformer 7 Error Code Detector 8 Modifying Device 9 Modifying Unit 10 Inverse Blocking Device 11 Memory 12 Output Terminal

Claims (3)

[Claims] 1. A blocker that collects a plurality of adjacent sample values of an input video signal to form a block, an orthogonal transformer that orthogonally transforms each block to transform it into an orthogonal component, and the orthogonal. A variable-length encoder for converting the converted signal in the block into a fixed-length DC component, a variable-length encoded AC component, and an end codeword indicating the end of the block, and an output from the variable-length encoder. A recording area of a predetermined size is set in the signal for each block, the DC component of the block corresponding to each recording area is stored at a predetermined position of the recording area, and the AC component corresponding to the recording area is stored. Variable length code words and block end code words are recorded until the recording area is filled, and if all variable length code words and end code words of the block corresponding to the recording area cannot be recorded, An arrayer that stores a codeword that cannot be recorded or a part of the codeword in a gap between recording areas of other blocks, and an error correction code is added to each of the plurality of recording areas supplied from the arrayer. An error correction code calculator that adds a flag indicating whether or not an uncorrectable error exists for each correction area, a recording and reproducing device that records and reproduces an output signal of the error correction code calculator, and the recording and reproducing device. An error corrector that detects an uncorrectable error position for each recording area from the error correction code added to the reproduced signal, outputs error position information, and simultaneously changes the flag to a code indicating that an error remains, When an uncorrectable error exists, the DC component of the recording area in which the uncorrectable error exists is replaced with a code word of a value that does not normally occur, and at the same time, the variable length code word corresponding to the first AC component is used as the block end code. When the flag output from the error corrector indicates that there is an error in the recording area, the error code inserter that replaces the word is used to change the AC component up to the first block end code word that appears in the recording area. If long block decoding is performed, or if there is no block end codeword in the recording area, variable length decoding is performed using only the codeword for the AC component included in the recording area. Variable-length decoder that performs variable-length decoding also using the codewords stored in the gaps of the recording areas corresponding to the blocks, an inverse orthogonal transformer that converts the output signal of the variable-length decoder into a sample value, and the inverse An error code detector that detects whether or not the output signal of the orthogonal transformer has a value that does not normally occur, and if the sample value is detected by the error code detector as a value that does not normally occur, Or a video signal retouching device having a retouching device that retouches a sampled value by replacing it with an adjacent sampled value in the future. 2. A modification process is performed by replacing a sample point to which a sample value, which does not normally occur, is assigned with a sample value which is not an error on the same line as the detected error code. 1. The recording signal adjusting device according to 1. 3. The retouching process is performed by replacing sample points to which sample values are not normally generated, with sample values before or after several frames or fields that are not in error at the same position on the screen. Claim 1 characterized by
Record modification device described.