JPH06324886A - Interrupt management method and interrupt management circuit - Google Patents

Abstract

(57) [Summary] [Object] The present invention provides a plurality of interrupt levels, an interrupt mask for controlling whether or not to permit an interrupt for each interrupt level, and a plurality of interrupt requests for each interrupt level. The present invention relates to an interrupt management method in a data processing device having the above, and efficiently processes other interrupt requests of the same or higher interrupt level during interrupt processing at a certain interrupt level. [Configuration] When another interrupt request occurs during processing at a certain interrupt level, the interrupt information currently being processed is stacked up to a predetermined number in a stack register, and when a predetermined stack number (max) is reached, Raise the interrupt level to prevent other interrupts from entering, the number of interrupt processes currently stacked is completed, and the number of processes stacked in the stack register is the specified number (min). When this occurs, the higher interrupt level set above is lowered to manage the new next interrupt request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a plurality of interrupt levels, an interrupt mask for controlling whether or not an interrupt is permitted for each interrupt level, and a plurality of interrupt requests for each interrupt level. The present invention relates to an interrupt management method in a data processing device.

Recently, Integrated Services Digital Network (ISDN),
High-speed, high-quality networks such as FDDI are widespread,
In a network controller for such a high-speed network, even if the highest level interrupt such as an error interrupt from a terminal device or an interrupt for instructing the next processing is included, it occurs in the network controller. It is required to efficiently process lower level interrupt requests for data communication between a terminal device and a network, such as opening of a data storage area and restart of a monitoring timer.

[0003]

2. Description of the Related Art FIG. 5 is a diagram for explaining a conventional interrupt management method, FIG. 5 (a) shows a configuration example of a conventional interrupt management circuit, and FIG. Is shown.

In the control board 1 of the network control device such as the digital integrated service network (ISDN) and the fiber distributed data interface network (FDDI) shown in FIG. 5A, for example, the microprocessor 2 Is used to transfer data between the terminal device and a network (not shown) based on an interrupt request accompanying input / output processing from the terminal device (not shown).

In this case, for reasons such as ease of processing, each interrupt request is divided into several levels, and an interrupt request Lij of a certain interrupt level Li
Since the interrupt mask was set for the interrupt requests with the interrupt level Li or lower at the time of entering, all the interrupts with the interrupt level Li or lower while the interrupt request Lij is running. The process of not accepting the request is performed.

[0006]

Therefore, in the above-mentioned conventional technique, as shown in FIG.
After Lij (for example, L11 in the illustrated example) is accepted by the microprocessor 2, interrupts for interrupt requests with interrupt levels below the interrupt request Lij (for example, illustrated interrupt requests L12, L13, etc.) are masked. Therefore, there was a problem that interrupts below the interrupt request Lij were missed.

For example, as described above, in the control board 1, if another interrupt request is input, an interrupt which is troublesome for the control board, such as an error interrupt from a terminal device (not shown), an interrupt for instructing the next process, etc. In the state where the highest level interrupt such as the above is present, the lower level generated in the control board 1, for example, opening and monitoring the data storage area required for data communication between the terminal device and the network. Since the interrupt request regarding the restart of the timer is rejected, there is a problem that the movements of them cannot be efficiently observed.

Further, each time an interrupt is input,
It is necessary to take a procedure to release the interrupt mask set above each time the interrupt mask is set and the interrupt processing is completed. There is a problem that the processing speed of the control device becomes slow.

In view of the above-mentioned conventional drawbacks, the present invention provides a data processing apparatus having a plurality of interrupt levels, an interrupt mask for each interrupt level, and a plurality of interrupt requests for each interrupt level. It is an object of the present invention to provide an interrupt management method capable of efficiently processing other interrupt requests of the same interrupt level during interrupt processing.

[0010]

FIG. 1 is a diagram showing a configuration example of an interrupt management circuit of the present invention. The above problems are solved by the interrupt management method configured as follows.

(1) In a data processor having a plurality of interrupt levels, an interrupt mask for controlling whether or not to permit an interrupt for each interrupt level, and a plurality of interrupt requests for each of the interrupt levels , When another interrupt request with the same or higher interrupt level occurs during processing at a certain interrupt level, the interrupt information currently being processed is stacked in stack register 10 up to a specified number, and the specified stack When the number reaches the maximum (max), the level of the above interrupt mask is set to a higher level, the above other interrupts are suppressed, the processing of the interrupt processing that is currently stacked is completed, and the stack register 10 The number of processes stacked in
When the number reaches a predetermined number (min), the set higher interrupt level is lowered to manage the other interrupt request.

(2) In a data processing device having a plurality of interrupt levels, an interrupt mask for controlling whether or not an interrupt is permitted for each interrupt level, and a plurality of interrupt requests for each of the interrupt levels , Stack register for stacking multiple interrupt information
10 and the stack upper limit register 11 for instructing to stack in a predetermined number of upper limit interrupt information to the stack register 10 and the stack register 10 described above.
When the interrupt processing that has been stacked in
A stack lower limit register 12 for detecting that the stack has been stacked out of the stack register 10 and has reached a predetermined lower limit, and a stack counter for counting the number of interrupt information currently stacked in the stack register 10. 13 is compared with the value of the stack upper limit register 11, the value of the stack lower register 12 and the count value of the stack counter 13, and the count value of the stack counter 13 is indicated by the stack upper register 11. When it is detected that the value exceeds the specified value, the interrupt mask level is raised to the higher level specified by the upper interrupt mask register 16, and subsequent interrupt requests are stacked in the stack register 10 above. Are interrupted, and the interrupt process currently stacked in stack register 10 Processing to complete the, it is stacked out from the stack register 10,
When it is detected that the stack lower limit register 12 has become less than or equal to the value instructed, the upper interrupt mask is set to the lower predetermined level instructed by the lower interrupt mask register 17, and the set lower register is set. An interrupt request of level or higher is returned to the stack register 10 above.
And an interrupt control circuit 15 for controlling the stacking of the two.

(3) The stack register 10 is configured to include a plurality of stack registers 10 corresponding to the plurality of interrupt levels. (4) As the stack register 10, only one stack register including a plurality of register stages is provided, and control is performed so that stacking in is performed in order from the lower interrupt level.

(5) As the stack register 10, only one stack register including a plurality of register stages is provided, and an interrupt request to be stuck in the stack register 10 is independent of the interrupt level of the interrupt request. , Controls to stack in the order in which they occur.

[0015]

That is, in the present invention, a stack register for stacking information related to the interrupt process currently being executed is provided when, for example, an interrupt request of the same interrupt level is generated while executing a process at a certain interrupt level. Each time a new interrupt request is generated, the information related to the interrupt process currently being executed is stacked in the stack register, and the number of interrupt processes stacked in the stack register is the specified number.
When (the number is set in the stack upper limit register) is exceeded, for example, the interrupt mask of the highest level is set so that the interrupt of the higher interrupt request after that is set, and the stack register is set in the above stack register. If the number of interrupts being processed is sequentially processed, stacked out, and the number of interrupts stacked in the stack register falls below a specified number (this number is set in the stack lower limit register), the above setting is made. The level of the highest interrupt mask that has been set is set to, for example, the lowest level so that the processing of interrupt requests that occur thereafter can be executed.

By performing such control, when, for example, interrupts of the same interrupt level occur consecutively, priority is sequentially given to subsequent interrupt requests. Until the interrupt process being executed is completed, all the interrupt processes that occur next are suppressed, and there is an effect that the problem that efficient interrupt process cannot be performed can be solved.

By providing the stack register for each of a plurality of interrupt levels, it is possible to easily recognize the state of the interrupt processing being stacked for each interrupt level.

Further, without the concept of the interrupt mask, if all interrupt requests are accepted and the number of interrupt processes stacked in the stack register reaches a predetermined number,
The acceptance of interrupt requests that occur later is stopped, the interrupt processing that is stacked is completed in sequence, and when the number of interrupt processing that is stacked out in the stack register is less than the specified number, it is restarted. ,
A new interrupt request may be accepted.

By controlling in this manner, it is possible to process the latest interrupt request with priority, without being trapped by the conventional interrupt level, and to efficiently process the interrupt processing that occurs next and next. Can be processed.

[0020]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing a configuration example of the interrupt management circuit of the present invention, FIGS. 2 to 4 are diagrams showing an embodiment of the present invention, and FIG. 2 (b) schematically shows a situation in which interrupt processing is stacked in the stack register, FIG. 3 shows another configuration example of the stack register, and FIG. An example is shown in which interrupt processing information is stacked in one stack register in the order of occurrence regardless of the interrupt level.

According to the present invention, a plurality of interrupt levels, an interrupt mask for controlling whether or not an interrupt is permitted for each interrupt level, and a data process having a plurality of interrupt requests for each interrupt level. When a new interrupt request occurs in the device, the stack register 10 that stacks the interrupt processing information (saving information) that is currently being executed, and the stack counter 1 that indicates how many interrupt information items are currently stacked
3 and when another interrupt request occurs while executing interrupt processing at a certain interrupt level, up to a predetermined number
The interrupt information currently being processed is stacked in the stack register 10, and when the number of stacks (max) specified by the stack upper limit register 11 is reached, the interrupt mask level is raised to prevent other interrupts from entering. , The number of processes that have been stacked in the stack register 10 after completion of the interrupt process that is currently stacked is the predetermined number (m
When it becomes "in", means for lowering the level of the upper interrupt mask set above and managing so as to process the next interrupt request is a means necessary for carrying out the present invention. The same reference numerals indicate the same objects throughout the drawings.

The interrupt management method of the present invention will be described below with reference to FIGS. First, as shown in FIG.
The stack register 10 stores information about the interrupt process currently being executed, for example, the contents of a plurality of registers in the microprocessor 2, when an interrupt request of the same interrupt level occurs during execution of an interrupt process. The evacuation to the position designated by the pointer (SP) 10a is repeated each time a new interrupt request is generated next time.

Then, the number of pieces of interrupt processing information stacked in the stack register 10 becomes the number set in the stack upper limit register 11 (for example, it can be arbitrarily set from a console or the like). That
When detected by the interrupt control circuit 15, the interrupt level is raised to the level of the interrupt mask specified by the operator console in the upper interrupt mask register 16 and the newly generated interrupt request is accepted by the microprocessor 2 thereafter. Do not allow

In this state, the interrupt processing stacked in the stack register 10 is processed by the microprocessor.
Each time 2 completes execution, stack register 10 stacks out, and the number of interrupt processes stacked in stack register 10 becomes less than or equal to the number specified by stack lower limit register 12 set from the operator console. Is detected by the above interrupt control circuit 15,
Lower the interrupt level to the level of the interrupt mask set in the lower interrupt mask register 17 from the console.

As a result, after that, the microprocessor 2 can accept a newly generated interrupt request. Fig. 2 schematically shows the generation of interrupt requests. For example, when an interrupt process (L11) of interrupt level 1 (LI) is being executed, an interrupt request (LI2) of the same interrupt level is generated. Then, information about the interrupt process (L11) that was executed before (saved information)
To the stack register 10, and as shown in Fig. 2 (b),
Stacked one after another.

Hereinafter, each time a new interrupt request (L1i) is generated, up to the number indicated by the stack upper limit register 11,
When the interrupt control circuit 15 detects that the stack upper limit register 11 has reached the number indicated by the stack upper limit register 11, the interrupt mask level is set to the interrupt mask level indicated by the upper interrupt mask register 16, for example, Raise it to the highest level to prevent microprocessor 2 from executing subsequent interrupt requests.

In this state, the stack register 10
The interrupt processing (L1i) that is stacked at is fetched from the top and executed, and when the execution is completed, it is stacked out from stack register 10.

Then, the number of interrupt processes remaining in the stack register 10 is equal to the stack lower limit register 12
The interrupt control circuit that the number has decreased to 1
When detected by 5, the level of the interrupt mask raised to the highest level is lowered to the mask level instructed by the lower interrupt mask register 17, for example, the lowest level ("0" level).

As a result, again, a newly generated interrupt request is fetched by the microprocessor 2 and the interrupt processing can be executed. After that, the process of the same procedure is repeated.

Therefore, according to the interrupt management method of the present invention, the stack register 10 is prepared, and the number of interrupt requests in the range indicated by the stack upper limit register 11 and the stack lower limit register 12 is kept until the stack is full. Then, when the stack becomes full, the subsequent stacks are suppressed and the interrupt processings that are stacked are sequentially executed. When the number becomes equal to or less than a predetermined number, the operation of continuing the stack is repeated again.

Therefore, the interrupt request that has recently occurred can always be preferentially executed, and efficient interrupt processing can be performed. Further, it is not necessary to set and release the interrupt mask for each interrupt, so that the processing speed is improved.

Further, as long as the interrupt information stacked in the stack register 10 is valid because the masking is not performed one by one, it is always processed later, so that the information occurring in the device is processed accurately. Become so.

In the above embodiment, the stack register 10
Therefore, the interrupt request that is newly generated is stacked in the order of the interrupt levels. However, the configuration of the stack register 10 is not limited to this format. For example, as shown in FIG. As described above, multiple units are provided corresponding to the interrupt level, and the vertically divided structure corresponding to the interrupt level is provided.Interrupt processing corresponding to the higher interrupt level is stacked in the stack register 10 of the corresponding interrupt level. You may

Also in this case, the execution of the stacked interrupt process is executed from the stack in the stack register 10 corresponding to the higher interrupt level, and the same operation as that of the above-described embodiment can be performed. or,
By configuring the stack register 10 in this way, the status of the stack at each interrupt level can be accurately recognized.

The embodiment shown in FIG. 4 removes, for example, the concept of an interrupt mask by one stack register 1
Fig. 0 schematically shows a method of stacking in the order of interrupt requests that have occurred.

In the examples shown in FIGS. 2 and 3, the higher interrupt level is later stacked and processed from the higher level, but in the stack register having the configuration shown in FIG. The structure that eliminates the concept of is that the interrupt request that occurs later is stacked at the top of stack register 10, and when it becomes full, it will be executed from the processing of the interrupt request that is stacked at the top. It becomes easier and a more flexible form of interrupt handling can be constructed.

As described above, the interrupt management method according to the present invention includes, for example, a plurality of interrupt levels, an interrupt mask for controlling whether or not an interrupt is permitted for each interrupt level, and a plurality of interrupt masks for each interrupt level. In a data processing device equipped with a single interrupt request, when another interrupt request occurs during processing at a certain interrupt level, a predetermined number of interrupt information currently being processed are stacked in a stack register, and a predetermined stack is created. number
When it reaches (max), the interrupt level is raised to prevent other interrupt requests from entering, and the interrupt processing currently stacked is completed and the interrupt processing stacked in the above stack register is completed. It is characterized in that, when the number of (1) reaches a predetermined number (min), the higher interrupt level set as described above is lowered so that another new interrupt request is managed.

[0038]

As described above in detail, according to the present invention, when, for example, interrupts of the same interrupt level occur consecutively, the subsequent interrupt request is preferentially processed. As described above, until the interrupt process that is currently being executed is completed, all the interrupt processes that occur next will be suppressed, and there is an effect that the problem that efficient interrupt process cannot be performed can be solved.

By providing the stack register for each of a plurality of interrupt levels, it is possible to easily recognize the state of the interrupt processing being stacked for each interrupt level.

Further, by eliminating the concept of interrupt mask,
When all interrupt requests are accepted and the number of interrupt processes that are stacked in the stack register reaches the specified number, acceptance of interrupt requests that occur later is stopped and the interrupt processes that are stacked are completed in sequence. A new interrupt request may be accepted again when the number of interrupts that are stuck out and stuck in the stack register is less than the specified number. By controlling in this way, the conventional interrupt level Thus, the processing of subsequent interrupt requests can be processed with priority, and the processing of interrupt requests that occur successively next and next can be efficiently processed.

Therefore, it is possible to provide high-quality and high-performance interrupt processing for the above network in a network control device for processing a high-speed, high-quality network such as ISDN and FDDI.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of an interrupt management circuit of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention (No. 1).

FIG. 3 is a diagram showing an embodiment of the present invention (part 2).

FIG. 4 is a diagram showing an embodiment of the present invention (part 3).

FIG. 5 is a diagram illustrating a conventional interrupt management method.

[Explanation of symbols]

1 Data processing device, Data processing system, System 10 Stack register 11 Stack upper limit register 12 Stack lower limit register 13 Stack counter 15 Interrupt control circuit 16 Upper interrupt mask register 17 Lower interrupt mask register 2 Microprocessor interrupt level Interrupt mask Interrupt request Interrupt processing information

Claims (5)

[Claims] 1. A plurality of interrupt levels (), an interrupt mask () for controlling whether or not an interrupt is permitted for each interrupt level, and a plurality of interrupt requests () for each interrupt level (). In a data processing device equipped with, while processing at an interrupt level (), the same or
Other interrupt requests at higher interrupt level ()
When () occurs, the interrupt information () currently being processed is stacked in the stack register (10) up to the specified number,
When the specified number of stacks (max) is reached, the level of the above interrupt mask () is set to a higher level to prevent the above other interrupts from entering and the processing of the interrupt processing currently stacked is completed. When the number of processes stacked in the stack register (10) reaches a predetermined number (min), the higher interrupt level () set above is lowered to process the other interrupt request (). An interrupt management method characterized by managing as follows. 2. A plurality of interrupt levels (), an interrupt mask () for controlling whether or not an interrupt is permitted for each interrupt level, and a plurality of interrupt requests () for each interrupt level (). In a data processing device equipped with, a stack register (10) that stacks a plurality of interrupt information () and an instruction to stack a predetermined number of interrupt information () at the upper limit into the stack register (10). The stack upper limit register (11) and the interrupt processing stacked in the stack register (10) are completed, and the stack register (10) is stacked out and the lower limit is reached. Stack lower limit register (12) to detect and the stack register (10) above
Stack counter (13) that is counting the number of interrupt information () currently stacked in the stack, the value of the stack upper limit register (11), the value of the stack lower limit register (12), and the stack counter ( When it is detected that the count value of the stack counter (13) exceeds the value indicated by the stack upper limit register (11) by comparing with the count value of 13), the interrupt mask () level To
Raise it to a higher level specified by the upper interrupt mask register (16) to prevent subsequent interrupt requests () from being stacked in the stack register (10) above, and are currently stacked in the stack register (10). Interrupt processing has completed the sequential processing and is stuck out from the stack register (10), and the stack lower limit register (12)
When it is detected that the value is less than or equal to the value instructed by, the upper interrupt mask () is set to the lower predetermined level instructed by the lower interrupt register (17), and the lower level set above is set. Interrupt request () of
An interrupt management circuit comprising: an interrupt control circuit (15) for controlling the stack register (10) to be stacked. 3. The interrupt management according to claim 2, wherein the stack register (10) is provided with a plurality of stack registers (10) corresponding to the plurality of interrupt levels (). circuit. 4. The stack register (10) is provided with only one stack register consisting of a plurality of register stages, and is controlled so as to be sequentially stacked in from a lower interrupt level (). The interrupt management circuit according to Item 2. 5. The stack register (10) is provided with only one stack register including a plurality of register stages, and the interrupt request () for stacking into the stack register (10) is the interrupt request (). 3. The interrupt management circuit according to claim 2, wherein the interrupt management circuit is controlled so as to be stacked in the order of occurrence regardless of the interrupt level ().