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JPH06318595A - Method for manufacturing wiring structure of semiconductor integrated circuit - Google Patents

Method for manufacturing wiring structure of semiconductor integrated circuit

Info

Publication number
JPH06318595A
JPH06318595A JP10713993A JP10713993A JPH06318595A JP H06318595 A JPH06318595 A JP H06318595A JP 10713993 A JP10713993 A JP 10713993A JP 10713993 A JP10713993 A JP 10713993A JP H06318595 A JPH06318595 A JP H06318595A
Authority
JP
Japan
Prior art keywords
film
wiring
integrated circuit
semiconductor integrated
wiring structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10713993A
Other languages
Japanese (ja)
Inventor
Hideaki Ono
秀昭 小野
Tadashi Nakano
正 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP10713993A priority Critical patent/JPH06318595A/en
Publication of JPH06318595A publication Critical patent/JPH06318595A/en
Withdrawn legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】 【目的】Cu配線を用いた場合に、絶縁膜や基板への配
線材料のCuの拡散を防止すると共に配線全体の電気抵
抗が上昇することを抑制する半導体集積回路の配線構造
体の製造方法を提供する。 【構成】Si基板10の表面に4000Åの絶縁膜12
を形成する。この絶縁膜12の全表面に、膜厚200Å
のW膜14を形成する。さらにこのW膜14の表面に、
イオンエネルギー10keV、ドーズ量2×1017at
om/cm2 の窒素イオンを注入し、このW膜14の表
面に約100Åの窒化タングステン膜16を形成する。
この窒化タングステン膜16の表面にCu膜18を50
00Å形成した。
(57) [Abstract] [Purpose] When a Cu wiring is used, the wiring of a semiconductor integrated circuit prevents diffusion of Cu of a wiring material into an insulating film or a substrate and suppresses an increase in electric resistance of the entire wiring. A method for manufacturing a structure is provided. [Structure] 4000 Å insulating film 12 on the surface of Si substrate 10
To form. The entire surface of this insulating film 12 has a film thickness of 200Å
W film 14 is formed. Furthermore, on the surface of the W film 14,
Ion energy 10 keV, dose 2 × 10 17 at
Nitrogen ions of om / cm 2 are implanted to form a tungsten nitride film 16 of about 100 Å on the surface of the W film 14.
A Cu film 18 is formed on the surface of the tungsten nitride film 16.
00Å formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体集積回路(LS
I)の配線構造体の製造方法に関する。
BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (LS).
I) A method for manufacturing a wiring structure.

【0002】[0002]

【従来の技術】現在、半導体集積回路の配線の材料とし
てはAl、またはAlにSiやCuなどを添加したAl
合金が使用されている。このような配線は、Alが主な
材料として使用されているため、配線の許容電流密度は
(2〜3)×105 A/cm2以下に制限されている。
この理由は、この配線に上記許容電流密度を越える電流
を流すと、エレクトロマイグレーションによりこの配線
が断線してしまうためである。高い電流密度で電流を流
すために、配線材料としてAl中に0.1〜5%のCu
を添加したAl−Cu合金が使用されることがあるが、
エレクトロマイグレーションに対する耐性は満足できる
ものではない。しかも、許容しうる電流密度は改善され
るものの配線の比抵抗は増加し、発熱に伴う信頼性低下
の問題が生じる。
2. Description of the Related Art At present, as a wiring material of a semiconductor integrated circuit, Al or Al obtained by adding Si or Cu to Al is used.
Alloys are used. Since Al is mainly used for such wiring, the allowable current density of the wiring is limited to (2 to 3) × 10 5 A / cm 2 or less.
The reason for this is that if a current exceeding the permissible current density is applied to this wiring, the wiring will be broken due to electromigration. In order to pass a current with a high current density, 0.1 to 5% Cu is contained in Al as a wiring material.
Although an Al-Cu alloy added with may be used,
Resistance to electromigration is unsatisfactory. Moreover, although the allowable current density is improved, the specific resistance of the wiring is increased, which causes a problem of reliability deterioration due to heat generation.

【0003】また、Al−Cu合金配線の下地としてT
iNなどの窒化物膜を形成することも行われているが、
窒化物は電気抵抗が高いため、実質的な配線抵抗が高く
なるという問題がある。一方、配線の耐エレクトロマイ
グレーション性を向上させるために、Al配線やAl合
金配線に代えて、耐エレクトロマイグレーション性が高
い実質的にCuからなるCu配線を用いることが提案さ
れている。
Further, as an underlayer of Al-Cu alloy wiring, T
Although a nitride film such as iN is also formed,
Since nitride has a high electric resistance, there is a problem that the substantial wiring resistance increases. On the other hand, in order to improve the electromigration resistance of the wiring, it has been proposed to use Cu wiring, which is substantially Cu and has high electromigration resistance, instead of the Al wiring or the Al alloy wiring.

【0004】[0004]

【発明が解決しようとする課題】しかしCuは、Alに
比べるとSi(基板)又はSiO2 (絶縁膜)中へ拡散
しやすく、このためトランジスタの正常な動作を妨げる
という問題が生じる。この問題を解決するために、金属
の窒化物又は硼化物で配線を覆う構造が提案されている
(特開平1−202841号公報参照)。しかし、これ
ら窒化物又は硼化物は、Cuの拡散を防止する効果を有
する一方、 高い電気抵抗を有する。したがって、配線
が窒化物又は硼化物で覆われると配線全体の抵抗が上昇
し、低抵抗材料であるCuを配線に用いるメリットが低
減する。
However, Cu is more likely to diffuse into Si (substrate) or SiO 2 (insulating film) than Al, which causes a problem that the normal operation of the transistor is hindered. In order to solve this problem, a structure in which the wiring is covered with a metal nitride or boride has been proposed (see Japanese Patent Laid-Open No. 1-202841). However, while these nitrides or borides have the effect of preventing the diffusion of Cu, they have high electrical resistance. Therefore, when the wiring is covered with nitride or boride, the resistance of the entire wiring increases, and the merit of using Cu, which is a low resistance material, for the wiring is reduced.

【0005】本発明は、上記事情に鑑み、Cu配線を用
いた場合に、絶縁膜や基板へのCuの拡散を防止すると
共に配線全体の電気抵抗が上昇することを抑制する半導
体集積回路の配線構造体の製造方法を提供することを目
的とする。
In view of the above circumstances, the present invention prevents the diffusion of Cu into the insulating film and the substrate and suppresses the increase of the electric resistance of the entire wiring when the Cu wiring is used. An object is to provide a method for manufacturing a structure.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
の本発明の半導体集積回路の配線構造体の製造方法は、
半導体集積回路の配線構造体の製造方法において、絶縁
膜の上に金属バリア膜を形成し、該金属バリア膜の表面
に、B、N、及びCから選ばれた1種をイオン注入し、
イオン注入された前記金属バリア膜の上に配線を形成す
ることを特徴とするものである。
A method of manufacturing a wiring structure of a semiconductor integrated circuit according to the present invention for achieving the above object comprises:
In a method of manufacturing a wiring structure for a semiconductor integrated circuit, a metal barrier film is formed on an insulating film, and one surface selected from B, N, and C is ion-implanted on the surface of the metal barrier film,
A wiring is formed on the ion-implanted metal barrier film.

【0007】ここで、上記金属バリア膜の材料としては
特に限定されないが、遷移金属の中で自己拡散係数が小
さくCuの拡散防止効果に優れたW、Ta及びこれ等の
合金が好ましく、例えば、 Ta膜 W膜 Ta−W合金膜 Nb、Mo、及びTiから選ばれた一種以上の金属を
添加したTa合金膜 Nb、Mo、Pd、及びPbから選ばれた一種以上の
金属を添加したW合金膜 Nb及び/又はMoを添加したTa−W合金膜 などが好ましい。
The material of the metal barrier film is not particularly limited, but W, Ta and alloys thereof having a small self-diffusion coefficient among transition metals and an excellent Cu diffusion preventing effect are preferable. Ta film W film Ta-W alloy film Ta alloy film containing one or more metals selected from Nb, Mo, and Ti W alloy containing one or more metals selected from Nb, Mo, Pd, and Pb Film Ta-W alloy film added with Nb and / or Mo is preferable.

【0008】[0008]

【作用】本発明の半導体集積回路の配線構造体の製造方
法では、イオン注入のエネルギを制御することにより、
既に堆積された金属バリア膜表面に極めて薄い窒化物、
硼化物、又は炭化物を形成することができる。これによ
り、従来のようにバリア膜全体を窒化物、硼化物又は炭
化物で構成するよりも配線全体の抵抗を低減することが
可能になる。イオン注入によって得られたこれら窒化
物、硼化物、炭化物の結晶構造はアモルファス構造に近
く、このためこれら窒化物などの膜厚が薄くてもCuの
粒界拡散を抑えることができ、バリア性が損なわれるこ
とはない。また、窒素の反応性スパッタリングや金属硼
化物のスパッタリング法に比べて、イオン注入法では
N、B、又はCの添加量を制御しやすく、バリア膜中へ
の過度のN、B、又はCの添加を防ぐことが容易であ
る。このため、配線抵抗のばらつきを低減するという効
果もある。
In the method for manufacturing a wiring structure for a semiconductor integrated circuit according to the present invention, by controlling the energy of ion implantation,
Very thin nitride on the surface of the already deposited metal barrier film,
Borides or carbides can be formed. As a result, it becomes possible to reduce the resistance of the entire wiring as compared with the conventional case where the entire barrier film is made of nitride, boride or carbide. The crystal structure of these nitrides, borides, and carbides obtained by ion implantation is close to an amorphous structure. Therefore, even if the film thickness of these nitrides is thin, Cu grain boundary diffusion can be suppressed and the barrier property is improved. It will not be damaged. Further, as compared with the reactive sputtering of nitrogen and the sputtering method of metal borides, the ion implantation method makes it easier to control the amount of N, B, or C added, and the excessive N, B, or C content in the barrier film can be controlled. It is easy to prevent addition. Therefore, there is also an effect of reducing variations in wiring resistance.

【0009】[0009]

【実施例】以下、本発明の実施例を説明する。先ず、金
属バリア膜としてW膜を用いた配線構造体の製造方法
を、図1を参照して説明する。図1(a)に示されるよ
うに、Si基板10の表面に4000ÅのBPSG(B
orophosphosilicate glass)
の絶縁膜12を形成する。この絶縁膜12の全表面に、
1mTorrのAr雰囲気中でRFマグネトロンスパッ
タリングにより、成膜速度10Å/sで膜厚200Åの
W膜14を形成する。さらにこのW膜14の表面に、イ
オンエネルギー10keV、ドーズ量2×1017ato
m/cm2 の窒素イオンを注入して約100Åの窒化タ
ングステン膜16を形成する。この窒化タングステン膜
16の表面に、全圧2mTorrのAr雰囲気中でRF
マグネットロンスパッタリングにより、成膜速度60Å
/sで、Cu膜18を5000Å成長させる。その後、
図1(b)に示されるように、W膜14、窒化タングス
テン膜16、及びCu膜18をパターニングしてCu配
線18aを形成する。さらにその後、図1(c)に示さ
れるように、CVD法によりWを下地膜14a,16a
とCu配線18aの外面のみに選択的に400Å成長さ
せてW被覆膜20を形成する。このW被覆膜20は、試
料温度を200〜400℃にし、WF6 とH2 の混合ガ
スを成膜室へ供給し、この混合ガスの圧力を1Torr
以下にして形成する。この成膜方法によると界面反応が
律速になり、下地膜14a,16aとCu配線18aの
外面のみにWを選択成長させることができる。ここで、
この配線構造体を多層化するためには、W被覆膜20上
にSiO2 膜などの絶縁膜を形成し、この絶縁膜の上に
上記した配線構造体を同様の方法で作製すればよい。
EXAMPLES Examples of the present invention will be described below. First, a method of manufacturing a wiring structure using a W film as a metal barrier film will be described with reference to FIG. As shown in FIG. 1A, 4000 Å BPSG (B
orophosphosilicate glass)
The insulating film 12 is formed. On the entire surface of this insulating film 12,
A W film 14 having a film thickness of 200Å is formed at a film forming rate of 10Å / s by RF magnetron sputtering in an Ar atmosphere of 1 mTorr. Further, the surface of the W film 14 has an ion energy of 10 keV and a dose of 2 × 10 17 ato.
Nitrogen ions of m / cm 2 are implanted to form a tungsten nitride film 16 of about 100 Å. RF is applied to the surface of the tungsten nitride film 16 in an Ar atmosphere at a total pressure of 2 mTorr.
Deposition rate of 60Å by magnetron sputtering
/ S, the Cu film 18 is grown to 5000 Å. afterwards,
As shown in FIG. 1B, the W film 14, the tungsten nitride film 16, and the Cu film 18 are patterned to form a Cu wiring 18a. After that, as shown in FIG. 1 (c), W is added to the base films 14a and 16a by the CVD method.
Then, a W coating film 20 is formed by selectively growing 400 Å only on the outer surface of the Cu wiring 18a. The W coating film 20 has a sample temperature of 200 to 400 ° C., a mixed gas of WF 6 and H 2 is supplied to the film forming chamber, and the pressure of the mixed gas is 1 Torr.
It is formed as follows. According to this film forming method, the interface reaction becomes rate-determining, and W can be selectively grown only on the outer surfaces of the base films 14a and 16a and the Cu wiring 18a. here,
In order to make this wiring structure multi-layered, an insulating film such as a SiO 2 film may be formed on the W coating film 20, and the wiring structure described above may be formed on this insulating film by the same method. .

【0010】次に、本発明の製造方法で製造した配線構
造体の実施例を、比較例と共に説明する。表1は、各種
バリア材料で形成された1000Åの厚さを持つバリア
層のCuに対するバリア性の相違を比較した試験結果を
示す。ここで、例えばW−C/Wは、W膜にCをイオン
注入してWの炭化物膜(W−C)を形成したバリア膜を
表す。また、1)及び2)に示される比較例は、それぞ
れ化合物材料のスパッタリング、及び反応性スパッタリ
ングで形成した。
Next, examples of the wiring structure manufactured by the manufacturing method of the present invention will be described together with comparative examples. Table 1 shows the test results comparing the difference in the barrier properties against Cu of the barrier layers formed of various barrier materials and having a thickness of 1000Å. Here, for example, W-C / W represents a barrier film formed by ion-implanting C into the W film to form a W carbide film (W-C). Further, the comparative examples shown in 1) and 2) were formed by sputtering a compound material and reactive sputtering, respectively.

【0011】各試料は、Si基板上に形成された500
0ÅのCu膜の上に、表1に示されるバリア材料からな
るバリア層を形成し、これをH2 ガス雰囲気中で610
℃×4hの熱処理を施して作製した。その後、Si基板
表面に拡散したCu濃度、及び抵抗値を測定した。Si
基板表面のCu濃度は、SIMS(Secondary
−Ion Mass Spectroscopy)によ
って測定した。
Each sample is a 500 formed on a Si substrate.
A barrier layer made of the barrier material shown in Table 1 is formed on the Cu film of 0Å, and the barrier layer is formed in a H 2 gas atmosphere at 610
It was manufactured by applying a heat treatment of ℃ × 4h. Then, the Cu concentration diffused on the Si substrate surface and the resistance value were measured. Si
The Cu concentration on the substrate surface is SIMS (Secondary
-Ion Mass Spectroscopy).

【0012】[0012]

【表1】 表1から明らかなように、本発明によれば、実行的な抵
抗を上昇させることなく従来技術で作製した化合物膜に
比較してCu汚染を抑制できることが分かる。
[Table 1] As is clear from Table 1, according to the present invention, Cu contamination can be suppressed as compared with the compound film produced by the conventional technique without increasing the effective resistance.

【0013】[0013]

【発明の効果】以上説明したように、本発明の半導体集
積回路の配線構造体の製造方法によれば、イオン注入で
形成された金属の化合物膜を配線の下地膜にしたため、
Cuの拡散を損なうことなく配線全体の抵抗を低減する
ことが可能になる。したがって、本発明により、比抵抗
がAl合金より小さく耐エレクトロマイグレーションに
優れた、工業的意義が非常に大きいCu配線を実現でき
る。
As described above, according to the method of manufacturing a wiring structure for a semiconductor integrated circuit of the present invention, the metal compound film formed by ion implantation is used as the underlying film of the wiring.
It is possible to reduce the resistance of the entire wiring without impairing the diffusion of Cu. Therefore, according to the present invention, it is possible to realize a Cu wiring which has a smaller specific resistance than an Al alloy and is excellent in electromigration resistance and has a great industrial significance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の配線構造体の製造方法の一例を示す断
面図である。
FIG. 1 is a cross-sectional view showing an example of a method for manufacturing a wiring structure of the present invention.

【符号の説明】[Explanation of symbols]

10 Si基板 12 絶縁膜 14 W膜 14a,16a 下地膜 16 窒化タングステン膜 18 Cu膜 18a Cu配線 20 W被覆膜 10 Si substrate 12 Insulating film 14 W film 14a, 16a Underlayer film 16 Tungsten nitride film 18 Cu film 18a Cu wiring 20 W coating film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路の配線構造体の製造方法
において、 絶縁膜の上に金属バリア膜を形成し、 該金属バリア膜の表面に、B、N、及びCから選ばれた
1種をイオン注入し、 イオン注入された前記金属バリア膜の上に配線を形成す
ることを特徴とする半導体集積回路の配線構造体の製造
方法。
1. A method for manufacturing a wiring structure of a semiconductor integrated circuit, comprising forming a metal barrier film on an insulating film, and forming one kind of B, N and C on the surface of the metal barrier film. A method of manufacturing a wiring structure of a semiconductor integrated circuit, which comprises ion-implanting and forming wiring on the ion-implanted metal barrier film.
JP10713993A 1993-05-10 1993-05-10 Method for manufacturing wiring structure of semiconductor integrated circuit Withdrawn JPH06318595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10713993A JPH06318595A (en) 1993-05-10 1993-05-10 Method for manufacturing wiring structure of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10713993A JPH06318595A (en) 1993-05-10 1993-05-10 Method for manufacturing wiring structure of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH06318595A true JPH06318595A (en) 1994-11-15

Family

ID=14451506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10713993A Withdrawn JPH06318595A (en) 1993-05-10 1993-05-10 Method for manufacturing wiring structure of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH06318595A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09102544A (en) * 1995-05-09 1997-04-15 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US6268291B1 (en) 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09102544A (en) * 1995-05-09 1997-04-15 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
US6268291B1 (en) 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping

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