JPH06314812A - Manufacture of photosensitive element with built-in circuit - Google Patents
Manufacture of photosensitive element with built-in circuitInfo
- Publication number
- JPH06314812A JPH06314812A JP5103879A JP10387993A JPH06314812A JP H06314812 A JPH06314812 A JP H06314812A JP 5103879 A JP5103879 A JP 5103879A JP 10387993 A JP10387993 A JP 10387993A JP H06314812 A JPH06314812 A JP H06314812A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- light receiving
- receiving element
- signal processing
- antireflection film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 238000005530 etching Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims description 88
- 230000001681 protective effect Effects 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims 1
- 230000003449 preventive effect Effects 0.000 abstract 5
- 239000004020 conductor Substances 0.000 abstract 3
- 238000009792 diffusion process Methods 0.000 description 16
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、回路内蔵受光素子の
作製方法に関する。半導体基板の表面に、それぞれ半導
体部分と配線部分とを持ち、反射防止膜で覆われた受光
素子と、この受光素子が光を受けて発生した信号を処理
する信号処理回路とを備えた回路内蔵受光素子の作製方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a light receiving element with a built-in circuit. Built-in circuit having a light-receiving element that has a semiconductor portion and a wiring portion on the surface of a semiconductor substrate and is covered with an antireflection film, and a signal processing circuit that processes a signal generated when the light-receiving element receives light. The present invention relates to a method for manufacturing a light receiving element.
【０００２】[0002]
【従来の技術】従来、この種の回路内蔵受光素子は次の
ようにして作製されている。まず、図５(a)に示すよう
に、半導体基板１の表面のフォトダイオード領域、信号
処理回路領域に、一般的な作製手順によって、それぞれ
フォトダイオードの半導体部分、信号処理回路の半導体
部分を形成する。上記フォトダイオードの半導体部分は
Ｐ型半導体基板１、Ｎ型エピタキシャル層２、Ｎ型埋込
拡散層３およびＮ型拡散層６からなる一方、上記信号処
理回路の半導体部分はＰ型半導体基板１、Ｎ型埋込拡散
層３、Ｎ型拡散層６、Ｎ型エピタキシャル層２、ベース
拡散層７，７′およびエミッタ拡散層８からなってい
る。なお、上記フォトダイオード領域と信号処理回路領
域とは、Ｐ型埋込分離拡散層４とＰ型分離拡散層５とで
仕切られ、両領域の表面は熱酸化膜９で覆われた状態と
なっている。次に、同図(b)に示すように、上記熱酸化
膜９のうちフォトダイオードの受光面上に存する部分を
除去（開口９ａを形成）し、この上に、ＣＶＤ法によっ
てシリコン窒化膜，シリコン酸化膜などからなる反射防
止膜１０を設ける。次に、図６(c)に示すように、上記
フォトダイオード領域と信号処理回路領域内の所定の箇
所に、上記反射防止膜１０の表面から上記半導体部分に
至るコンタクト用開口を形成し、この半導体基板１上に
例えばＡｌＳｉからなる導電層２０を設ける。この導電
層２０をパターン加工して、上記フォトダイオードおよ
び信号処理回路の配線部分１２，１３，２１，２２，１
１を形成する。次に、図６(d)に示すように、半導体基
板１上に、ＣＶＤ法によって上記反射防止膜１０と同様
の材料からなる保護膜（膜厚１μｍ程度）１４を設け
る。なお、保護膜１４は反射防止膜１０上にそのまま残
しても良いが、さらに反射率を低減させたい場合は、図
７(e)に示すように、保護膜１４のうちフォトダイオー
ドの受光面上の部分を除去（開口１４ａを形成）して、
反射防止膜９を露出させる。このように、受光面上に反
射防止膜９を露出させることにより、反射防止効果を高
めることができる。2. Description of the Related Art Conventionally, a light receiving element with a built-in circuit of this type is manufactured as follows. First, as shown in FIG. 5A, a semiconductor portion of a photodiode and a semiconductor portion of a signal processing circuit are formed in a photodiode region and a signal processing circuit region on the surface of a semiconductor substrate 1 by a general manufacturing procedure. To do. The semiconductor portion of the photodiode is composed of a P-type semiconductor substrate 1, an N-type epitaxial layer 2, an N-type buried diffusion layer 3 and an N-type diffusion layer 6, while the semiconductor portion of the signal processing circuit is a P-type semiconductor substrate 1, The N-type buried diffusion layer 3, the N-type diffusion layer 6, the N-type epitaxial layer 2, the base diffusion layers 7 and 7 ', and the emitter diffusion layer 8 are included. The photodiode region and the signal processing circuit region are partitioned by the P-type buried isolation diffusion layer 4 and the P-type isolation diffusion layer 5, and the surfaces of both regions are covered with the thermal oxide film 9. ing. Next, as shown in FIG. 3B, a portion of the thermal oxide film 9 on the light receiving surface of the photodiode is removed (opening 9a is formed), and a silicon nitride film, An antireflection film 10 made of a silicon oxide film or the like is provided. Next, as shown in FIG. 6C, a contact opening extending from the surface of the antireflection film 10 to the semiconductor portion is formed at a predetermined position in the photodiode region and the signal processing circuit region. A conductive layer 20 made of, for example, AlSi is provided on the semiconductor substrate 1. The conductive layer 20 is patterned to form the wiring portions 12, 13, 21, 22, 1 of the photodiode and the signal processing circuit.
1 is formed. Next, as shown in FIG. 6D, a protective film (film thickness of about 1 μm) 14 made of the same material as the antireflection film 10 is provided on the semiconductor substrate 1 by the CVD method. Although the protective film 14 may be left on the antireflection film 10 as it is, if it is desired to further reduce the reflectance, as shown in FIG. Is removed (the opening 14a is formed),
The antireflection film 9 is exposed. By thus exposing the antireflection film 9 on the light receiving surface, the antireflection effect can be enhanced.
【０００３】[0003]
【発明が解決しようとする課題】ところで、回路内蔵受
光素子を高機能化、高性能化および高集積化するため
に、配線部分のピッチを縮小することが要請されてい
る。この結果、最近、上記導電層２０をパターン加工す
る際、ウエットエッチングではなく、ＢＣｌ3などのＣ
ｌ系プラズマまたはＣＦ4などのＦ系のプラズマを用い
たドライエッチングが行われている。ウエットエッチン
グは、等方性エッチングであり、サイドエッチによる線
幅シフトが大きいため、微細加工に適しないからであ
る。By the way, in order to make the light receiving element with a built-in circuit highly functional, high performance and highly integrated, it is required to reduce the pitch of the wiring portion. As a result, recently, when patterning the conductive layer 20, C such as BCl 3 is used instead of wet etching.
Dry etching using l-based plasma or F-based plasma such as CF 4 is performed. This is because the wet etching is isotropic etching and has a large line width shift due to side etching, and is not suitable for fine processing.
【０００４】しかしながら、上記Ｃｌ系プラズマ、Ｆ系
プラズマを用いて導電層２０をエッチングする場合、エ
ッチングの終了時に下地の反射防止膜（シリコン窒化膜
などからなる）１０がエッチングされる。このため、反
射防止膜１０の膜厚が設計値から外れて、反射率が高く
なってしまうという問題がある。However, when the conductive layer 20 is etched using the Cl-based plasma or the F-based plasma, the underlying antireflection film (made of a silicon nitride film) 10 is etched at the end of the etching. Therefore, there is a problem that the film thickness of the antireflection film 10 deviates from the designed value and the reflectance increases.
【０００５】同様に、保護膜１４をエッチングすると
き、エッチングの終了時に下地の反射防止膜１０がエッ
チングされる。このため、反射防止膜１０の膜厚が設計
値から外れて、反射率が高くなるという問題がある。Similarly, when the protective film 14 is etched, the underlying antireflection film 10 is etched at the end of the etching. Therefore, there is a problem that the film thickness of the antireflection film 10 deviates from the designed value and the reflectance increases.
【０００６】なお、上記単層配線構造の回路内蔵受光素
子の場合に限られず、多層配線構造の回路内蔵受光素子
の場合も同様に、反射防止膜の膜厚が設計値から外れ
て、反射率が高くなるという問題が生ずる。Not only in the case of the light receiving element with a built-in circuit having the single-layer wiring structure but also in the light receiving element with a built-in circuit of the multi-layer wiring structure, similarly, the film thickness of the antireflection film deviates from the design value and the reflectance is increased. Raises the problem.
【０００７】そこで、この発明の目的は、反射防止膜の
膜厚制御を高精度に行うことができ、したがって反射防
止膜の反射率を低下させることができる回路内蔵受光素
子の作製方法を提供することにある。Therefore, an object of the present invention is to provide a method of manufacturing a photodetector with a built-in circuit, which can control the film thickness of the antireflection film with high accuracy and therefore can reduce the reflectance of the antireflection film. Especially.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、この発明の回路内蔵受光素子の作製方法は、半導体
基板の表面に、それぞれ半導体部分と配線部分とを持
ち、反射防止膜で覆われた受光素子と、この受光素子が
光を受けて発生した信号を処理する信号処理回路とを備
えた回路内蔵受光素子の作製方法であって、上記半導体
基板の表面に、上記受光素子の半導体部分と、信号処理
回路の半導体部分をそれぞれ形成する工程と、上記半導
体基板上に、所定の屈折率を有する反射防止膜を設ける
工程と、上記反射防止膜の表面側から上記受光素子の半
導体部分、上記信号処理回路の半導体部分に至るコンタ
クト用開口を形成する工程と、上記半導体基板上に導電
層設け、この導電層をパターン加工して、上記受光素子
および信号処理回路の配線部分を形成するとともに、上
記受光素子の受光面に上記導電層を残す工程と、上記反
射防止膜に対するエッチングレートに比して上記導電層
に対するエッチングレートが大きい所定のエッチング液
を用いて、上記受光面上に残された導電層を除去する工
程を有することを特徴としている。In order to achieve the above object, a method of manufacturing a light receiving element with a built-in circuit according to the present invention has a semiconductor portion and a wiring portion on the surface of a semiconductor substrate, each of which is covered with an antireflection film. And a signal processing circuit for processing a signal generated when the light receiving element receives light. A method of manufacturing a light receiving element with a built-in circuit, comprising: And a semiconductor portion of the signal processing circuit, a step of providing an antireflection film having a predetermined refractive index on the semiconductor substrate, and a semiconductor portion of the light receiving element from the surface side of the antireflection film. A step of forming a contact opening to reach a semiconductor portion of the signal processing circuit, a conductive layer is provided on the semiconductor substrate, and the conductive layer is patterned to form the light receiving element and the signal processing circuit. Forming a wiring portion and leaving the conductive layer on the light-receiving surface of the light-receiving element; and using a predetermined etching solution having a higher etching rate for the conductive layer than the etching rate for the antireflection film, The method is characterized by including a step of removing the conductive layer left on the light receiving surface.
【０００９】また、上記受光面上に残された導電層をエ
ッチングする前に、上記半導体基板上に保護膜を設け、
この保護膜と上記導電層の受光面上の部分とを続けてエ
ッチングするのが望ましい。Further, before etching the conductive layer left on the light receiving surface, a protective film is provided on the semiconductor substrate,
It is desirable to continuously etch this protective film and the portion of the conductive layer on the light-receiving surface.
【００１０】また、この発明の回路内蔵受光素子の作製
方法は、半導体基板の表面に、それぞれ半導体部分と配
線部分とを持ち、反射防止膜で覆われた受光素子と、こ
の受光素子が光を受けて発生した信号を処理する信号処
理回路とを備えた回路内蔵受光素子の作製方法であっ
て、上記半導体基板の表面に、上記受光素子の半導体部
分と、信号処理回路の半導体部分をそれぞれ形成する工
程と、上記半導体基板上に、所定の屈折率を有する反射
防止膜を設ける工程と、上記反射防止膜の表面側から上
記受光素子の半導体部分、上記信号処理回路の半導体部
分に至るコンタクト用開口を形成する工程と、上記半導
体基板上に第１の導電層設け、この第１の導電層をパタ
ーン加工して、上記受光素子および信号処理回路の配線
部分を形成するとともに、上記受光素子の受光面に上記
第１の導電層を残す工程と、上記半導体基板上に層間絶
縁膜を設け、この層間絶縁膜のうち上記受光素子の受光
面上に存する部分を除去する工程と、上記半導体基板上
に第２の導電層と保護膜とを順に設け、この保護膜のう
ち上記受光素子の受光面上に存する部分を除去する工程
と、上記反射防止膜に対するエッチングレートに比して
上記導電層に対するエッチングレートが大きい所定のエ
ッチング液を用いて、上記受光面上に残された第１，第
２の導電層を一度に除去する工程を有することを特徴と
している。Further, according to the method of manufacturing a light receiving element with a built-in circuit of the present invention, a light receiving element which has a semiconductor portion and a wiring portion on the surface of a semiconductor substrate and is covered with an antireflection film, and the light receiving element emits light. A method of manufacturing a light receiving element with a built-in circuit, comprising a signal processing circuit for processing a signal received and generated, wherein a semiconductor portion of the light receiving element and a semiconductor portion of the signal processing circuit are formed on a surface of the semiconductor substrate. And a step of providing an antireflection film having a predetermined refractive index on the semiconductor substrate, and for contact from the surface side of the antireflection film to the semiconductor portion of the light receiving element and the semiconductor portion of the signal processing circuit. A step of forming an opening and providing a first conductive layer on the semiconductor substrate, and patterning the first conductive layer to form a wiring portion of the light receiving element and the signal processing circuit. The step of leaving the first conductive layer on the light receiving surface of the light receiving element, and providing an interlayer insulating film on the semiconductor substrate, and removing a portion of the interlayer insulating film existing on the light receiving surface of the light receiving element. A step of forming a second conductive layer and a protective film on the semiconductor substrate in this order, removing a portion of the protective film on the light receiving surface of the light receiving element, and an etching rate for the antireflection film. The method is characterized by including a step of removing the first and second conductive layers left on the light receiving surface at a time by using a predetermined etching solution having a higher etching rate for the conductive layer.
【００１１】[0011]
【作用】この発明によれば、受光素子の受光面上におい
て、反射防止膜上に残された導電層が、上記反射防止膜
に対するエッチングレートに比して上記導電層に対する
エッチングレートが大きい所定のエッチング液を用いて
除去される。したがって、導電層のエッチング終了時
に、下地の反射防止膜のエッチング量が従来に比して低
減される。したがって、反射防止膜の膜厚が精度良く制
御されて、設計値に略一致する状態に仕上がる。この結
果、従来に比して、反射防止膜の反射率を低く抑えるこ
とが可能となる。なお、上記エッチング液でエッチング
するのは、配線部分ではない。配線部分は、従来通りド
ライエッチングを採用することによって、加工精度を維
持することができる。According to the present invention, the conductive layer left on the antireflection film on the light receiving surface of the light receiving element has a predetermined etching rate with respect to the conductive layer higher than the etching rate with respect to the antireflection film. It is removed using an etching solution. Therefore, at the end of etching the conductive layer, the etching amount of the underlying antireflection film is reduced as compared with the conventional case. Therefore, the film thickness of the antireflection film is controlled with high accuracy, and the state where the film thickness substantially matches the design value is completed. As a result, it becomes possible to suppress the reflectance of the antireflection film to a lower value than in the conventional case. Note that it is not the wiring portion that is etched by the above-mentioned etching solution. By adopting dry etching for the wiring portion as usual, the processing accuracy can be maintained.
【００１２】また、上記受光面上に残された導電層をエ
ッチングする前に、上記半導体基板上に保護膜を設け、
この保護膜と上記導電層の受光面上の部分とを続けてエ
ッチングする場合、導電層が介在しているので、上記保
護膜のエッチングによって反射防止膜の膜厚が影響を受
けることがない。Before etching the conductive layer left on the light receiving surface, a protective film is provided on the semiconductor substrate,
When this protective film and the portion of the conductive layer on the light-receiving surface are successively etched, the conductive layer is interposed so that the thickness of the antireflection film is not affected by the etching of the protective film.
【００１３】また、後述するように、この発明は多層配
線構造の回路内蔵受光素子にも、容易に適用される。Further, as will be described later, the present invention can be easily applied to a light receiving element with a built-in circuit having a multilayer wiring structure.
【００１４】[0014]
【実施例】以下、この発明の回路内蔵受光素子の作製方
法を実施例により詳細に説明する。EXAMPLES A method of manufacturing a photodetector with a built-in circuit according to the present invention will be described in detail below with reference to examples.
【００１５】図１に示すように、図７(e)に示したもの
と同一の単層配線構造の回路内蔵受光素子を作製するも
のとする。なお、簡単のため、図中、同一の構成部分は
同一の番号で示している。As shown in FIG. 1, a circuit built-in light receiving element having the same single-layer wiring structure as that shown in FIG. 7E is manufactured. Note that, for simplification, in the drawings, the same components are denoted by the same numbers.
【００１６】まず、図１(a)に示すように、半導体基
板１の表面のフォトダイオード領域、信号処理回路領域
に、従来例と同様に一般的な作製手順によって、それぞ
れフォトダイオードの半導体部分、信号処理回路の半導
体部分を形成する。上記フォトダイオードの半導体部分
はＰ型半導体基板１、Ｎ型エピタキシャル層２、Ｎ型埋
込拡散層３およびＮ型拡散層６からなる一方、上記信号
処理回路の半導体部分はＰ型半導体基板１、Ｎ型埋込拡
散層３、Ｎ型拡散層６、Ｎ型エピタキシャル層２、ベー
ス拡散層７，７′およびエミッタ拡散層８からなってい
る。なお、上記フォトダイオード領域と信号処理回路領
域とは、Ｐ型埋込分離拡散層４とＰ型分離拡散層５とで
仕切られ、両領域の表面は絶縁膜としての熱酸化膜９で
覆われた状態となる。First, as shown in FIG. 1A, in the photodiode region and the signal processing circuit region on the surface of the semiconductor substrate 1, the semiconductor portion of the photodiode and the semiconductor region of the photodiode are respectively formed by the same general manufacturing procedure as in the conventional example. The semiconductor portion of the signal processing circuit is formed. The semiconductor portion of the photodiode is composed of a P-type semiconductor substrate 1, an N-type epitaxial layer 2, an N-type buried diffusion layer 3 and an N-type diffusion layer 6, while the semiconductor portion of the signal processing circuit is a P-type semiconductor substrate 1, The N-type buried diffusion layer 3, the N-type diffusion layer 6, the N-type epitaxial layer 2, the base diffusion layers 7 and 7 ', and the emitter diffusion layer 8 are included. The photodiode region and the signal processing circuit region are partitioned by a P-type buried isolation diffusion layer 4 and a P-type isolation diffusion layer 5, and the surfaces of both regions are covered with a thermal oxide film 9 as an insulating film. It will be in a state of being.
【００１７】次に、上記熱酸化膜９のうちフォトダイ
オードの受光面上に存する部分を除去（開口９ａを形
成）し、この上に、ＣＶＤ法によってシリコン窒化膜，
シリコン酸化膜などからなる反射防止膜１０を設ける。Next, a portion of the thermal oxide film 9 existing on the light receiving surface of the photodiode is removed (opening 9a is formed), and a silicon nitride film,
An antireflection film 10 made of a silicon oxide film or the like is provided.
【００１８】次に、上記フォトダイオード領域と信号
処理回路領域内の所定の箇所に、上記反射防止膜１０の
表面から上記半導体部分に至るコンタクト用開口を形成
する。Next, a contact opening extending from the surface of the antireflection film 10 to the semiconductor portion is formed at a predetermined position in the photodiode region and the signal processing circuit region.
【００１９】次に、この半導体基板１上に例えばＡｌ
Ｓｉからなる導電層２０を設け、この導電層２０をパタ
ーン加工して、上記フォトダイオードおよび信号処理回
路の配線部分１２，１３，２１，２２，１１を形成す
る。このとき、上記フォトダイオードの受光面上に、導
電層２０の一部１５を残す。Next, on the semiconductor substrate 1, for example, Al
The conductive layer 20 made of Si is provided, and the conductive layer 20 is patterned to form the wiring portions 12, 13, 21, 21, 22 of the photodiode and the signal processing circuit. At this time, a part 15 of the conductive layer 20 is left on the light receiving surface of the photodiode.
【００２０】次に、図１(b)に示すように、半導体基
板１上に、ＣＶＤ法によって上記反射防止膜１０と同様
の材料からなる保護膜（膜厚１μｍ程度）１４を設け
る。Next, as shown in FIG. 1B, a protective film (about 1 μm thick) 14 made of the same material as the antireflection film 10 is provided on the semiconductor substrate 1 by the CVD method.
【００２１】この後、保護膜１４のうちフォトダイオ
ードの受光面上の部分を除去（開口１４ａを形成）し
て、導電層１５を露出させる。続いて、上記反射防止膜
１０に対するエッチングレートに比して導電層１５に対
するエッチングレートが大きい所定のエッチング液を用
いて、導電層１５を除去する（作製完了）。なお、この
例のように導電層１５がＡｌ系材料からなるときは、リ
ン酸系のエッチング液を用いれば良い。After that, a portion of the protective film 14 on the light receiving surface of the photodiode is removed (opening 14a is formed) to expose the conductive layer 15. Then, the conductive layer 15 is removed using a predetermined etching solution having a higher etching rate for the conductive layer 15 than the etching rate for the antireflection film 10 (manufacturing is completed). When the conductive layer 15 is made of an Al-based material as in this example, a phosphoric acid-based etching solution may be used.
【００２２】このようにした場合、導電層１５のエッチ
ング終了時に、下地の反射防止膜（シリコン窒化膜など
からなる）１０のエッチング量を従来に比して低減でき
る。また、保護膜１４のエッチングによって反射防止膜
１０の膜厚が影響を受けることもない。したがって、反
射防止膜１０の膜厚を精度良く制御でき、設計値に略一
致させることができる。この結果、従来に比して、反射
防止膜１０の反射率を低く抑えることができる。In this case, when the etching of the conductive layer 15 is completed, the etching amount of the underlying antireflection film (made of a silicon nitride film or the like) 10 can be reduced as compared with the conventional case. Further, the thickness of the antireflection film 10 is not affected by the etching of the protective film 14. Therefore, the film thickness of the antireflection film 10 can be accurately controlled and can be made to substantially match the design value. As a result, the reflectance of the antireflection film 10 can be suppressed lower than in the conventional case.
【００２３】なお、反射率を低減する必要性があまりな
いときは、導電層１５をリン酸系のエッチング液で除去
した後に、半導体基板１上に保護膜１４を設け、上記フ
ォトダイオードの受光面上にそのまま保護膜１４を残し
ても良い。When it is not necessary to reduce the reflectance, the conductive layer 15 is removed with a phosphoric acid-based etching solution, and then the protective film 14 is provided on the semiconductor substrate 1 to form the light receiving surface of the photodiode. The protective film 14 may be left on the surface as it is.
【００２４】次に、この発明を適用して多層配線構造の
回路内蔵受光素子を作製する例について述べる。Next, an example of manufacturing a photodetector with a built-in circuit having a multilayer wiring structure by applying the present invention will be described.
【００２５】図２(a)に示すように、先に述べた例の
工程〜と全く同様に工程を進めて、半導体基板１上
に、フォトダイオードおよび信号処理回路の配線部分１
２，１３，２１，２２，１１を形成するとともに、上記
フォトダイオードの受光面上に、導電層２０の一部１５
を残した状態にする。As shown in FIG. 2 (a), steps exactly the same as the steps 1 to 3 described above are carried out, and the photodiode 1 and the wiring portion 1 of the signal processing circuit are formed on the semiconductor substrate 1.
2, 13, 21, 22, 11 are formed, and a part 15 of the conductive layer 20 is formed on the light receiving surface of the photodiode.
To leave.
【００２６】次に、同図(b)に示すように、ＣＶＤ法
によって層間絶縁膜１６を形成し、この層間絶縁膜１６
のうち上記フォトダイオードの受光面上の部分を除去す
る（開口１６ａを形成する）。このとき、導電層１５を
残しているので、層間絶縁膜１６のエッチングによって
反射防止膜１０の膜厚が影響を受けることはない。Next, as shown in FIG. 3B, an interlayer insulating film 16 is formed by the CVD method, and the interlayer insulating film 16 is formed.
Of the above, the portion on the light receiving surface of the photodiode is removed (the opening 16a is formed). At this time, since the conductive layer 15 is left, the film thickness of the antireflection film 10 is not affected by the etching of the interlayer insulating film 16.
【００２７】次に、図３(c)に示すように、半導体基
板１上に例えばＡｌからなる導電層１７を設ける。Next, as shown in FIG. 3C, a conductive layer 17 made of, for example, Al is provided on the semiconductor substrate 1.
【００２８】次に、図４(e)に示すように、半導体基
板１上に、ＣＶＤ法によって上記反射防止膜１０と同様
の材料からなる保護膜（膜厚１μｍ程度）１８を設け
る。Next, as shown in FIG. 4E, a protective film (film thickness of about 1 μm) 18 made of the same material as the antireflection film 10 is provided on the semiconductor substrate 1 by the CVD method.
【００２９】この後、保護膜１８のうちフォトダイオ
ードの受光面上の部分を除去（開口１８ａを形成）し
て、導電層１７を露出させる。続いて、同図(f)に示す
ように、上記反射防止膜１０に対するエッチングレート
に比して導電層１７，１５に対するエッチングレートが
大きい所定のエッチング液を用いて、導電層１７，１５
を一度に除去する（１５ａはエッチング残りを示してい
る。）。ここでは導電層１７，１５を同時に除去した
が、図２(b)の段階で導電層１５をまず除去しておいて
もよい。なお、この例のように導電層１７，１５がＡｌ
系材料からなるときは、リン酸系のエッチング液を用い
れば良い。After that, the portion of the protective film 18 on the light receiving surface of the photodiode is removed (opening 18a is formed) to expose the conductive layer 17. Then, as shown in FIG. 3F, the conductive layers 17, 15 are formed by using a predetermined etching solution having a larger etching rate for the conductive layers 17, 15 than the etching rate for the antireflection film 10.
Are removed at once (15a indicates an etching residue). Here, the conductive layers 17 and 15 are removed at the same time, but the conductive layer 15 may be removed first at the stage of FIG. In addition, as in this example, the conductive layers 17 and 15 are made of Al.
When it is made of a system material, a phosphoric acid-based etching solution may be used.
【００３０】このようにした場合、導電層１５のエッチ
ング終了時に、下地の反射防止膜（シリコン窒化膜など
からなる）１０のエッチング量を従来に比して低減でき
る。また、保護膜１８のエッチングによって反射防止膜
１０の膜厚が影響を受けることもない。したがって、反
射防止膜１０の膜厚を精度良く制御でき、設計値に略一
致させることができる。この結果、従来に比して、反射
防止膜１０の反射率を低く抑えることができる。保護膜
１８が反射防止膜１０に比べてエッチングレートが大き
いエッチングが可能な場合には、保護膜１８のうちフォ
トダイオードの受光面上の部分の除去（開口１８ａを形
成）は導電層１７，１５の除去後に行ってもよい。In this case, when the etching of the conductive layer 15 is completed, the etching amount of the underlying antireflection film (made of a silicon nitride film) 10 can be reduced as compared with the conventional case. Further, the film thickness of the antireflection film 10 is not affected by the etching of the protective film 18. Therefore, the film thickness of the antireflection film 10 can be accurately controlled and can be made to substantially match the design value. As a result, the reflectance of the antireflection film 10 can be suppressed lower than in the conventional case. When the protective film 18 can be etched with a higher etching rate than the antireflection film 10, the portions of the protective film 18 on the light-receiving surface of the photodiode (the openings 18a are formed) are removed by the conductive layers 17 and 15. May be carried out after the removal of.
【００３１】なお、反射率を低減する必要性があまりな
いときは、図３(d)に示すように、上記導電層１７を設
けた後（工程）、導電層１７，１５のうちフォトダイ
オードの受光面上の部分をリン酸系のエッチング液で除
去し、続いて、半導体基板１上に保護膜１４を設け、そ
のまま保護膜１４を残しても良い。When it is not necessary to reduce the reflectance, as shown in FIG. 3 (d), after the conductive layer 17 is provided (step), one of the conductive layers 17 and 15 of the photodiode is removed. It is also possible to remove the portion on the light-receiving surface with a phosphoric acid-based etching solution, subsequently provide the protective film 14 on the semiconductor substrate 1, and leave the protective film 14 as it is.
【００３２】[0032]
【発明の効果】以上より明らかなように、この発明の回
路内蔵受光素子の作製方法は、配線部分形成時に、受光
素子の受光面上に導電層を残し、この導電層を、反射防
止膜に対するエッチングレートに比して上記導電層に対
するエッチングレートが大きい所定のエッチング液を用
いて除去しているので、導電層のエッチング終了時に、
下地の反射防止膜のエッチング量を従来に比して低減す
ることができる。したがって、反射防止膜の膜厚を精度
良く制御して、設計値に略一致させることができる。こ
の結果、従来に比して、反射防止膜の反射率を低く抑え
ることができる。As is apparent from the above, according to the method of manufacturing a light receiving element with a built-in circuit of the present invention, a conductive layer is left on the light receiving surface of the light receiving element at the time of forming the wiring portion, and the conductive layer is used as an antireflection film. Since the etching is performed using a predetermined etching solution having a larger etching rate for the conductive layer than the etching rate, at the end of etching the conductive layer,
The etching amount of the underlying antireflection film can be reduced as compared with the conventional case. Therefore, it is possible to control the film thickness of the antireflection film with high accuracy and substantially match the design value. As a result, the reflectance of the antireflection film can be suppressed lower than in the conventional case.
【００３３】また、上記受光面上に残された導電層をエ
ッチングする前に、上記半導体基板上に保護膜を設け、
この保護膜と上記導電層の受光面上の部分とを続けてエ
ッチングする場合、導電層が介在しているので、上記保
護膜のエッチングによって反射防止膜の膜厚が影響を受
けるのを防止できる。Before etching the conductive layer left on the light receiving surface, a protective film is provided on the semiconductor substrate,
When the protective film and the portion of the conductive layer on the light-receiving surface are successively etched, the conductive layer is interposed so that the thickness of the antireflection film can be prevented from being affected by the etching of the protective film. .
【００３４】また、この発明は多層配線構造の回路内蔵
受光素子に容易に適用することができる。Further, the present invention can be easily applied to a light receiving element with a built-in circuit having a multilayer wiring structure.
【図１】 この発明の一実施例の回路内蔵受光素子の作
製方法を説明する工程図である。FIG. 1 is a process chart for explaining a method of manufacturing a light receiving element with a built-in circuit according to an embodiment of the present invention.
【図２】 この発明の一実施例の回路内蔵受光素子の作
製方法を説明する工程図である。FIG. 2 is a process drawing explaining a method of manufacturing a light receiving element with a built-in circuit according to an embodiment of the present invention.
【図３】 上記回路内蔵受光素子の作製方法を説明する
工程図である。FIG. 3 is a process diagram illustrating a method of manufacturing the above-described light receiving element with a built-in circuit.
【図４】 上記回路内蔵受光素子の作製方法を説明する
工程図である。FIG. 4 is a process diagram illustrating a method of manufacturing the above-described light receiving element with a built-in circuit.
【図５】 従来の回路内蔵受光素子の作製方法を説明す
る工程図である。5A to 5C are process diagrams illustrating a conventional method of manufacturing a light receiving element with a built-in circuit.
【図６】 上記従来の回路内蔵受光素子の作製方法を説
明する工程図である。FIG. 6 is a process diagram illustrating a method of manufacturing the conventional photodetector with a built-in circuit.
【図７】 上記従来の回路内蔵受光素子の作製方法を説
明する工程図である。FIG. 7 is a process chart for explaining a method for manufacturing the conventional photodetector with a built-in circuit.
１ Ｐ型半導体基板 ２ Ｎ型エピタキシャル層 １０ 反射防止膜 １１，１２，１３，２１，２２ 配線部分 １４，１７ 保護膜 １５，１７，２０ 導電層 １６ 層間絶縁膜 1 P-type semiconductor substrate 2 N-type epitaxial layer 10 Antireflection film 11, 12, 13, 21, 22 Wiring part 14, 17 Protective film 15, 17, 20 Conductive layer 16 Interlayer insulating film
Claims (3)
分と配線部分とを持ち、反射防止膜で覆われた受光素子
と、この受光素子が光を受けて発生した信号を処理する
信号処理回路とを備えた回路内蔵受光素子の作製方法で
あって、 上記半導体基板の表面に、上記受光素子の半導体部分
と、信号処理回路の半導体部分をそれぞれ形成する工程
と、 上記半導体基板上に、所定の屈折率を有する反射防止膜
を設ける工程と、 上記反射防止膜の表面側から上記受光素子の半導体部
分、上記信号処理回路の半導体部分に至るコンタクト用
開口を形成する工程と、 上記半導体基板上に導電層設け、この導電層をパターン
加工して、上記受光素子および信号処理回路の配線部分
を形成するとともに、上記受光素子の受光面に上記導電
層を残す工程と、 上記反射防止膜に対するエッチングレートに比して上記
導電層に対するエッチングレートが大きい所定のエッチ
ング液を用いて、上記受光面上に残された導電層を除去
する工程を有することを特徴とする回路内蔵受光素子の
作製方法。1. A light receiving element, which has a semiconductor portion and a wiring portion on a surface of a semiconductor substrate and is covered with an antireflection film, and a signal processing circuit for processing a signal generated when the light receiving element receives light. And a step of forming a semiconductor portion of the light receiving element and a semiconductor portion of a signal processing circuit on the surface of the semiconductor substrate, the method comprising: A step of providing an antireflection film having a refractive index; a step of forming a contact opening from the surface side of the antireflection film to the semiconductor portion of the light receiving element and the semiconductor portion of the signal processing circuit; Providing a conductive layer, patterning the conductive layer to form wiring portions of the light receiving element and the signal processing circuit, and leaving the conductive layer on the light receiving surface of the light receiving element; A photodetector with a built-in circuit, comprising a step of removing the conductive layer left on the light-receiving surface by using a predetermined etching solution having a higher etching rate for the conductive layer than that for the antireflection film. Manufacturing method of device.
ングする前に、上記半導体基板上に保護膜を設け、この
保護膜と上記導電層の受光面上の部分とを続けてエッチ
ングすることを特徴とする請求項１に記載の回路内蔵受
光素子の作製方法。2. A protective film is provided on the semiconductor substrate before etching the conductive layer left on the light-receiving surface, and the protective film and the portion of the conductive layer on the light-receiving surface are continuously etched. The method for producing a light-receiving element with a built-in circuit according to claim 1, wherein.
分と配線部分とを持ち、反射防止膜で覆われた受光素子
と、この受光素子が光を受けて発生した信号を処理する
信号処理回路とを備えた回路内蔵受光素子の作製方法で
あって、 上記半導体基板の表面に、上記受光素子の半導体部分
と、信号処理回路の半導体部分をそれぞれ形成する工程
と、 上記半導体基板上に、所定の屈折率を有する反射防止膜
を設ける工程と、 上記反射防止膜の表面側から上記受光素子の半導体部
分、上記信号処理回路の半導体部分に至るコンタクト用
開口を形成する工程と、 上記半導体基板上に第１の導電層設け、この第１の導電
層をパターン加工して、上記受光素子および信号処理回
路の配線部分を形成するとともに、上記受光素子の受光
面に上記第１の導電層を残す工程と、 上記半導体基板上に層間絶縁膜を設ける工程と、 上記半導体基板上に第２の導電層と保護膜とを順に設け
る工程と、 上記反射防止膜に対するエッチングレートに比して上記
導電層に対するエッチングレートが大きい所定のエッチ
ング液を用いて、上記受光面上に残された第１，第２の
導電層を除去する工程を有することを特徴とする回路内
蔵受光素子の作製方法。3. A light receiving element having a semiconductor portion and a wiring portion on a surface of a semiconductor substrate and covered with an antireflection film, and a signal processing circuit for processing a signal generated when the light receiving element receives light. And a step of forming a semiconductor portion of the light receiving element and a semiconductor portion of a signal processing circuit on the surface of the semiconductor substrate, the method comprising: A step of providing an antireflection film having a refractive index; a step of forming a contact opening from the surface side of the antireflection film to the semiconductor portion of the light receiving element and the semiconductor portion of the signal processing circuit; A first conductive layer is provided, and the first conductive layer is patterned to form wiring portions of the light receiving element and the signal processing circuit, and the first conductive layer is formed on the light receiving surface of the light receiving element. Remaining, a step of providing an interlayer insulating film on the semiconductor substrate, a step of sequentially providing a second conductive layer and a protective film on the semiconductor substrate, and the above-mentioned etching rate relative to the antireflection film. A method of manufacturing a light-receiving element with a built-in circuit, comprising the step of removing the first and second conductive layers left on the light-receiving surface using a predetermined etching liquid having a high etching rate for the conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5103879A JP2892569B2 (en) | 1993-04-30 | 1993-04-30 | Fabrication method of photodetector with built-in circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5103879A JP2892569B2 (en) | 1993-04-30 | 1993-04-30 | Fabrication method of photodetector with built-in circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06314812A true JPH06314812A (en) | 1994-11-08 |
| JP2892569B2 JP2892569B2 (en) | 1999-05-17 |
Family
ID=14365726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5103879A Expired - Fee Related JP2892569B2 (en) | 1993-04-30 | 1993-04-30 | Fabrication method of photodetector with built-in circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2892569B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019057688A (en) * | 2017-09-22 | 2019-04-11 | ラピスセミコンダクタ株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
1993
- 1993-04-30 JP JP5103879A patent/JP2892569B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019057688A (en) * | 2017-09-22 | 2019-04-11 | ラピスセミコンダクタ株式会社 | Semiconductor device and method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2892569B2 (en) | 1999-05-17 |
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