JPH06314661A - Forming method for semiconductor thin film - Google Patents

Abstract

PURPOSE:To reduce resistivity of a polycrystalline silicon thin film to be used as various electrodes or a wiring material for constituting a semiconductor integrated circuit. CONSTITUTION:When a thin amorphous silicon thin film 13 having a thickness of about 50nm or less is grown on a silicon substrate 11 through a silicon oxide film 12, a ratio (D/S) of the number of silicon atoms S to that of impurity atoms D in reaction gas is so set to 0.05-0.2 that impurity concentration in the film becomes 5X10<20>-2.5X10<21>cm<-3> to form a film. Then, a polycrystalline silicon thin film 14 having low resistivity is formed by heat treating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor thin film, and more particularly to a method for forming a polycrystalline silicon thin film used in various semiconductor devices.

[0002]

2. Description of the Related Art A polycrystalline silicon thin film plays an important role as a material for forming a semiconductor device as various electrodes, wiring materials or resistors. For example, a polycrystalline silicon thin film is applied to a capacitor electrode, a gate electrode in a memory device, or a contact burying material between a device active layer and a wiring layer. Further, in recent years, a polycrystalline silicon thin film transistor (TFT) using a polycrystalline silicon thin film itself as an active layer of a device.
Have been developed and put into practical use as a load element of SRAM (static RAM) or a liquid crystal drive element for a liquid crystal display (LCD).

Conventionally, as a method of forming these polycrystalline silicon thin films, a silane-based gas (SiH ₄ , Si ₂ H ₆ ) has been used.
Using a chemical vapor deposition (CVD) method with a film forming gas of 6
A method of directly depositing a polycrystalline silicon thin film at a film forming temperature of about 50 ° C., or an amorphous silicon thin film is first deposited at a film forming temperature of about 500 ° C., and then the sample temperature is set to 6
There is a method in which a polycrystalline silicon thin film is obtained by performing heat treatment (crystallization treatment) while maintaining it at a certain temperature of about 00 to 900 ° C.
The latter method is described in, for example, Kobayashi et al., Abstract of the Entities Conference on Solid State Devices.
And Materials (Abstracts of t
he 20th Conference on Sol
id State Devices and Mate
rials) 1989. pp. 57-60.

In particular, since the polycrystalline silicon thin film formed by the latter method has a large average crystal grain size, the resistance can be made lower than that of the polycrystalline silicon thin film formed by the former method, or It has advantages such as few crystal grain boundaries that strongly affect the transistor characteristics. For this reason, this latter method is currently receiving attention, and
It is being energetically developed as an application to a thin film for electrodes or as a method for forming various electrodes in the future.

Next, a conventional method of forming a polycrystalline silicon thin film by crystallizing this amorphous silicon will be described with reference to a specific example. First, a thermal oxide film is grown to 100 nm on a silicon single crystal substrate, and then a normal LP is formed.
Amorphous silicon thin film 150n using CVD furnace
m to form an amorphous silicon substrate. The film forming conditions are, for example, a pressure of 0.15 Torr, a temperature of 470 ° C.,
Film forming gas flow rate 100% -Si ₂ H ₆ 96 sccm, He
Base is a 4% -PH ₃ 120sccm. Next, using an electric furnace, in a nitrogen atmosphere if the temperature falls, the temperature inside the furnace is 850 ° C.
Then, the amorphous silicon thin film is crystallized by carrying out a heat treatment for 30 minutes while keeping it at the above temperature to obtain a polycrystalline silicon thin film. The ratio of the numbers of P and Si atoms in the reaction gas obtained from the flow rates of the PH ₃ gas and the Si ₂ H ₆ gas at this time (P / Si = 2.5 × 1
When an amorphous silicon film is formed at 0 ^-2 ), the P concentration existing in the film after crystallization becomes about 3 × 10 ²⁰ cm ^-3 . In the case of a polycrystalline silicon film having a thickness of about 100 nm or more, which has been conventionally used, when P having such a high concentration is present in the film, the resistivity is about 6 × 10 ⁻³ Ω · m, which is a sufficiently low resistance. It becomes a polycrystalline silicon film.

Here, the relationship between the impurity concentration in the polycrystalline silicon film and the resistivity is described by Wada et al. In Denki Kagaku, 47 (197).
9) 118, Nakayama, et al., Japanese Journal of Applied Physics (Japanese Journal of App).
Lied Physics), 23 (1984) L49
3 etc. According to these, 3 × 10 ²⁰
There is a tendency that the resistivity becomes minimum at a phosphorus (P) concentration in the film in the vicinity of ˜1 × 10 ²¹ cm ⁻³ , and the resistivity increases at a concentration higher than that.

In order to change the phosphorus concentration in the polycrystalline silicon film, P in the reaction gas at the time of forming the amorphous silicon film
FIG. 3 shows the results of examining the change in resistivity of the polycrystalline silicon film after crystallization by changing / Si. As the film forming conditions, the conditions of the specific examples shown above were used except the gas flow rate ratio.

As can be seen from FIG. 3, when the amount of P / Si is small, the resistivity of the film decreases as P / Si in the reaction gas increases. This is because the carrier concentration increases as the phosphorus concentration in the film increases. However, P / S
When i = 1 × 10 ^-2 , the decrease in the resistivity disappears, and the decrease in resistivity cannot be expected even if P / Si is further increased. Rather, excessive P deteriorates the crystallinity of the polycrystalline silicon, and it is even observed that the resistivity slightly increases. Therefore,
Conventionally, a value of about P / Si = 2 × 3 × 10 ⁻² is used as a condition for forming low resistivity polycrystalline silicon, and a polycrystalline silicon film having a phosphorus concentration of 2 × 4 × 10 ²⁰ cm ^−3. Was getting

[0009]

Polycrystalline silicon as an electrode material is required to be applied in a very fine region due to high integration of semiconductor devices. For example, by applying to a buried contact hole having a diameter of 0.2 μm or less or a complicated region narrower than 0.1 μm, which is seen in the formation of a three-dimensional type capacitor, etc. Substantial thinning of silicon is progressing.

However, the conventional condition (P / Si = 0.02)
When the film is formed in 5), as the thickness of the polycrystalline silicon film is reduced, as shown in FIG. 2, there is a phenomenon in which the resistivity increases sharply from around the film thickness of about 50 nm. In fact, when the film thickness is 100 nm, the resistivity is 6 × 10 ⁻⁶ Ω · m
In contrast, the film thickness of 25 nm was 6.5 × 10 ⁻⁵ Ω.
・ Increase by more than an order of magnitude, and the resistivity will increase as the thickness decreases. However, even in thin film growth, the concentration of impurities (phosphorus) in the film at the time of growth is about the same as in the case of the conventionally used film thickness, and there is no decrease due to thinning.
However, the impurity concentration in the polycrystalline silicon film is slightly decreased because of the outward diffusion of impurities during the crystallization heat treatment, but this is not enough to cause the increase in the resistivity.

This decrease is a major obstacle to applying a polycrystalline silicon film to various electrode materials for highly integrated semiconductor devices. An object of the present invention is to provide a method for forming a semiconductor thin film having a sufficiently low resistivity even in a thin film having a thickness of 50 nm or less.

[0012]

A method of forming a semiconductor thin film according to a first aspect of the present invention is a semiconductor thin film in which an amorphous silicon thin film having a thickness of 50 nm or less is deposited by a CVD method while introducing impurities and then polycrystallized by heat treatment. In the forming method, the ratio (D / S) of the number D of impurity atoms to the number of silicon (Si) atoms in the reaction gas is set to 0.05 to 0.2.

The method of forming a semiconductor thin film of the second invention is a method of forming a semiconductor thin film in which an amorphous silicon thin film having a thickness of 50 nm or less is deposited by a CVD method while introducing impurities and then polycrystallized by heat treatment. The impurity concentration inside is 5 × 10 ^{20 to} 2.5 × 10 ²¹ cm
^The feature is that the amount of impurities to be introduced is controlled so as to be ⁻³ .

Setting D / S to 0.05 to 0.2 is C
It is easy by controlling the flow rate of the reaction gas in the VD method. By setting D / S to be 0.05 to 0.2, the impurity concentration in the polycrystalline silicon film is 5 × 10 ^{20 to} 2.5.
It becomes about 10 ²¹ cm ^-3 . This impurity concentration varies somewhat depending on the heat treatment conditions for crystallization, but the variation is 1
It can be suppressed within 0%.

The resistivity of the polycrystalline silicon film is 1 × 10 ^-5 Ω
・ The impurity concentration should be 5 × 10 ² cm ^-3 in order to obtain m.
It is necessary to be above. However, the impurity concentration is 2.5 × 1
When it is 0 ²¹ cm ⁻³ or more, carrier mobility is lowered due to the influence of crystallinity deterioration and impurity scattering, and conversely the resistivity increases, which is not preferable.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. 1A to 1C are sectional views of a semiconductor chip for explaining a first embodiment of the present invention.
The purpose is to obtain a polycrystalline silicon thin film having a thin film thickness and a low resistivity.

First, as shown in FIG. 1A, a silicon oxide film 12 is formed on a P-type silicon substrate 11 having a plane orientation (100) and a resistivity of 1 × 10 ⁻² Ω · m by a thermal oxidation method.
It was formed to a thickness of nm.

Next, as shown in FIG. 1B, a plurality of amorphous silicon thin films 13 having a thickness of 10 to 100 nm and doped with phosphorus (P) are used by using an ordinary batch type LPCVD apparatus using a resistance heating furnace. A film was formed. The film forming conditions are: a reaction tube temperature of 470 ° C., a pressure of 0.15 Torr, a reaction gas of 100% -Si ₂ H ₆ , and a He base of 4% -PH ₃ gas, and the respective flow rates are 96 sccm, 120 to 48.
It was set to 0 sccm. P / Si in the reaction gas under these conditions
The value was 2.0 × 10 ^-2 to 1 × 10 ^-1 , and the phosphorus concentration in the film after crystallization was 2 × 10 ^{20 to} 1.3 × 10 ²¹ cm ^-3.
It was set up so that it could be obtained from the membrane.

Thereafter, as shown in FIG. 1C, the amorphous silicon thin film 13 is heated to 850 in a nitrogen atmosphere.
A polycrystalline silicon thin film 14 was formed by heat treatment at 30 ° C. for 30 minutes. In addition, as the heat treatment, 600 to 900 ° C., 30
Conditions of minutes to 2 hours can be used.

The phosphorus concentration in the film is 3 × 10 ²⁰ cm ^-3 (P /
Si = 2.5 × 10 ⁻² ) as a conventional example, and phosphorus concentration of 1.3 × 10 ²¹ cm ⁻³ (P / Si = 1.0 × 1)
0 ⁻¹ ) and 2.0 × 10 ²¹ cm ⁻³ (P / Si = 1.5
2 × 10 ⁻¹ ) are shown as examples in FIG.
In the conventional example, when the film thickness is 100 nm or more, 6 × 10 ⁻⁶
Even if the resistivity is sufficiently low as Ω · m, if the film thickness of the amorphous silicon to be formed becomes thin, it becomes approximately 5
From around 0 nm, there is a sharp decrease in the resistivity of the polycrystalline silicon after crystallization. It is considered that the cause is that the crystal grain size of polycrystalline silicon becomes smaller as the film thickness becomes thinner, the amount of impurities segregated at the grain boundaries increases, and the number of activatable impurity atoms becomes insufficient.

On the other hand, the phosphorus concentration in the film is 1.3 × 10
^{At 21} cm ^-3 , the film thickness up to about 30 nm is 2.0 x 1
At 0 ²¹ cm ^-3 , the resistivity is 1 up to a film thickness of about 20 nm.
It can be lowered to × 10 ⁻⁵ Ω · m. That is, according to the method of the first embodiment, by introducing more impurities into the film, the increase in the segregation amount due to the thinning is compensated,
Since the number of impurity atoms that can be activated can be increased,
It is possible to lower the resistivity than before.

Next, film thicknesses of 18 nm, 50 nm and 10
Regarding 0 nm polycrystalline silicon, the phosphorus concentration in the film is 2
The P / Si value at the time of film formation is set from 2.0 × 10 ^-2 to five times the value of 1 × 10 ^-1 so as to be from × 10 ²⁰ cm ^-3 to 1.3 × 10 ²¹ cm ^-3. FIG. 4 shows changes in the phosphorus concentration in the film and the resistivity when the concentration was increased.

As shown in FIG. 4, in the case of a polycrystalline silicon film having a film thickness of 100 nm or more, the resistivity is sufficiently reduced when the phosphorus concentration in the film is 2 × 10 ²⁰ cm ^-3 , and the resistivity is increased even if the concentration is further increased. Not decreasing. On the other hand, for a film having a film thickness of 50 nm, the phosphorus concentration in the film is 2 × 10 ²⁰ cm ⁻³ to 5 × 10 ^20.
By increasing to cm ^-3 , the resistivity is 1.5 × 10 ^-5 Ω
・ Reduced from m to 1 × 10 ^-5 Ω ・ m, and the resistivity is low enough to be applied as various electrode materials. Further, by making the phosphorus concentration larger than 1.0 × 10 ⁻²¹ cm ⁻³ ,
It can be seen that a polycrystalline silicon film having a resistivity comparable to that of a film having a thickness of 100 nm can be obtained.

As described above, according to the first embodiment, a polycrystalline silicon thin film having a low resistivity can be formed even in a thin film having a film thickness of 50 nm or less as compared with the conventional method.

In the first embodiment, phosphorus (P) is used.
Although only the doped film has been described, even if the dopant impurity is arsenic (As) or boron (B), the same effect (reduction in resistivity) is obtained by the present invention.
When the impurity is P, tert-butylphosphine can be used instead of PH ₃ , when the impurity is As, arsine, tert-butylarsine or arsenic trichloride can be used, and when the impurity is B, diborane can be used. Further, SiH ₄ may be used instead of Si ₂ H ₆ as the film forming gas.

FIGS. 5A to 5D are sectional views of a semiconductor chip for explaining the second embodiment of the present invention. In the second embodiment, the present invention is applied to a contact burying material for a device active layer and a wiring layer in various semiconductor devices.

First, as shown in FIG. 5A, As is ion-implanted into the surface of a P-type silicon substrate 21 having a plane orientation (100) to form an n ⁺ diffusion layer 22. Next, FIG. 5 (b)
, The silicon oxide film 23 having a thickness of 1 μm is formed on the entire surface.
Formed by photolithography process and ion etching process, and has a diameter of 0.15 μm and a depth of 0.5 μm.
Contact hole 28 is formed.

Next, as shown in FIG. 5C, the phosphorus concentration in the film is 3 × 10 ²⁰ cm ⁻³ (conventional example) and 1.3 × 10 ²¹ cm ⁻ as in the first embodiment. ³ (Example) so that the P / Si values during film formation are 2.5 × 10 ^-2 and 1 respectively.
An amorphous silicon thin film having a thickness of 100 nm is formed on the entire surface while P doping is performed at × 10 ⁻¹ , and the temperature is 850 ° C.
The amorphous silicon thin film was crystallized under the heat treatment condition of 0 minutes to form a polycrystalline silicon thin film 24. afterwards,
The polycrystalline silicon thin film on the oxide film was removed by the ion etching process.

As shown in FIG. 5D, a titanium (Ti) film 25 of 30 nm, a titanium nitride (TiN) film 26A of 100 nm, an A1-Si-Cu alloy film 27 of 550 nm, and a titanium nitride film are formed by a sputtering method. 26B to 30 nm
In this order, the upper electrode was formed by depositing in order, the separation groove 29 was formed, and 1000 polycrystalline silicon contact plugs were arranged in series. In the contact resistance evaluation substrate manufacturing process described above, the conventional method and the method of this example differ only in P / Si value at the time of forming an amorphous silicon thin film,
All other processes are the same.

The contact resistance of the produced contact resistance evaluation substrate was measured. As a result, contact 1
The resistance per hit is the resistance value (8
In the second embodiment, it is 45
It was greatly reduced to 0Ω. It has been found that the use of the means of this embodiment makes it possible to form a fine contact portion having a diameter of about 0.15 μm, which will greatly contribute to high integration of semiconductor devices in the future. Further, the P / Si value is set to 7.5 × 1 so that the phosphorus concentration in the film becomes 8 × 10 ²⁰ cm ^−2.
Even when the film was formed as 0 ^-2 , the same effect was obtained.

FIGS. 6A to 6C are sectional views of a semiconductor chip for explaining the third embodiment of the present invention. In the third embodiment, the present invention is applied to the capacitive electrode of a memory device.

First, as shown in FIG. 6A, As is ion-implanted into the surface of a P-type silicon single crystal substrate having a plane orientation of (100) to form an n ⁺ diffusion layer 32, and thermal diffusion is performed thereon. A silicon oxide film 33 having a thickness of 1 μm is formed, and a groove having a width of 1 μm is formed in the oxide film. Then, similarly to the second embodiment, the phosphorus concentration in the film is 3 × 10 ²⁰ cm ⁻³ (conventional example).
And 8 × 10 ²⁰ cm ⁻³ (Example) so that the P / Si values during film formation are 2.5 × 10 ⁻² and 7.5 × 1 respectively.
Amorphous silicon thin films of 30 nm and 100 nm are formed while P doping is performed at 0 ^−1.
Crystallization is performed by heat treatment at 30 ° C. for 30 minutes to form a polycrystalline silicon film 35.

Next, as shown in FIG. 6B, after patterning the polycrystalline silicon thin film 35 to form the lower electrode 35A, a capacitance insulating film 36 is formed to a thickness of 5 nm. Next, as shown in FIG. 6C, P / Si is used as the upper electrode 37.
= 2.5 × 10 ^-2 , 150n amorphous silicon film
A film was formed and polycrystallized by heat treatment at 850 ° C. for 30 minutes.

The characteristics of the capacitor thus manufactured were measured. From the high frequency C-V characteristics, + on the lower electrode
Table 1 shows the ratio (C / C ₀ ) between the capacitance value C when 3 V is applied and the capacitance value C ₀ near zero bias.

[0035]

[Table 1]

From Table 1, according to the conventional method, when the thickness of the lower electrode is reduced from 100 nm to 30 nm, the C / C ₀ value becomes 0.
It becomes smaller from 98 to 0.85, and it can be seen that depletion of carriers is widened in the polycrystalline silicon of the lower electrode. On the other hand, according to the third embodiment, 0.94 and C / C ₀
It can be seen that there is almost no decrease in the value, a sufficient amount of carriers are present in the polycrystalline silicon as compared with the conventional example, and a good electrode is formed.

[0037]

As described above, the present invention provides a method for forming a semiconductor thin film in which an amorphous silicon thin film having a thickness of 50 nm or less is deposited by a CVD method while introducing impurities and then polycrystallized by heat treatment. The impurity concentration is set to 5 × 10 ^{20 to} 2.5 × 10 ²¹ cm ^{−3 in a} range that compensates for the amount of impurity atom segregation due to thinning and does not cause deterioration of crystallinity or reduction of mobility due to impurity scattering. As described above, the ratio of the flow rate of the impurity-introduced gas to the flow rate of the film-forming gas is increased.
By increasing the film thickness to ˜0.2, it is possible to easily form a polycrystalline silicon thin film having a sufficiently low resistivity after crystallization.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the film thickness and the resistivity of a polycrystalline silicon thin film when the phosphorus concentration is changed.

FIG. 3 is a diagram showing a relationship between P / Si value and resistivity.

FIG. 4 is a diagram showing the relationship between the phosphorus concentration in a polycrystalline silicon film and the resistivity.

FIG. 5 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor chip for explaining a third embodiment of the present invention.

[Explanation of symbols]

11, 21 Silicon substrate 12, 23, 33 Silicon oxide film 13 Amorphous silicon thin film 14, 24, 35 Polycrystalline silicon thin film 22, 32 n ⁺ Diffusion layer 25 Titanium film 26A, 26B Titanium nitride film 27 Al-Si-Cu alloy film 28 Contact Hole 29 Separation Groove 35A Lower Electrode 36 Insulating Film 37 Upper Electrode

Claims (7)

[Claims] 1. A method of forming a semiconductor thin film in which an amorphous silicon thin film having a thickness of 50 nm or less is deposited by a CVD method while introducing an impurity and then polycrystallized by heat treatment, wherein an impurity is contained with respect to the number of silicon (Si) atoms in a reaction gas. A method for forming a semiconductor thin film, wherein the ratio (D / S) of the number of atoms D is set to 0.05 to 0.2. 2. The impurity concentration in the semiconductor thin film is 5 × 10 ^20.
2. The method for forming a semiconductor thin film according to claim 1, wherein the amount of impurities introduced is controlled so as to be about 2.5 × 10 ²¹ cm ⁻³ . 3. A method of forming a semiconductor thin film in which an amorphous silicon thin film having a thickness of 50 nm or less is deposited by a CVD method while introducing impurities and then polycrystallized by heat treatment, wherein the impurity concentration in the semiconductor thin film is 5 × 10 ²⁰ to
A method for forming a semiconductor thin film, which comprises controlling the amount of impurities to be introduced so as to be 2.5 × 10 ²¹ cm ⁻³ . 4. Silane (SiH ₄ ) or disilane (S
The method for forming a semiconductor thin film according to claim 1 or 3, wherein i ₂ H ₆ ) is used as a film forming gas. 5. The method for forming a semiconductor thin film according to claim 1, wherein phosphine (PH ₃ ) or tert-butylphosphine is used as a gas for introducing impurities. 6. The gas for introducing impurities contains arsine (As)
H ₃₎ or arsenic trichloride (AsCl ₃₎ or claim 1 or claim 3 method of forming a semiconductor thin film according using tertiary butyl arsine. 7. Diborane (B ₂
The method for forming a semiconductor thin film according to claim 1, wherein H ₆ ) is used.