JPH06313772A - Space filter type speed measuring apparatus, speed control system having the same and automobile - Google Patents

Abstract

PURPOSE:To provide a space filter type speed measuring apparatus in which a response time can be suppressed to short even if an averaging time is increased by providing a plurality of counters for counting number of pulses within a predetermined time. CONSTITUTION:A central frequency component proportional to a speed is extracted by a waveform shaper 4, this extracted signal is converted to pulses, and input to a plurality of counters 5-8. The number of output pulses from the shaper 4 is counted by the counters 5-8 in a predetermined time. In this case, a counting time of one counter is so counted as to be partly superposed with a counting time of at least the other counter, counted results are sequentially latched and output thereby to shorten a latching period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spatial filter type speed measuring device for measuring a ground speed in a non-contact manner, a speed control system equipped with this device, and an automobile. Circuit processing technology for enhancing

[0002]

2. Description of the Related Art Conventionally, in this type of spatial filter type velocity measuring device, a frequency signal proportional to the velocity of a moving object to be measured is detected and converted into a voltage, current, digital code or the like. It is converted and output. In general, because the spatial filter has a finite number of pitches and the measurement object has a random pattern, the detected frequency signal is not a single frequency signal, but a center proportional to the velocity of the measurement object. It becomes a narrow band irregular signal with a frequency. Therefore, in order to measure the speed with high accuracy, it is essential to perform averaging when converting the frequency signal into another physical quantity. (See "Measurement and Control" Vol. 19, No. 4)

[0003]

However, in such an averaging process, if the number of averagings is increased in order to improve the measurement accuracy, the response time also becomes longer in proportion to the number of averagings, and the actual speed is reduced. There is a problem that the time delay of the measurement speed becomes large. This problem is shown in Figure 4.
This will be explained using the conventional example shown in. The light from the measurement object is received by two sets of comb-teeth type photodiodes (hereinafter referred to as PD) 1 that form a spatial filter, and a common-mode component is removed from the output of PD1 in the differential amplifier circuit 2.
The tracking filter 3 removes noise frequency components. Then, the waveform shaping circuit 4 converts the sinusoidal signal output from the tracking filter 3 into a pulse, and the counter 55 counts the number of output pulses from the waveform shaping circuit 4 within a certain fixed time. The counting result is latched by the latch circuit 13 until the next counting is completed, and is output via the D / A converter 14. The counting result of the counter 55 is a value proportional to the average value of the frequency measurement values within a fixed time. Therefore, the averaging time becomes equal to the latch period.

The response time will be described with reference to FIG.
Now, here, the response time is defined as the maximum delay time of the measured speed with respect to the actual speed when the speed of the measurement object is decreasing at a constant deceleration. In the figure, t _n (n is an integer)
Is the time when the counting result of the counter 55 is latched, V _n
Represents the actual speed at time t _n , and S _n represents the measured speed latched at time t _n . This measurement speed S _n is
It is the average value of the actual speed from time t _n-1 to t _n , that is, (V _n-1 + V _n ) / 2. The delay time of t _n with respect to the time when the actual speed is equal to S _n is (t _n -t _n-1 ) /
2, which is half the averaging time. However, this value should be called the minimum delay time, and the maximum delay time is
This value is the value obtained by adding the latch cycle. Therefore, the response time is expressed as (averaging time / 2) + latch period.

As described above, since the averaging time and the latch period are equal to each other, the response time eventually becomes (averaging time × 1.
5), which is proportional to the averaging time. That is, if the number of times of averaging is increased in order to improve the measurement accuracy, the averaging time also becomes longer, and eventually the response time becomes longer in proportion to the number of times of averaging.

The present invention solves the above-mentioned problems. By providing a plurality of counters for counting the number of pulses within a fixed time, the response time can be kept short even if the averaging time is lengthened. An object of the present invention is to provide a spatial filter type speed measuring device, a speed control system including the same, and an automobile.

[0007]

In order to achieve the above object, the invention of claim 1 receives light from a relatively moving measuring object, and from the received optical signal the speed of the measuring object. In a spatial filter type velocity measuring device for measuring a velocity by extracting and measuring a center frequency component proportional to, a waveform shaping circuit for extracting the center frequency component from a received optical signal and obtaining a pulse output from the extracted signal And a plurality of counters for counting the number of output pulses from the waveform shaping circuit within a predetermined time, and among these counters, the counting time of one counter is partially counted by at least another counter. It is designed to overlap with time. The invention according to claim 2 is a speed control system comprising the spatial filter type speed measuring device according to claim 1, wherein the speed is controlled by controlling a brake or an accelerator by the output of this device. The invention according to claim 3 is an automobile equipped with the speed control system according to claim 2.

[0008]

According to the structure of claim 1, the waveform shaping circuit extracts the central frequency component proportional to the speed from the received light signal from the object to be measured, the extracted signal is converted into a pulse, and the plurality of counters are provided. Is entered. These counters count the number of output pulses from the waveform shaping circuit within a predetermined time. At this time, the counting time of one counter is counted so as to partially overlap with the counting time of at least one other counter, and these counting results are sequentially latched and output, thereby shortening the latch cycle. can do. According to the configuration of claim 2, by controlling the brake or the accelerator by the output of this device, efficient braking or acceleration becomes possible. According to the structure of claim 3, efficient braking / accelerating ability can be obtained.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a processing circuit of a spatial filter type velocity measuring device. The configuration different from the conventional example described above is provided with a plurality of counters (5 to 8) for counting the number of output pulses from the waveform shaping circuit 4, and further each counter 5
The point is that buffers 9 to 12 for storing the outputs of to 8 are provided. The reset signal of each counter 5-8, the output control signal of each buffer 9-12, and the control signal of the latch circuit 13 are output from the timing circuit 15. In this embodiment, four counters 5 to 8 and four buffers 9 to 12 are connected in parallel.

FIG. 2 is a timing chart of the control of the counters 5-8, the buffers 9-12, and the latch circuit 13 by the timing circuit 15. In the figure, RE1 to 4 are reset timings of the counters 5 to 8 and BU bars 1 to 4
Indicates the open timing of each buffer 9 to 12, and LD bar indicates the latch timing of the latch circuit 13. The cycle of each counter reset and each buffer open, that is, the averaging time is T, and the reset timing of each counter and the open timing of each buffer are set with a phase delay of T / 4. Also, multiple buffers are never opened at the same time. Immediately before each counter is reset, the value counted by the counter until then is latched by the latch circuit 13. Because of this and the reset timing of each counter being delayed by T / 4, the latch cycle becomes T / 4.

As mentioned above, the averaging time is T,
Since the latch period is T / 4, the response time is (averaging time / 2) + latch period = averaging time × 0.7
It becomes 5. For example, assuming that the averaging time is 30 ms, in the conventional technique, the latch period is 30 as shown in FIG.
ms, and the response time is 45 ms. On the other hand, in this embodiment, as shown in FIG. 3A, the latch period is shortened to 7.5 ms and the response time is shortened to 22.5 ms, which is half that of the conventional case. Further, comparing FIGS. 3A and 3B, it can be seen that in the case of (a) having four counters of this embodiment, as compared with the case of only one conventional counter (b). It can be seen that the measured speed value becomes finer than the actual speed.

As described above, by providing a plurality of counters, the response time can be shortened as compared with the conventional case when the averaging time and the measurement accuracy are the same. Further, even if the averaging time is lengthened to improve the measurement accuracy, the response time can be suppressed to be short. Note that the number of counters is not limited to four in the above-described embodiment, and a plurality of counters may be used. In that case, the number of buffers may be the number of counters.

An antilock brake system (ABS) for controlling the brake so as not to lock, and a traction control for controlling the accelerator by using the output of the spatial filter type speed measuring device which performs the above circuit processing. It is also possible to construct a speed control system such as a system (TCL). In addition, by installing this speed control system in an automobile, efficient braking
Acceleration ability is obtained.

[0014]

As described above, according to the invention of claim 1,
Provided with a plurality of counters for counting pulses having a frequency proportional to the velocity of the measuring object detected by the spatial filter,
Among these counters, the counting time of one counter is partially overlapped with the counting time of at least one other counter, and immediately before each counter is reset, the count value of the counter up to that time is latched. Therefore, the latch cycle can be shortened. As a result, even if the averaging time is lengthened in order to improve the measurement accuracy, the response time can be kept short, and therefore the time delay of the measurement speed with respect to the actual speed can be reduced. According to the second aspect of the present invention, since the speed measurement value with high accuracy can be obtained by lengthening the averaging time, it becomes possible to perform efficient brake or accelerator control, and shorten or reduce the braking distance. It can be expected to have high acceleration. According to the invention of claim 3, the braking distance is shortened, the acceleration performance is improved, and the safety of the automobile is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a processing circuit of a spatial filter type velocity measuring device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the processing circuit.

FIG. 3A is an explanatory diagram of a response time with respect to a speed change according to the present embodiment, and FIG.

FIG. 4 is a block diagram of a processing circuit of a conventional spatial filter type velocity measuring device.

FIG. 5 is a diagram for explaining the definition of response time with respect to speed change.

[Explanation of symbols]

 4 waveform shaping circuit 5, 6, 7, 8, 55 counter 9, 10, 11, 12 buffer 13 latch circuit 15 timing circuit

Claims (3)

[Claims] 1. A space for measuring speed by receiving light from a relative moving measurement object, extracting a center frequency component proportional to the speed of the measurement object from the received optical signal, and measuring the center frequency component. In the filter type speed measurement device, the center frequency component is extracted from the received optical signal and the waveform shaping circuit that obtains a pulse output from the extracted signal and the number of output pulses from the waveform shaping circuit within a predetermined time are counted. A spatial filter type velocity measuring device, comprising: a plurality of counters, wherein the counting time of one of these counters partially overlaps with the counting time of at least one other counter. . 2. A speed control system comprising the spatial filter type speed measuring device according to claim 1, wherein the speed is controlled by controlling a brake or an accelerator according to the output of the device. 3. An automobile equipped with the speed control system according to claim 2.