JPH06309873A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device which can prevent erroneous recognition of output data by reducing the undershoot, etc., of ringing caused by an abrupt change of output. CONSTITUTION:The semiconductor storage device is constituted of a latch circuit 30 which holds an outputting state synchronously to a system clock signal K, delay circuit which rewrites the content in the latch circuit 30 based on a one-shot pulse (x) related to the signal K, circuit composed of a NAND circuit and inverter, and output circuit 11 which outputs the content of the latch circuit 30. In addition, the latch circuit 30 maintains its output at a prescribed level before the output of the output circuit 11 changes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed semiconductor memory device such as a CDRAM or SDRAM, and in particular, reduces undershoot of ringing due to abrupt voltage change to prevent misidentification of output data. The present invention relates to a semiconductor memory device that can be used.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a conventional semiconductor memory device, for example, an output circuit of a synchronous device and a latch circuit in the preceding stage of the output circuit for holding output data.

In the figure, 1 is an input terminal to which a data DB (internal data line signal) is supplied, and this input terminal 1 is connected to one input terminal of a NOR circuit 4. Reference numeral 2 is an input terminal to which the latch enable signal / DOT is supplied, and this input terminal 2 is connected to the other input terminals of the NOR circuits 4 and 8, respectively. The output terminal of the NOR circuit 4 is connected to the inverter 5, and the output terminal of the inverter 5 is connected to one input terminal of the NAND circuit 6.

Reference numeral 7 denotes an input terminal to which a data DB bar (hereinafter referred to as data IDB) having a phase different from that of the data DB by 180 ° is supplied. This input terminal 7 is connected to one input terminal of a NOR circuit 8 and The output terminal of the NOR circuit 8 is connected to the input terminal of the inverter 9, and the output terminal of the inverter 9 is connected to one input terminal of the NAND circuit 10.
The other input terminal of the NAND circuit 10 is the NAND circuit 6
Of the NAND circuit 6 and the other input terminal of the NAND circuit 6 is connected to the output terminal of the NAND circuit 10. Here, the NOR circuits 4 and 8, the inverters 5 and 9,
The NAND circuits 6 and 10 constitute the latch circuit 3 at the output front stage.

The output terminal of the NAND circuit 6 is the gate of the P-type MOS transistor 12 and the N-type MOS transistor 15.
Respectively, the source of the P-type MOS transistor 12 is connected to the drain of the P-type MOS transistor 13, the drain of the P-type MOS transistor 12 is connected to the gate of the N-type MOS transistor 17, and the P-type MOS transistor 13 is connected. Of the P type MOS transistor 13 is connected to the gate of the N type MOS transistor 16 and the gate of the N type MOS transistor 21, respectively.

The drain of the N-type MOS transistor 15 and the drain of the N-type MOS transistor 16 are connected to each other, the connection point is connected to the gate of the N-type MOS transistor 17, and the source of the N-type MOS transistor 15 and the N-type MOS transistor are connected. The source of the transistor 16 is connected and the connection point is grounded. The connection point between the drain of the P-type MOS transistor 13 and the source of the P-type MOS transistor 12 is connected to the source of the P-type MOS transistor 19. The source of the N-type MOS transistor 17 is connected to the power supply terminal 18, and the drain of the N-type MOS transistor 17 is connected to the drain of the N-type MOS transistor 22.

On the other hand, the output terminal of the NAND circuit 10 is a P-type M
The gate of the OS transistor 19 and the gate of the N-type MOS transistor 20 are respectively connected, and the drain of the N-type MOS transistor 20 and the N-type MOS transistor 2 are connected.
1 is connected to the drain, and this connection point is connected to the drain of the P-type MOS transistor 19 and the N-type MO transistor.
The source of the N-type MOS transistor 20 and the N-type MOS transistor 2 are connected to the gate of the S-transistor 22.
The source of 1 is connected, and the connection point is grounded.

The source of the N-type MOS transistor 22 is grounded, and the output terminal 23 is led out from the connection point of the drain of the N-type MOS transistor 22 and the drain of the N-type MOS transistor 17. Here, P-type MOS transistors 12, 13 and 19, and N-type MOS transistor 1
The output circuit 11 is composed of 5, 16, 17, 20, 21, and 22.

Next, the operation will be described with reference to FIG. First, the operation of this circuit will be briefly described. Now, when the synchronous device is read, data in the synchronous device is shown in FIGS. 7B and 7C in synchronization with the external system clock signal K shown in FIG. 7A. The data DB and IDB respectively shown are supplied to one input terminal of each of the NOR circuits 4 and 8.

Here, when the latch enable signal / DOT supplied to the other input terminals of the OR circuits 4 and 8 shown in FIG. 7D is at the high level "1", the data DB
Although / and / DB are not captured by the latch circuit 3, the data DB and / DB are captured by the latch circuit 3 when the latch enable signal / DOT is at low level "0".
Then, after the fetched data is amplified in the output circuit 11, as shown in FIG.
Is output as output data Dout from. During this period, the output enable signal / OEM shown in FIG. 7K is activated to the low level "0".

Next, the operation of this circuit will be described in detail.
Now, when the synchronous device is read, when the data DB and / DB in the synchronous device are supplied to the respective input terminals of the NOR circuits 4 and 8 in synchronization with the system clock signal K, the OR circuit 4 NOR gates 4 and 8 when the latch enable signal / DOT supplied to the other input terminals of
Signals S1 and S3 as shown in FIG. 7E and FIG.

These signals S1 and S3 are inverted by inverters 5 and 9, respectively, to become signals S2 and S4 as shown in FIGS. 7F and 7H. The signals S2 and S4 are supplied to one input terminals of the NAND circuits 6 and 10, respectively. The output signals S5 and S6 of the NAND circuits 10 and 6 are supplied to the other input terminals of the NAND circuits 6 and 10, respectively. Therefore, at the output side of the NAND circuits 10 and 6, the output signals S5 and S as shown in FIGS.
6 is taken out as an output signal of the latch circuit 3 and supplied to the output circuit 11 of the next stage. During the operation of the output circuit 11, the output enable signal / OEM is activated to the low level "0" as shown in FIG.
Is on and the transistors 16 and 21 remain off.

Now, looking at the operation at time t1, the signal S5 changes from the high level "1" to the low level "0", and the signal S6 changes from the low level "0" to the high level "1". In the case, that is, when the data DB and the latch enable signal / DOT are both low level “0”, the signal S5 is low level “0”, and the signal S6 is high level “1”, the high level “1” of the signal S6 Thus, the transistor 12 is turned off and the transistor 15 is turned on. When the transistor 15 is turned on, the gate of the transistor 17 is grounded and the transistor 17 is turned off. On the other hand, the low level "0" of the signal S5 causes the transistor 2
0 turns off, transistor 19 turns on, and power supply terminal 1
The current from 4 flows to the gate of the transistor 22 via the transistors 13 and 19 to turn it on, and as a result, the output data Dout of low level "0" is output to the output terminal 23 as shown in FIG. 7L.

Next, looking at the operation at time t2, the signal S5 changes from low level "0" to high level "1".
When the signal S6 changes from the high level “1” to the low level “0”, that is, the data DB is the high level “1”, the latch enable signal / DOT is the low level “0”, and the signal S5 is When the high level "1" and the signal S6 are low level "0", the transistor 20 is turned on and the transistor 19 is turned off by the high level "1" of the signal S5, and the gate of the transistor 22 is grounded when the transistor 20 is turned on. The transistor 22 is turned off. On the other hand, the low level "0" of the signal S6 turns on the transistor and turns off the transistor 15, and the current from the power supply terminal 14 flows through the transistors 13 and 12 to the gate of the transistor 17 to turn it on, resulting in the output. The output data Dout of high level “1” is output to the terminal 23 as shown in FIG. 7L.

[0015]

Since the conventional semiconductor memory device is constructed as described above, if the system clock signal K causes the output data Dout to be high level "1".
If the level changes from 0 to low level “0” or from low level “0” to high level “1”, output ringing occurs due to abrupt voltage change. In this case, there is a problem that the output data Dout is recognized as a high level "1" even though the output data Dout is a low level "0" due to undershoot.

The present invention has been made to solve the above problems, and a semiconductor capable of preventing erroneous recognition of output data by reducing an undershoot of ringing caused by a sudden change of output data. The purpose is to obtain a storage device.

[0017]

In a semiconductor memory device according to the present invention, holding means for holding an output state in synchronization with a clock signal, and rewriting the contents of the holding means based on a signal related to the clock signal. The rewriting means and the output means for outputting the contents of the holding means are provided, and the holding means holds the output at a predetermined level before the output of the output means changes.

[0018]

According to the present invention, the contents of the holding means for holding the output state in synchronization with the clock signal are rewritten by the rewriting means, and the output of the output means is held at a predetermined level before the output changes. As a result, the undershoot of the ringing of the output due to the abrupt voltage change is prevented, and the erroneous recognition of the output data Dout is avoided.

[0019]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, parts corresponding to those in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, 31 is an input terminal to which a one-shot pulse x generated by using a system clock signal K as a trigger to supply the above-mentioned output data Dout to a low level “0” standby state is supplied, as will be described later. 31 is connected to the input terminal of the inverter 32, and the output terminal of the inverter 32 is connected to the input terminal of the NAND circuit 33. The output terminal of the inverter 5 and the output terminal of the NAND circuit 10 are also connected to the NAND circuit 2.
Connect to the input terminal of 8. Further, the output terminal of the NAND circuit 33 is connected to the input terminal of the NAND circuit 10. here,
The NOR circuits 4 and 8, the inverters 5, 9 and 32, and the NAND circuits 10 and 33 constitute a latch circuit 30 as a holding unit.

Next, the operation will be described with reference to FIG. First, the operation of this circuit will be briefly described. Now, when the synchronous device is read, data in the synchronous device is shown in FIGS. 2B and 2C in synchronization with the external system clock signal K shown in FIG. 2A. The data DB and / DB respectively shown are supplied to one input terminal of each of the NOR circuits 4 and 8. Here, when the latch enable signal / DOT supplied to the other input terminals of the OR circuits 4 and 8 shown in FIG. 2D is at the high level “1”, the data DB and / DB are not taken into the latch circuit 30. However, when the latch enable signal / DOT is at the low level "0", the data DB and / DB are taken into the latch circuit 30.

At this time, the one-shot pulse x shown in FIG. 2E, which is generated by using the system clock signal K as a trigger.
Is supplied, the data DB and / DB temporarily enter a standby state from high level "1" to low level "0" (or low level "0" to high level "1"). And the latch enable signal / DOT shown in FIG. 2D
Becomes low level "0", the data DB and / DB are taken into the latch circuit 30. Then, the fetched data is amplified in the output circuit 11 serving as the output means, and then output from the output terminal 23 as the output data Dout, as shown in FIG. 2N. During this period, the output enable signal / OEM shown in FIG. 2M is activated to the low level "0".

Therefore, when the output data Dout is output from the output terminal 23, that is, the output enable signal / O.
When the EM is at the low level "0", the output data Dout is always in the standby state of the low level "0" as shown in FIG. 2N, so that the undershoot of ringing can be prevented, and thus the output data Dout of the output data Dout can be prevented. False positives can be avoided.

Next, the operation of this circuit will be described in detail.
Now, when the synchronous device is read, if the data DB and / DB in the synchronous device are supplied to the respective input terminals of the NOR circuits 4 and 8 in synchronization with the system clock signal K, the OR circuit 4 NOR gates 4 and 8 when the latch enable signal / DOT supplied to the other input terminals of
The signals S1 and S3 as shown in FIG. 2F and FIG. These signals S1 and S3 are inverted by inverters 5 and 9, respectively, and are inverted in FIGS. 2G and 2I.
Signals S2 and S4 as shown in FIG. The signals S2 and S4 are supplied to one input terminals of the NAND circuits 33 and 10, respectively. The output signals S5 and S6 of the NAND circuits 10 and 33 are supplied to the other input terminals of the NAND circuits 33 and 10, respectively.

Further, the one-shot pulse x as shown in FIG. 2C, which is generated by using the clock signal K as a trigger to bring the output data Dout into the low level “0” standby state, is supplied from the input terminal 31, and the inverter 32 is supplied. The signal S7 shown in FIG. 2J is inverted and is supplied to the other input terminal of the NAND circuit 33. Therefore, the output signals S8 and S9 as shown in FIGS. 2K and 2L are finally output to the output side of the NAND circuits 10 and 33.
Is output as an output signal and is supplied to the output circuit 11 of the next stage.

During the operation of the output circuit 11, the output enable signal / OEM is activated to the low level "0" as shown in FIG. 2M, so that the transistor 13 remains on and the transistors 16 and 21 remain off. . So now,
Looking at the operation at the time point t1, the signal S8 changes from the high level “1” to the low level “0”, and the signal S9
Changes from low level "0" to high level "1", that is, data DB is low level "0", latch enable signal / DOT is high level "1", and one-shot pulse x is high level "1". When the signal S8 is at the low level "0" and the signal S9 is at the high level "1", the signal S
High level "1" of 9 turns off transistor 12,
The transistor 15 is turned on, the gate of the transistor 17 is grounded when the transistor 15 is turned on, and the transistor 17 is turned off.

On the other hand, the low level "0" of the signal S8 turns off the transistor 20 and turns on the transistor 19, so that the current from the power supply terminal 14 is applied to the transistors 13 and 1.
The gate of the transistor 22 is turned on via 9 to turn it on, and as a result, the output terminal 23 becomes low level "0" as shown in FIG. 2N, and the output data Dout is substantially in a standby state.

Next, looking at the operation at the time point t2, when the data DB, the latch enable signal / DOT, and the one-shot pulse x are all at the low level "0",
Similar to the time point t1, the signal S8 is low level "0", and the signal S9 is
Is high level "1", the output circuit 11 operates in the same manner as described above, and as a result, output data Dout of low level "0" is output to the output terminal 23 as shown in FIG. 2N.
Therefore, since the output data Dout is substantially held at the low level "0" at the time point t1, the output data Dout captured at the low level "0" of the latch enable signal / DOT is at the high level "0" at the time point t2. Even if the level changes from "1" to low level "0", the undershoot due to the ringing does not occur.

Next, looking at the operation at the time point t3, when the data DB, the latch enable signal / DOT, and the one-shot pulse x are all at the high level "1",
Since the signal S8 is at the low level "0" and the signal S9 is at the high level "1" as at the times t1 and t2, the output circuit 11 operates as described above, and as a result, the output terminal 23 is at the low level as shown in FIG. 2N. It becomes “0” and output data Do
ut goes into standby.

Next, looking at the operation at time t4, the signal S8 changes from low level "0" to high level "1".
When the signal S9 changes from the high level "1" to the low level "0", the high level "1" of the signal S9 turns on the transistor 20 and the transistor 19 is turned off. Is grounded and the transistor 22 is turned off. On the other hand, the low level "0" of the signal S9 turns on the transistor, turns off the transistor 15, and the current from the power supply terminal 14 flows through the transistors 13 and 12 to the gate of the transistor 17 to turn it on, resulting in the output. The output data Dout of high level "1" is output to the terminal 23 as shown in FIG. 2N.

Thus, the output data Dout is output to the output terminal 23.
2D, that is, when the output enable signal / DOT shown in FIG. 2D is low level “0”, the output data Dout is always in the standby state of low level “0” as shown in FIG. Of the output data Dout can be avoided.

FIG. 3 shows an external system clock signal K.
3 is a configuration diagram showing a circuit as a rewriting unit for generating the above-mentioned one-shot pulse x by utilizing the rising edge of the. In the figure, reference numeral 40 is an input terminal to which the system clock signal K shown in FIG. 2A is supplied, and this input terminal 40 is connected to the input terminal of the delay circuit 41 and the NAND circuit 4.
2 is connected to one of the input terminals of the delay circuit 41, and the output terminal of the delay circuit 41 is connected to the other input terminal of the NAND circuit 42.
The output terminal of the NAND circuit 42 is connected to the output terminal 44 via the inverter 43.

Next, the operation will be described. Input terminal 40
2A is externally supplied to the system clock signal K shown in FIG.
And the NAND circuit 42, respectively. Delay circuit 4
1, the system clock signal K supplied to the delay circuit 41
Is supplied to the NAND circuit 42 after being delayed by a predetermined time.

In the NAND circuit 42, the input terminal 40
System clock signal K supplied from the delay circuit 41
ANDed with the delayed clock signal from. The output of the NAND circuit 42 is inverted by the inverter 43 and converted into the one-shot pulse x shown in FIG.
Is supplied to the latch circuit 30 shown in FIG. When this one-shot pulse x is supplied to the inverter 32 of the latch circuit 30, inverted, and further supplied to the NAND circuit 33, the transistor 17 of the output circuit 11 is turned off, the transistor 13 is turned on, and the output data Dout is output as described above. Becomes a low level "0" standby state.

As described above, in the present embodiment, the one-shot pulse x is generated by the system clock signal K and the delayed one of the system clock signal K, and the one-shot pulse x forces the output data Dout. Since the standby state of the low level "0" is set, the undershoot of the ringing due to the change of the output can be prevented, and the erroneous recognition of the output data Dout can be avoided.

Example 2. Although the operation of the synchronous device is completed in one cycle of the system clock signal K in the above embodiment, the operation of the system device may be completed in two cycles of the system clock signal K. This will be described with reference to FIG. 4, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

The circuit configuration is the same as that shown in FIG. 1, but the circuit system for generating the one-shot pulse x is different. That is, as shown in FIG. 4, in this example, the system clock signal K supplied through the input terminal 40 is divided into ½ by the frequency divider 45, and the clock signal for two cycles is divided into one cycle. Minute clock signal K1. The clock signal K1 and a signal obtained by delaying the clock signal K1 by the delay circuit 41 for a predetermined time are used in the NAND circuit 4
The logical product is obtained by 2 and the output signal is inverted by the inverter 42 and output as the one-shot pulse x1 from the output terminal 44.

Next, the operation will be described with reference to FIG. FIG. 5 is a timing chart when the operation of the synchronous device is completed within two cycles of the system clock signal K by using the clock signal K1 generated by the circuit system described in FIG. In FIG. 5, parts corresponding to those in FIG. Now, when the synchronous device is read, the data in the synchronous device is synchronized with the external system clock signal K shown in FIG. 5A as data DB and / DB shown in FIGS. 5C and 5D, respectively. , And 8 respectively. Here, FIG. 5E
When the latch enable signal / DOT supplied to the other input terminal of each of the OR circuits 4 and 8 shown in FIG.
Not latched to 0 but latch enable signal / DOT
Is low level "0", the data DB and / DB are taken into the latch circuit 30.

At this time, when the one-shot pulse x1 shown in FIG. 5F is supplied by using the clock signal K1 shown in FIG. 5B generated based on the system clock signal K as a trigger, the data DB and / DB temporarily go to high level. The standby state changes from "1" to low level "0" (or low level "0" to high level "1"). Then, the latch enable signal / DOT shown in FIG. 5E is at the low level “0”.
Then, the data DB and / DB are taken into the latch circuit 30. Then, after being amplified in the output circuit 11, it is output as output data Dout from the output terminal 23 as shown in FIG. 5O. During this period, the output enable signal / OEM shown in FIG. 5N is activated to the low level "0".

Therefore, when the output data Dout is output from the output terminal 23, that is, the output enable signal / O.
When the EM is at the low level “0”, the output data Dout is always in the standby state of the low level “0” as shown in FIG. 5O, so that the undershoot of ringing can be prevented, and the output data Dout is erroneously recognized. Can be avoided.

As described above, in this embodiment, the one-shot pulse x1 is generated by the frequency-divided signal K1 of the system clock signal K and the delayed signal of the frequency-divided signal K1.
Since the output data Dout is forcibly set to the standby state of low level “0” by this one-shot pulse x1, it is possible to prevent the undershoot of ringing due to the change of the output, and thereby the output data Dout of the output data Dout is prevented. False positives can be avoided.

Example 3. In the above embodiment, the case where the ringing undershoot due to the change in the output is prevented has been described. However, the ringing overshoot due to the change in the output can be similarly applied and the same effect can be obtained.

[0042]

As described above, according to the present invention, the holding means for holding the output state in synchronization with the clock signal, and the rewriting means for rewriting the contents of the holding means based on the signal related to the clock signal. And output means for outputting the content of the holding means, and the holding means holds the output at a predetermined level before the output of the output means changes, so that the output is abruptly changed. There is an effect that it is possible to eliminate adverse effects such as undershoot of ringing and avoid misidentification of output data.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the semiconductor memory device according to the present invention.

FIG. 3 is a block diagram showing a main part of an embodiment of a semiconductor memory device according to the present invention.

FIG. 4 is a block diagram showing a main part of another embodiment of the semiconductor memory device according to the present invention.

FIG. 5 is a timing chart for explaining the operation of another embodiment of the semiconductor memory device according to the present invention.

FIG. 6 is a circuit diagram showing a conventional semiconductor memory device.

FIG. 7 is a timing chart for explaining the operation of the conventional semiconductor memory device.

[Explanation of symbols]

 30 latch circuit 41 delay circuit 42 NAND circuit 43 inverter 45 frequency divider circuit

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] September 9, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

Reference numeral 7 is an input terminal to which a data DB bar (hereinafter, referred to as data / DB) whose phase is 180 ° different from that of the data DB is supplied. This input terminal 7 is connected to one input terminal of the NOR circuit 8, The output terminal of the NOR circuit 8 is connected to the input terminal of the inverter 9, and the output terminal of the inverter 9 is connected to one input terminal of the NAND circuit 10.
The other input terminal of the NAND circuit 10 is the NAND circuit 6
Of the NAND circuit 6 and the other input terminal of the NAND circuit 6 is connected to the output terminal of the NAND circuit 10. Here, the NOR circuits 4 and 8, the inverters 5 and 9,
The NAND circuits 6 and 10 constitute the latch circuit 3 at the output front stage.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

Next, the operation will be described with reference to FIG. First, the operation of this circuit will be briefly described. Now, when the synchronous device is read, data in the synchronous device is shown in FIGS. 7B and 7C in synchronization with the external system clock signal K shown in FIG. 7A. The data DB and / DB respectively shown are supplied to one input terminal of each of the NOR circuits 4 and 8.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

Next, looking at the operation at time t2, the signal S5 changes from low level "0" to high level "1".
When the signal S6 changes from the high level “1” to the low level “0”, that is, the data DB is the high level “1”, the latch enable signal / DOT is the low level “0”, and the signal S5 is When the high level "1" and the signal S6 are low level "0", the transistor 20 is turned on and the transistor 19 is turned off by the high level "1" of the signal S5, and the gate of the transistor 22 is grounded when the transistor 20 is turned on. The transistor 22 is turned off. On the other hand, the low level "0" of the signal S6 causes the transistor 1
2 turns on, transistor 15 turns off, and power supply terminal 1
The current from 4 flows to the gate of the transistor 17 through the transistors 13 and 12 to turn it on, and as a result, the output terminal 23 is set to the high level "1" as shown in FIG. 7L.
The output data Dout of is output.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

[0019]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, parts corresponding to those in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, reference numeral 31 denotes an input terminal to which a one-shot pulse x generated by using a system clock signal K as a trigger for supplying the above-mentioned output data Dout to a low level “0” standby state is supplied, as will be described later. 31 is connected to the input terminal of the inverter 32, and the output terminal of the inverter 32 is connected to the input terminal of the NAND circuit 33. Further, the output terminal of the inverter 5 and the output terminal of the NAND circuit 10 are also connected to the NAND circuit 3
Connect to the input terminal of 3 . Further, the output terminal of the NAND circuit 33 is connected to the input terminal of the NAND circuit 10. here,
The NOR circuits 4 and 8, the inverters 5, 9 and 32, and the NAND circuits 10 and 33 constitute a latch circuit 30 as a holding unit.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

Next, the operation of this circuit will be described in detail.
Now, when the synchronous device is read, if the data DB and / DB in the synchronous device are supplied to the respective input terminals of the NOR circuits 4 and 8 in synchronization with the system clock signal K, the OR circuit 4 NOR gates 4 and 8 when the latch enable signal / DOT supplied to the other input terminals of
The signals S1 and S3 as shown in FIG. 2F and FIG. These signals S1 and S3 are inverted by inverters 5 and 9, respectively, and are inverted in FIGS. 2G and 2I.
Signals S2 and S4 as shown in FIG. The signals S2 and S4 are supplied to one input terminals of the NAND circuits 33 and 10, respectively. The output signals S 8 and S 9 of the NAND circuits 10 and 33 are supplied to the other input terminals of the NAND circuits 33 and 10, respectively.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

During the operation of the output circuit 11, the output enable signal / OEM is activated to the low level "0" as shown in FIG. 2M, so that the transistor 13 remains on and the transistors 16 and 21 remain off. . So now,
Looking at the operation at the time point t1, the signal S8 changes from the high level “1” to the low level “0”, and the signal S9
If There has changed from the low level "0" to high level "1", i.e., the data DB is the low level "0", the latch enable signal / DOT is the high level "1", the one-shot pulse x is high level "1 , The signal S8 is low level "0" and the signal S9 is high level "1", the signal S
High level "1" of 9 turns off transistor 12,
The transistor 15 is turned on, the gate of the transistor 17 is grounded when the transistor 15 is turned on, and the transistor 17 is turned off.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

Next, looking at the operation at time t4, the signal S8 changes from low level "0" to high level "1".
Changes to, when the signal S9 changes from the high level "1" to low level "0", the high level "1" signal S 8 transistor 20 is turned on, the transistor 19 is turned off, the transistor by turning on the transistor 20 The gate of 22 is grounded and the transistor 22 is turned off. On the other hand, the low level "0" of the signal S9 causes the transistor 1
2 turns on, transistor 15 turns off, and power supply terminal 1
The current from 4 flows to the gate of the transistor 17 through the transistors 13 and 12 to turn it on, and as a result, the output terminal 23 has a high level "1" as shown in FIG. 2N.
The output data Dout of is output.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

The circuit configuration is the same as that shown in FIG. 1, but the circuit system for generating the one-shot pulse x is different. That is, as shown in FIG. 4, in this example, the system clock signal K supplied through the input terminal 40 is divided into ½ by the frequency divider 45, and the clock signal for two cycles is divided into one cycle. Minute clock signal K1. The clock signal K1 and a signal obtained by delaying the clock signal K1 by the delay circuit 41 for a predetermined time are used in the NAND circuit 4
2 ANDed, so as to output the output signal from the output terminal 44 is inverted by an inverter 4 3 as a one-shot pulse x1.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

Example 3. In the above embodiment has described the case to prevent Ann Dark-shot ringing based on a change in output, it can be applied similarly when the overshoot ringing based on a change in the output, the same effects.

[Procedure Amendment 10]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H03K 17/687 19/0175 7436-5J H03K 17/687 F 8941-5J 19/00 101 F

Claims (1)

[Claims] 1. A holding means for holding an output state in synchronization with a clock signal, a rewriting means for rewriting the contents of the holding means based on a signal related to the clock signal, and an output for outputting the contents of the holding means. And a holding means for holding the output of the output means at a predetermined level before the output of the output means changes.