JPH06309272A - Memory access method - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a memory access method, and in particular, provides a memory access method that enables direct access to a buffering memory of various control units from a processor unit via a system bus. The purpose is to [Configuration] A bus control unit 1 connected to a system bus,
In a control unit memory access method having a DMA controller 2 and a buffering memory 3, the control unit includes a register for temporarily holding data, and the address of the buffering memory 3 sent from the processor unit 7 is temporarily held in the register. Then, when the input / output control signal is received thereafter, the input / output of data is executed with respect to the address of the buffering memory 3 temporarily held in the register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method for a control unit having a buffering memory,
In particular, when data is transferred between a plurality of processors and speed matching is performed between systems having different processing speeds, a control unit such as an input / output control unit or a communication control unit having a function of temporarily holding data in the memory is used. The present invention relates to a memory access method.

[0002]

2. Description of the Related Art In recent years, a system having a plurality of processors in which processing is distributed for each function has been constructed in response to a demand for high speed communication of a computer utilizing system. In such a computer system, a buffer for temporarily storing data in the memory by DMA (Direct Memory Access) in order to increase the communication speed and the processing speed and to perform communication between functional processes having different processing speeds. Rings are often held.

For example, in a computer system composed of a plurality of functional units such as a processor unit for controlling the entire system and a display unit dedicated for display, input / output for performing high-speed data transfer with an external input / output device. The control unit and the communication control unit for speed matching with the external communication line have a buffering memory inside, and once the data is stored in the buffering memory by DMA, the data is transferred. .

Conventionally, in such a system, each unit is connected by a system bus commonly used among the units, and an address assigned to a partner unit to be accessed is designated and a DMA inside the unit is designated.
Data is transferred by DMA by setting the controller.

[0005]

However, the conventional DMA
A unit having a buffering function for transfer uses a buffering memory to which an address unique to the unit is added, so that the address of the buffering memory is directly specified from an external unit through the system bus. I couldn't.

In a unit having a buffering memory, access to the normal buffering memory is D
There is a problem that it is necessary to set the MA transfer, and even when confirming a partial change of the data in the buffering memory, the DMA transfer has to be performed, which rather causes a processing time.

Therefore, the present invention has been made in consideration of the above circumstances, and a memory which enables direct access from a processor unit via a system bus to a buffering memory of various control units. The purpose is to provide access methods.

[0008]

FIG. 1 shows a block diagram for explaining the principle configuration of the present invention. 1, a bus controller 1 connected to a system bus 8 which is an address and data transmission path, a DMA controller 2, an address latch buffer 4, and a buffering memory 3 for temporarily storing data. A memory access of the control unit which is connected to the processor unit 7 by the system bus 8 and which receives the input / output control signal from the processor unit 7 and DMA-transfers the data to the buffering memory 3 in the control unit. In the method, the control unit includes a register for temporarily holding data, temporarily holds the address of the buffering memory 3 sent from the processor unit 7 in the register, and then receives an input / output control signal sent from the processor unit 7. When temporarily held in the register Against address of the buffer ring memory 3, there is provided a memory access method of a control unit and executes the input and output of data.

Further, in the control unit, a set register 5 for temporarily holding an address to be accessed in the buffering memory 3 and an enable signal for receiving the input / output control signal and permitting memory access are set register 5.
When the window register 6 for outputting to the set register 5 is received from the processor unit 7, the data is written to the address of the buffering memory 3 or the address of the address. It is set in the set register 5 as a part of it, and then set in the set register 5 when an input / output control signal for writing or reading data sent from the processor unit 7 to the window register 6 is received. An address of the buffering memory 3 or a part of the address may be used to specify a memory address to be accessed and input / output of data to / from the buffering memory 3.

[0010]

From the processor unit 7, via the system bus 8, the address of the register in the control unit to be accessed is specified, and the input / output control signal for writing in which the address of the buffering memory 3 is used as data is output. Send to control unit.

The bus control unit 1 of the control unit analyzes this input / output control signal and temporarily holds the received data, that is, the address of the buffering memory 3 in a register.

Next, when the control unit receives the input / output control signal sent from the processor unit 7, the bus control unit 1 inputs / outputs data to / from the address of the buffering memory 3 temporarily held in the register. Run.

With the above operation, the processor unit 7 can directly access the buffering memory 3 in the control unit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited to this. FIG. 2 shows a circuit block diagram of an input / output control unit which is an embodiment of the present invention. The input / output control unit is, for example, an interface for performing data transfer with an external floppy disk drive.

In the figure, the system bus 8 and the processor unit 7 are the same as those shown in FIG. 11
Is a buffer control unit connected to the system bus 8 in the input / output control unit, detects a collision on the system bus, controls timing of signals, and analyzes data and addresses flowing on the system bus. This is the part that sends and receives only data to the system bus.

A DMA controller 12 controls data transfer to a buffering memory 13 for temporarily storing data. Reference numeral 14 is an address latch buffer that holds an address to be accessed when the DMA controller 12 transfers data.

Reference numeral 15 is a set register which is a characteristic part of the present invention, in which a part of the address of the buffering memory to be accessed from the processor unit 7 is set. Reference numeral 16 is a read buffer used when the address set in the set register is read and confirmed from the external processor unit 7 or the like.

Reference numeral 11A denotes an I / O address decoding circuit in the bus control section 11 for decoding an address of an I / O element belonging to the input / output control unit and outputting a chip select signal of the I / O element. It is a department.

Normally, the input / output control unit has some I / O addresses which can be directly accessed from the external processor unit 7 or the like via the system bus 8.
By designating this I / O address and sending an input / output control command signal for data I / O read or I / O write to the system bus 8, the data of the designated I / O address is written. Read and write.

For example, when the address of the set register 15 is externally supplied to the buffer control unit 11, the I / O address decoding unit decodes this address and outputs a signal * BFPR for selecting the set register 15. . * BFPR will be described later.

Next, signals used for accessing the buffering memory 13 in the input / output control unit will be described. From the DMA controller 12, the memory read command signal * MRD (2
1) The memory write command signal * MWT (22) is output.

When an input / output control signal from the outside is received from the buffer controller 11, the I / O read command signal * IOR (24) and I / O corresponding to this control signal are received.
The write command signal * IOW (25) is output. A
EN (23) is a DMAC address enable signal that becomes active when the DMA controller 12 transfers data.

* BFPR (26) is the set register 15
Is a chip select signal for designating an element to be accessed, and this * BFPR is active (“L”).
In the level state), the data, for example, the address of the buffering memory to be accessed is written in the set register at the rising edge of * IOW. * BFWR (2
7) is a window register chip select signal.

The window register not shown here is a fictitious register for directly accessing an address in the buffering memory 13 from the external processor unit 7 or the like, but in the input / output control unit. , I / O addresses for external access are given for the window register.

As will be described later, access to the buffering memory is permitted by sending an input / output control signal of data by designating the address of the window register from the outside.

As shown in FIG. 2, * BFWR (27)
Is input to the enable terminal (EN) of the set register 15, and * BFWR is active (“L” level state)
When it becomes the enable state, the data set in the set register 15 is output to the address buses A4 to A15.

In the circuit block diagram of this embodiment, A0 to A15 of the address buses (A0 to A23) in the input / output control unit are buffering memories 13 and D.
The address of the MA controller 12 is designated, and A16 to A23 designate the address dedicated to the DMA controller 12.

Here, the address lines A4 to A15 are connected to the bus control unit 11 via the address latch buffer 14, and when DMA transfer is performed, the enable terminal EN of the address latch buffer 14 becomes active. , The addresses A4 to A15 are enabled, and the DMA controller 12 transfers data to the buffering memory 13.

On the other hand, when DMA transfer is not performed,
When the enable terminal EN of the set register 15 is activated, the data (D4 to D15) set in the set register 15 is output onto the addresses A4 to A15, together with A0 to A3 directly connected to the bus control unit 11. The address of the buffering memory 13 is designated.

In this way, the addressing of A0 to A3 and the addressing of A4 to A15 relating to the buffering memory 13 is performed separately.
It is considered that the address of the group area is divided into a plurality of group areas, and the addresses (A4 to A15) of the divided group areas are designated by the data set in the set register 15, and the addresses of A0 to A3 It is considered that each storage area in the group area is designated.

That is, in this embodiment, one of 16 recording areas in one group area is designated by A0 to A3, and the data (D
4 to D15) designate addresses (A4 to A15) indicating the entire 16 storage areas in a certain group area.

Next, an embodiment in which the buffering memory 13 is directly accessed from the external processor unit 7 will be described. FIG. 3 is a timing chart of signals in the embodiment of the present invention. Here, an example of reading data stored at an address in the buffering memory from the external processor unit 7 is shown.

In the following description, (100C) h is previously assigned to the set register 15 as an I / O address accessible from the external processor unit 7, and (103C) h is assigned to the window register.
It is assumed that 16 I / O addresses from 0) h to (103F) h are given in advance.

For example, the address (100C) h is designated from the processor unit 7 to specify the data (1238).
If the input / output control signal for writing h is output, the address (1
00C) h, that is, the data (1
238) h is set. Here, the lower 4 bi of the data
The numerical value of t may be arbitrary data instead of "8".

Referring to the time chart of FIG. 3, the bus controller 11 sends an address (100
C) h is fetched, the address (100C) h is output to the internal address buses A0 to A23, and the data (1
238) h is output to the internal data buses D0 to D15, the address (100C) h is further decoded by the I / O address data code section 11A, and the set register 15
Output the chip select signal * BFPR (26).

Further, the bus control unit 11 recognizes that the data write signal is received and outputs the I / O write command signal * IOW (25). At this time, D is set in the set register 15 at the rising timing of * IOW (25).
Of the data indicated by 0 to D15, the upper 12 bits (D4 to D15) of data "(123) h" are set. In order to actually access the buffering memory at the next timing, this setting data “(123)
h ″ is latched as internal addresses A4 to A15.

Next, in order to read the data stored in the address (001234) h of the buffering memory 13, the address (1034) h of the window register is designated from the processor unit 7 and the input / output control for reading the data is performed. When the signal is output, the data stored in the address (001234) h of the buffering memory 13 is read out via the system bus 8.

Referring to the time chart of FIG. 3, the bus controller 11 sends an address (103
4) h is fetched, the address (1034) h is output to the internal address buses A0 to A23, and the I / O address decoding unit 11A causes the address (1034) to be output.
It decodes h and outputs the chip select signal * BFWR (27) of the window register.

At this time, * BFWR (27) is output and at the same time, the set register 15 is enabled and the data "(12
3) h ”is the address line (A of the buffering memory 13
4 to A15).

At the same time, the buffering memory 13
The lower 4-bit value “4” of the address of the window register is output as it is to the address lines A0 to A3 of the buffer register 13 (A0 to A3).
(1234) h is designated as 15).

Further, the bus control unit 11 recognizes that the data read signal is received, outputs the I / O read command signal * IOR (24), and outputs the buffer at the rising timing of * IOR (24). The data output from the ring memory 13 is latched on the internal data bus (D0 to D15).

After that, the bus control unit 11 sets D0 to D15.
By flowing this data latched above onto the system bus 8, the processor unit 7 can read the data stored at the specified address of the buffering memory 13.

The above is the embodiment in which the data stored in the address in the buffering memory 13 is read from the external processor unit 7, but the data may be written in the address in the buffering memory 13 as well. The same method is used.

In the embodiment, the bus controller 11
Although the address space that can be directly accessed from is limited to A0 to A3, if this address space is expanded to reduce the number of address group areas designated by the set register 15 as necessary, the number of times the data is set to the set register 15 is increased. Can be reduced, and the processing speed can be improved.

[0045]

According to the present invention, it becomes possible to directly input / output data from / to the buffering memory from the external processor unit without setting the DMA, so that the processing speed of the processor unit can be improved. It is possible to contribute to improvement and performance improvement of a computer system using the memory access method according to the present invention.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a circuit block diagram according to an embodiment of the present invention.

FIG. 3 is a time chart in the embodiment of the invention.

[Explanation of symbols]

1 Bus Control Unit 2 DMA Controller 3 Buffering Memory 4 Address Latch Buffer 5 Set Register 6 Window Register 7 Processor Unit 8 System Bus 11 Bus Control Unit 11A I / O Address Decoding Unit 12 DMA Controller 13 Buffering Memory 14 Address Latch Buffer 15 Set register 16 Read buffer 21 * MRD (Memory read command signal) 22 * MWT (Memory write command signal) 23 AEN (DMAC address enable signal) 24 * IOR (I / O read command signal) 25 * IOW (I / O Write command signal) 26 * BFPR (chip select signal of set register) 27 * BFWR (chip select signal of window register)

Claims (2)

[Claims] 1. A bus controller (1) connected to a system bus (8), which is a transmission path for address and data, and D
A control unit having a MA controller (2), an address latch buffer (4), and a buffering memory (3) for temporarily storing data is provided with a system bus (8).
Connected to the processor unit (7) by means of which the input / output control signal from the processor unit (7) is received and the data is transferred to the buffering memory (3) in the control unit.
In the memory access method of a control unit for MA transfer, the control unit includes a register for temporarily holding data, temporarily holds the address of the buffering memory (3) sent from the processor unit (7) in the register, and then the processor A control unit which, when receiving an input / output control signal sent from the unit (7), executes input / output of data with respect to the address of the buffering memory (3) temporarily held in the register. Memory access method. 2. A bus control unit (1) connected to a system bus (8) which is an address and data transmission path, and D
A control unit having a MA controller (2), an address latch buffer (4), and a buffering memory (3) for temporarily storing data is provided with a system bus (8).
Connected to the processor unit (7) by means of which the input / output control signal from the processor unit (7) is received and the data is transferred to the buffering memory (3) in the control unit.
In a memory access method of a control unit for MA transfer, a set register (5) for temporarily holding an address to be accessed of a buffering memory (3) and a memory access by receiving the input / output control signal in the control unit. A window register (6) for outputting an enabling signal for enabling to the set register (5) is provided, and an input / output control signal for writing data sent from the processor unit (7) to the set register (5) is received. Sometimes the data is set in the set register (5) as indicating the address of the buffering memory (3) or a part of the address, and then the data sent from the processor unit (7) to the window register (6). When the input / output control signal for writing or reading is received, The address of the buffering memory (3) set in the register (5) or a part of the address is used to specify a memory address to be accessed and to execute input / output of data to / from the buffering memory (3). A method of accessing a memory of a control unit having a feature.