JPH06303255A - Cell switch - Google Patents

Abstract

(57) [Abstract] [Purpose] In a cell switch equipped with two switching devices, cell data loss is minimized and system switching is performed at high speed. [Structure] The first and second switching devices 21 and 22 are provided with first and second buffers 21f and 22f, respectively, and are tested when changing the first switching device from a current switching device to a standby switching device. Cells are loaded into the first and second buffers. When the cell data output from the second buffer matches the test cell, the second data is output until the cell data output from the first buffer matches the test cell.
The reading operation from the buffer is stopped. First and second
Input cell data is only provided to the second switching device after the cell data from the buffer of the first match the test cell. Even if the first cell data does not match the test cell, when the number of cell data stored in the second buffer reaches a predetermined number, the input cell data is loaded only in the second switching device.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a cell exchange.

[0002]

Cell exchanges are used with ATM communications to exchange input cell data for output cell data. This cell exchange includes first and second exchanges, and exchanges input cell data with output cell data in each exchange. Then, one of the first and second exchanging units is used as a working exchanging unit, and the other is used as a spare exchanging unit.
And these 1st and 2nd exchange parts are provided with the 1st and 2nd buffer, respectively. When the first switching unit is used as the working switching unit, a plurality of input cell data are stored in the first buffer as storage cell data.
Each memory cell data is read from the first buffer as output cell data. On the other hand, the second buffer is empty during the operation of the first buffer.

Conventionally, this type of cell switch is further provided with a receiving section and a transmitting section, and the receiving section receives the received cell data and gives the received cell data as input cell data to the working switching section. The transmission unit transmits the output cell data.

When the first exchanging unit operates as the working unit and the second exchanging unit is the spare unit, the first exchanging unit is often used as the spare exchanging unit depending on the situation of the first exchanging unit. . At this time, first, the receiving unit stops receiving the received cell data. In addition, the first exchange section stops the generation of output cell data. As a result, some storage cell data will be held in the first buffer as residual cell data. These residual cell data are transferred to the second buffer via the transfer path. Therefore, the same content as the first buffer is held in the second buffer. After the transfer of the memory cell data from the first buffer to the second buffer is completed, the first exchange unit becomes a spare exchange unit,
The second exchange section is changed to the working exchange section.

[0005]

However, in the conventional cell exchange, it is necessary to transfer the residual cell data held in the first buffer to the second buffer. I cannot change to the exchange department. Further, in the conventional cell exchange, at the time of the above change, the receiving unit stops receiving the received cell data, so that congestion occurs in the received cell data on the reception path, that is, traffic congestion occurs. As a result, some received cell data are discarded on the receiving path. That is, there is a problem that the input cell data is discarded while the residual cell data is transferred from the first exchange section to the second exchange section. in addition,
A large-scale exchange requires a large-scale circuit and a bus with high throughput for residual cell data transfer.

It is an object of the present invention to provide a cell exchange capable of changing a working exchange unit to a spare exchange unit at high speed.

Another object of the present invention is to provide a cell exchange capable of minimizing discard of input cell data.

[0008]

According to the present invention, an ATM
A cell switch used for communication for exchanging input cell data for output cell data, wherein the input cell data is continuously stored as a first buffer data up to a preset number, and the first buffer is stored. A first buffer means for outputting data as first output cell data; and a second buffer data for continuously storing the input cell data as a second buffer data up to a preset number. Second output means for outputting the received cell data as the input cell data, and second receiving means for receiving the received cell data as the input cell data. And a sending means for sending one of the first and second output cell data as the output cell data, and sending the first and second control signals. Control signal generating means for generating the input cell data when the receiving means receives the first control signal, and the receiving means receives the second control signal. At this time, the input cell data is given to the first and second buffer means, and further, in response to the second control signal, the input cell data is tested in the first and second buffer means as the input cell data. A test data supplying means for giving data, and a first detection signal when the first output cell data matches the test data and a second detection signal when the second output cell data matches the test data Detecting means for outputting the detection signal and the second buffer means and outputs the monitoring signal when the number of the second buffer data reaches the predetermined number. And a receiving means and a sending means upon coupling the receiving means and the sending means to the second buffer means when receiving the first and second detection signals, and receiving the monitoring signal. Is provided to the second buffer means, and a control means for coupling the second buffer means to the second buffer means is provided.

[0009]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, the illustrated cell exchange is an AT.
Used in M communication to exchange input cell data with output cell data. The input cell data and the output cell data are provided with fixed-length data blocks, and these cell data have a header in which address signals are arranged and a data area in which data signals are arranged. As is well known, the cell exchange exchanges input cell data with output cell data according to an address signal.

The cell exchange comprises a receiving circuit 11 and a transmitting circuit 1.
2, the reception circuit 11 is connected to the external reception path 13 and continuously receives a plurality of reception cell data. The receiving circuit 11 is further connected to the first and second switching devices 21 and 22 and continuously supplies the received cell data to the first and second switching devices 21 and 22 as input cell data. The first exchange device 21 exchanges (converts) each input cell data into first output cell data, and sends the first output cell data to the transmission circuit 12 as described later. Similarly, the second switching device 22 exchanges (converts) each input cell data into the second output cell data and sends the second output cell data to the transmission circuit 12 as described later. In the transmission circuit 12, one of the first and second output cell data is selectively transmitted as output cell data on the external transmission path as described later. In addition, the cell exchange is the main control circuit 30.
And first and second control circuits 31 and 32.

The first exchange device 21 includes a first test cell generation circuit 21a, a first cell exchange circuit 21b, a first detection circuit 21c, and a first monitoring circuit 21d.
The first cell exchange circuit 21b is the first exchange unit 21e.
And a first buffer 21f. The first exchange unit 21e exchanges each input cell data with the first exchange cell data by the time division method and stores the first exchange cell data in the first buffer 21f as the first storage cell data. Each first memory cell data is read out from the first buffer 21f as first output cell data at a predetermined time interval.

The first buffer 21f has a predetermined capacity. That is, the first storage cell data can be stored in the first buffer 21f up to a predetermined number. The first buffer 21f is, for example, a first-in first-out memory. The first monitoring circuit 21d monitors the number of the first memory cell data stored in the first buffer 21f, and when the number of the first memory cell data reaches a predetermined number, the first monitor circuit 21d performs the first monitoring. The circuit 21d outputs the first supervisory signal.

Similarly, the second switching device 22 includes a second test cell generating circuit 22a and a second cell switching circuit 21.
b, the second detection circuit 22c, and the second monitoring circuit 22d
Is equipped with. The second cell exchanging circuit 22b includes a second exchanging unit 22e and a second buffer 22f, and similarly to the first exchanging unit 21e, the second exchanging unit 22e uses the time division method for each input cell. The data is exchanged for the second exchange cell data and the second exchange cell data is used as the second storage cell data in the second buffer 22.
Store in f. Each second memory cell data is read from the second buffer 22f as second output cell data at a predetermined time interval.

The second buffer 22f has a predetermined capacity. In other words, the second storage cell data can be stored in the second buffer 22f up to a predetermined number. The second buffer 22f is, for example, a first-in first-out memory. The second monitoring circuit 22d monitors the number of the second memory cell data stored in the second buffer 22f, and when the number of the second memory cell data reaches a predetermined number, the second monitoring circuit 22d performs the second monitoring. The circuit 22d outputs the second supervisory signal.

In the exchange operation, one of the first and second exchanges 21 and 22 is used as the active exchange.
The other of the first and second exchanges 21 and 22 is used as a spare exchange. In the illustrated example, the first switching device 21 is used as the working switching device and the second switching device 2 is used.
2 is used as a preliminary exchange device.

The main control circuit 30 sends an operation mode signal to the first and second control circuits 31 and 32 in response to an active signal given from an external device (not shown) via the control path 33. This operation mode signal determines either the working state or the standby state in the first and second switching devices 21 and 22. The active signal sets the first switching device 21 to the working switching device as will be described later.

First and second responsive to the operating mode signal
The control circuits 31 and 32 of 1 provide a first reception control signal and a first transmission control signal to the reception circuit 11 and the transmission circuit 12, respectively. When the first reception control signal is given, the receiving circuit 11 selects the first switching device 21 and continuously supplies the received cell data as the input cell data to the first switching device 21. In response to the first transmission control signal, the transmission circuit 12 selects the first switching device 22 to receive the first output cell data.

The first reception control signal and the second reception control signal are sent to the first and second test cell generation circuits 21a and 22a and the first and second detection circuits 21c and 22c as shown in FIG. Is also given. When receiving the first reception control signal, the first and second test cell generation circuits 21a and 2a
2a passes the received cell data respectively. Similarly, in response to the first transmission control signal, the first and second
The detection circuits 21c and 22c of 1) pass the received cell data. In the illustrated example, the first cell exchange circuit 21b is located between the first test cell generation circuit 21a and the first detection circuit 21c, and is input from the reception circuit 11 via the first test cell generation circuit 21a. Receive cell data,
This input cell data is converted into first output cell data. The first output cell data is sent to the transmission circuit 12 via the first detection circuit 21c, and is sent to the external transmission path 23 as output cell data.

With reference to FIG. 1, a change operation in which the first exchanging device 21 is used as a spare exchanging device will be described.

At the time of the change operation, the main control circuit 30 is supplied with a preparation command signal from the control path 33. When receiving the preparation command signal, the main control circuit 30 controls the first and second control circuits 31 and 32 to cause the first and second control circuits 31 and 32 to receive the second reception control signal and the second reception control signal, respectively. Send a transmission control signal. The second reception control signal is supplied from the first control circuit 31 to the reception circuit 11 and the first and second test cell generation circuits 21a and 22a,
On the other hand, the second transmission control signal is transmitted from the second control circuit 32 to the transmission circuit 12 and the first and second detection circuits 21c and 22.
is supplied to c.

In response to the second reception control signal, the first and second test cell generation circuits 21a and 22a generate test cells, and the test cells are respectively converted into first and second cell switching circuits 21b and 21b. 22b. Each test cell is CCITT I.D. 361 is provided, and a test cell area in which a test identification code having a predetermined pattern is arranged is further provided. After generating the test cell, the receiving circuit 11 supplies the received cell data as the input cell data to both the first and second switching devices 21 and 22 in response to the second reception control signal.

Referring to FIGS. 1 and 2, here, FIG.
As shown in (A), it is assumed that the memory cell data C1 to C4 have already been loaded into the first buffer 21f as the first memory cell data, and the second buffer 22f is empty. In this situation, the test cell TC is followed by the exchanged cell data C5 to C8 supplied by the first and second exchange units 21e and 22e. That is, the exchanged cell data C5 to C8 are commonly supplied to the first and second buffers 21f and 22f, which are equal to the same first and second exchanged cell data.

As shown in FIG. 2B, the test cell TC operates in the first and second buffers 21 in the first time interval.
It is stored in f and 22f as a storage test cell TC.
In this case, the test cell TC is loaded as the storage test cell in the final stage of the first buffer 21f, and the same test cell TC is loaded in the front stage of the second buffer 22f. In the first time interval, the memory cell data C1 is read from the first buffer 21f as the first output cell data by the first-in first-out method. On the other hand, cell data is not read from the second buffer 22f in the first time interval.

As described above, during the change operation, the first
The second transmission control signal is given to the detection circuit 21c of
As a result, the first detection circuit 21c detects whether or not the first output cell data matches the test cell. First
If the output cell data of 1) includes the test cell identification code, the first detection circuit 21c sends out the first detection signal. In this case, since the first output cell data does not have the test cell identification code, the first detection circuit 21c does not send the first detection signal. Then, the first detection circuit 2
1c passes the first output cell data.

As shown in FIG. 2C, the cell data C5 is stored as the storage cell data C5 in the final stage of the first buffer and the front stage of the second buffer in the second time interval. At the same time, in the second time interval, the memory cell data C2 is read from the first buffer 21f as the first output cell data and given to the first detection circuit 21c. At this time, the memory test cell TC is read out from the second buffer 22f as the second output cell data and given to the second detection circuit 22c.

As described above, during the change operation, the second
Is transmitted to the second detection circuit 22c, whereby the second detection circuit detects whether or not the second output cell data matches the test cell. When the second output cell data has the test cell identification code, the second detection circuit 22c sends out the second detection signal. Here, since the second output cell data has the test cell identification code, the second detection signal is sent from the second detection circuit 22c. On the other hand, as shown in FIG.
Since the output cell data of 1 does not include the test cell identification code, the first detection circuit 21c does not send the first detection signal.

The second detection signal is given from the second detection circuit 22c to the second control circuit 32, whereby the second detection signal is supplied.
The control circuit 32 controls the second exchange circuit 22b to stop the read operation of the second buffer 22f.

As shown in FIG. 2D, at the third time interval, the cell data C6 is loaded into the first and second buffers 21f and 22f as the storage cell data C6. Instead, the memory cell data C3 is read as the first output cell data from the first buffer 21f and given to the first detection circuit 21c. On the other hand, as described above, the read operation is stopped in the second buffer 22f, so that the cell data is not read from the second buffer 22f.

As shown in FIG. 2E, the cell data C7 is stored in the first and second buffers 2 in the fourth time interval.
The memory cell data C7 is loaded into 1f and 22f. At the same time, in the fourth time interval, the memory cell data C4 is used as the first output cell data in the first buffer 21.
It is read from f and given to the first detection circuit 21c.

As shown in FIG. 2F, the cell data C8 is stored in the first and second buffers 2 in the fifth time interval.
The memory cell data C8 is loaded into 1f and 22f. At the fifth time interval, the memory test cell TC is read out from the first buffer 21f as the first output cell data and given to the first detection circuit 21c. As a result, the storage cell data C5 to C8 are loaded into the first and second buffers 21f and 22f, respectively. That is, the second buffer 22f has the same contents as the first buffer 21f.

When the test cell TC is given to the first detection circuit 21c as the first output cell data, as described above, the first detection circuit 21c outputs the first detection signal to the second detection signal.
To the control circuit 32. As a result, the second control circuit 32 controls the first exchange circuit 21b to stop the read operation of the first buffer 21f.

After receiving the first and second detection signals, the second
The control circuit 32 of 1 supplies a changeable signal to the main control circuit 30. Upon receiving the change enable signal, the main control circuit 30 gives a change operation signal to the first and second control circuits 31 and 32. In response to the change operation signal, the first control circuit 31 controls the receiving circuit 11 to distribute the receiving cell data to the receiving circuit 11 only to the second switching device 22. On the other hand, the second control circuit 32 controls the transmission circuit 12 to control the transmission circuit 1 in response to the change operation signal.
2 to select the second output cell data sent from the second switching device 22. Further, the second control circuit 22 has a first
Also, the read operation is permitted to the second exchange circuits 21b and 22b. That is, the first and second exchange circuits 21b and 22
The read operation of b is controlled by the second control circuit 32.

With reference to FIGS. 1 and 3, a change operation when a failure occurs in the first switching device 21 operating as the active switching device will be described. Here, FIG.
As shown in (A), it is assumed that the memory cell data C1 to C4 are loaded as the first memory cell data in the first buffer 21f and the second buffer 22f is empty. Then, it is assumed that the test cell TC is followed by the exchange cell data C5 to C8 given from the first and second exchange units 21e and 22e, respectively.
In this situation, assume that a failure occurs in the first switching device 21 and the supplied cell data cannot be written into the first buffer 21f (reading is possible). As a result, in the first time interval, as shown in FIG. 3B, the test cell TC is written as the memory test cell TC only in the second buffer 22f. At this time, the test cell TC is loaded as a memory test cell in the frontmost stage of the second buffer 22F. In the first time interval, the memory cell data C1 is read from the first buffer 21f as the first output cell data by the first-in first-out operation and is given to the first detection circuit 21c. On the other hand, cell data is not read from the second buffer 22f in the first time interval.

Since the first output cell data does not have the test cell identification code, the first detection circuit 21c is the first detection circuit 21c.
The first output cell data is passed without sending the detection signal of.

As shown in FIG. 3C, the cell data C5 is stored as the storage cell data C5 at the frontmost stage of the second buffer 22f in the second time interval. at the same time,
In the second time interval, the memory cell data C2 is read from the first buffer 21f as the first output cell data and sent to the first detection circuit 21c. At this time, the memory test cell TC is read out from the second buffer 22f as the second output cell data and given to the second detection circuit 22c.

When the second output cell data has the test cell identification code, the second detection circuit 22c sends out the second detection signal. On the other hand, as shown in FIG. 3C, since the first output cell data does not have the same identification code as the test cell, the first detection circuit 21c does not output the first detection signal. .

Since the first detection circuit 21c is connected to the transmission circuit 12, the transmission circuit 12 sends the cell data C1 as output cell data to the external transmission path 23 at the second time interval.

The second detection signal is sent from the second detection circuit 22c to the second control circuit 32, which causes the second control circuit 32 to control the second exchange circuit 22b.
Then, the reading operation of the buffer 22f is stopped.

As shown in FIG. 3D, the cell data C6 is loaded into the second buffer 22f as the storage cell data C6 in the third time interval. The memory cell data C3 is read out as first output cell data from the first buffer 21f and given to the first detection circuit 21c. On the other hand, since the read operation of the second buffer 22f is stopped, cell data is not read. In the third time interval, the transmission circuit 12 sends the cell data C3 as output cell data to the external sending path 23.

As shown in FIG. 3 (E), the cell data C7 is loaded into the second buffer 22f as the storage cell data C7 at the fourth time interval. At the same time, in the fourth time interval, the memory cell data C4 is read out from the first buffer 21f as the first output cell data and given to the first detection circuit 21c. Further, at the fourth time interval, the cell data C3 is sent from the sending circuit 12 to the external sending path 23.

As shown in FIG. 3F, the cell data C8 is loaded into the second buffer 22f as the storage cell data C8 at the fifth time interval. On the other hand, since the first buffer 21f is empty, cell data is not read from the first buffer 21f during the fifth time interval. Also, at the fifth time interval, the cell data C4 is transmitted to the transmission circuit 12
From the external transmission path 23.

As described above, the second monitor circuit 22d monitors the number of memory cell data stored in the second buffer 22f. When the number of memory cell data reaches a predetermined number, the second monitoring circuit 22d gives a second monitoring signal to the main control circuit 30. In the example shown,
The predetermined number is 4.

In response to the second monitor signal, the main control circuit 30 sends a change operation signal to the first and second control circuits 3.
1 and 32. When receiving the change operation signal,
The first control circuit 31 controls the receiving circuit 31 to cause the receiving circuit 11 to distribute the received cell block only to the second switching device 22. On the other hand, in response to the change operation signal, the second control circuit 32 controls the transmission circuit 12 to control it.
To select the second output cell data sent from the second switching device 22. Furthermore, in the second control circuit 32, the first
And the read operation is permitted to the second exchange circuits 21b and 22B. As a result, as shown in FIG. 5G, the memory cell data C5 is read from the second buffer 22f as the second output cell data.

In FIG. 1, the first and second test cell generation circuits 21a and 22a are collectively used as a test cell generation unit. In addition, the first and second detection circuits 21
c and 22c are also collectively used as a detection unit for detecting test cells. In addition, the main control circuit 30 and the first and second control circuits 31 and 32 are collectively used as a control signal generation unit or a control unit that sends out the various signals described above.

In the above-mentioned embodiment, the operation of changing the first exchanging device to the spare exchanging device when the first exchanging device is the active exchanging device has been described, but the second exchanging device is the active exchanging device. When operating as a device and then changing the second switching device to a spare switching device, the same operation as described above is performed.

When the second switching device is changed from the current switching device to the spare switching device, if the write operation cannot be performed in the second buffer, the first monitoring signal sent from the first monitoring device. In response to this, the main control circuit sends a change operation signal to the first and second control circuits.

[0048]

As described above, in the present invention, the system switching control is performed by monitoring the test cells and the staying cells in the buffer, so that the cell data loss during system switching is minimized in the normal state. Not only can it be limited, but high-speed system switching can also be performed. Furthermore, there is an effect that the loss of cell data in the event of a failure can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a cell exchange according to the present invention.

FIG. 2 is a diagram for explaining one operation of the cell exchange shown in FIG.

FIG. 3 is a diagram for explaining another operation of the cell exchange shown in FIG.

[Explanation of symbols]

 11 receiving circuit 12 transmitting circuit 21 first switching device 22 second switching device 30 main control circuit 31 first control circuit 32 second control circuit

Claims (3)

[Claims] 1. A cell exchange for exchanging input cell data for output cell data used in ATM communication, comprising:
First buffer means for continuously storing the input cell data as a first buffer data up to a preset number and outputting the first buffer data as first output cell data; and the input cell data. As a second buffer data continuously stored up to a preset number and outputting the second buffer data as second output cell data, and the first buffer means for receiving the received cell data. And receiving means for continuously applying the received cell data as the input cell data to the second buffer means, and sending for sending one of the first and second output cell data as the output cell data And a control signal generating means for generating first and second control signals, wherein the receiving means receives the first control signal. Applying the input cell data to the first buffer means, the receiving means applying the input cell data to the first and second buffer means when receiving the second control signal, and Test data supply means for supplying test data as the input cell data to the first and second buffer means in response to the second control signal, and the first output cell data match the test data. At this time, the first detection signal is output and a second detection signal is output when the second output cell data matches the test data, and the second buffer means is monitored to detect the second output signal. Monitoring means for outputting a monitoring signal when the number of the buffer data in the buffer reaches the predetermined number, and the receiving means and the sending means when receiving the first and second detection signals. Cell switch, characterized in that a control means for coupling said receiving means and said delivery means when receiving said monitoring signal as well as coupled to said second buffer means to said second buffer means. 2. The cell exchange according to claim 1, wherein the received cell data has a predetermined fixed-length data block format, and the data block format includes a header in which an address signal is arranged and a data signal. And a test area in which a test identification code having a predetermined pattern is arranged, and the detection means includes the first and second output cell data. A cell exchange, wherein the first and second detection signals are output when the test identification code is detected in the cell exchange. 3. The cell exchange according to claim 2, wherein after the test identification code is detected in the first output cell data, the test identification code is detected in the second output cell data. A cell switching system characterized in that the first buffer means is controlled to stop reading of the first output cell data from the first buffer.