JPH06302615A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent grain boundaries which might cause the deterioration and variations of device characteristics from being formed within an active region of a semiconductor device. CONSTITUTION:A semiconductor device is constructed such that a polycrystalline silicon layer 6 is first formed and a portion which becomes an active region of the device and one of one sides are formed as an amorphous silicon region 3 by implanting ions 27, and further upon crystallizing the amorphous region a starting point of crystal growth is limited to one end of the active region (just under one end of a gate electrode 4). Accordingly, upon crystallization the crystal growth is started from the one end of the active region so that any grain boundary is prevented from being formed within the active region by setting the size of the active region to be smaller than a maximum growth distance of the crystal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a polycrystalline thin film transistor.

[0002]

2. Description of the Related Art As a conventional method of manufacturing a semiconductor device,
There are the following things. First, the first conventional example is "JAPA
NESE JOURNAL OF APPLIED PHYSICS, Vol.25, No.2, pp.
L121-L123, 1986 ”. Figure 6
It is sectional drawing which shows the manufacturing process of the said prior art example. In FIG. 6, first, as shown in (a), amorphous silicon is formed on a silicon substrate 1 having an insulating film 2.
Form layer 3. As a method of forming the amorphous silicon layer 3, an LPCVD method using SiH ₄ or Si ₂ H ₆ is used. Next, the gate oxide film 5 is formed on the amorphous silicon layer 3. Next, the gate electrode 4 is formed on the gate oxide film 5.
And an insulating film 9 is formed on the surface. next,
As shown in (b), the amorphous silicon layer 3 is heat treated (6
By performing low temperature annealing at about 00 ° C.), solid phase growth is performed to form the polycrystalline silicon layer 6. Next, as shown in (c), N-type (or P-type) impurities are introduced by an ion implantation method using the gate electrode 4 as a mask. The ion-implanted region is the source 23 and the drain 25.
Becomes Next, the interlayer insulating film 7 is formed. Next, (d)
As shown in FIG. 3, after the interlayer insulating film 7 on the source 23 and the drain 25 and the gate oxide film 5 are etched, the source contact electrode 21 and the drain contact electrode 22 are formed. Next, the protective film 8 is formed on the entire surface. A polycrystalline silicon transistor manufactured through the above process can be formed on an insulating film and is expected to be applied to a three-dimensional device or the like. However, unlike a single crystal transistor, a polycrystalline silicon transistor is
Crystal grain boundaries exist in the element formation portion. Since carriers are captured at the crystal grain boundaries, the capture causes the grain boundaries to be positively or negatively charged to form a barrier potential that hinders carrier conduction. Therefore, the carrier mobility in the polycrystalline transistor is lower than that in the single crystal, and it depends on the crystal grain size in the polycrystalline. Therefore, in the case of a device having a MOS structure as shown in FIG.
The number of crystal grain boundaries in the channel region 24 affects the characteristics of the transistor. Further, as a second conventional example, there is one described in "Solid-state element material conference abstract pp.1160, 1990". This is because a material with a high crystal nucleus generation rate (eg, silicon nitride film) is formed in advance at a predetermined position on the insulating film, and then an amorphous silicon layer is formed on the entire surface and polycrystallized by heat treatment. Then, only the element region is solid-phase grown into a polycrystal having a large grain size. In such a manufacturing method, the polycrystalline silicon layer formed on the material having a high crystal nucleus generation rate has a large grain size and the other regions are small. There is a possibility that the particle size can be controlled by using this method.

[0003]

However, the conventional polycrystalline thin film transistor as described above has the following problems. First, in the first conventional example, in the heat treatment for polycrystallizing the amorphous layer, the generation of crystal nuclei occurs irregularly, so that the grain size in the polycrystal layer cannot be controlled and the crystal grain boundaries are not controlled. Variations in the number of As a result, the element characteristics greatly vary, so it is not possible to design an element having the desired characteristics.Therefore, it is necessary to secure a large circuit characteristic margin because an optimal circuit design cannot be made, and there is a problem that a highly functional circuit cannot be assembled. In addition, there is a problem that the yield decreases and the manufacturing cost increases because the characteristics of the element vary. Further, in the second conventional example, when a material having a fast crystal nucleus is formed to control the grain size,
Although alignment is required at the time of formation, in the case of a crystal growth distance of about 1 μm or less, which is well known in the ordinary solid-phase growth method, the element region and the crystal grain boundary may be separated due to an error in mask alignment accuracy. There is a problem that it is difficult to strictly control

The present invention has been made in order to solve the problems of the prior art as described above, and prevents the formation of crystal grain boundaries that cause deterioration and dispersion of device characteristics in the active region of the device. It is an object to provide a method for manufacturing a semiconductor device.

[0005]

In order to achieve the above object, the present invention is constructed as described in the claims. First, the invention according to claim 1 is MO
A method of manufacturing an S-type transistor, comprising a step of amorphizing a portion of a portion of the polycrystalline semiconductor thin film to be an element active region to form a first amorphized region, and the first amorphous state. Forming a gate electrode so as to cover a boundary portion between the polycrystallized region and the polycrystallized region; forming a second amorphized region by amorphizing only just under the gate electrode; And a step of crystallizing the second amorphized region. The invention according to claim 2 is a method for manufacturing a bipolar transistor, wherein in the method according to claim 1, a mask is used instead of the gate electrode, and an active region is formed in a portion below the mask. It is configured as follows.

[0006]

As described above, in the present invention, the polycrystalline layer is first formed, and the portion to be the active region of the element and one side thereof are ion-implanted to form the amorphous layer. When crystallized, the starting point of crystal growth is limited to one end of the active region. Therefore, when crystallizing, crystal growth occurs from one end of the above-mentioned active region. Therefore, by setting the size of the active region smaller than the maximum crystal growth possible distance, the crystal grows in the active region. It is possible to prevent the formation of grain boundaries. Therefore, it is possible to manufacture a high-performance transistor having a higher carrier mobility as compared with the conventional manufacturing method, and it is possible to stably manufacture a constant characteristic with little variation. Also,
Accurate control is possible because there is no need for mask alignment and self alignment is performed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
1 to 3 are cross-sectional views showing a first embodiment of the manufacturing method of the present invention, showing a method of manufacturing a MOS transistor. 1 to 3 show a series of manufacturing processes,
1C to FIG. 2D, and FIG. 2F to FIG. 3G. First, as shown in FIG. 1A, a polycrystalline silicon layer 6 is formed on the insulating film 2 formed on the silicon substrate 1. Next, the gate oxide film 5 is formed on the polycrystalline silicon layer 6. Then, for example, LP
The gate electrode 4 is formed by using polysilicon by CVD, and the mask material 12 is formed on the surface thereof. Next, (b)
As shown in, the ion implantation of Si ions 27 (first amorphization) is performed. Ions are implanted into the mask material 12 in the region where the mask material 12 is present at the upper portion, while ions are implanted into the polycrystalline silicon layer 6 in the region where the mask material 12 is not present at the upper portion. Reference numeral 26 indicates a region where ions are implanted. Here, the implantation energy is set so that the projected range is in the polycrystalline silicon layer 6 in the region where the mask material 12 is not present. Next, as shown in (c), the portion of the polycrystalline silicon layer 6 into which the Si ions are implanted becomes the amorphous silicon region 3. Next, as shown in FIG. 2D, the mask material 12 is removed and the gate electrode 4 is etched. At this time, etching is performed so that the edge of the amorphous silicon region 3 (the boundary between the non-ion-implanted portion of the polycrystalline silicon layer 6 and the amorphous silicon region 3) is located below the gate electrode 4. . Then again Si
Ion implantation of ions 27 (second amorphization) is performed. The implantation energy at this time is set so that the projected range is in the polycrystalline silicon layer 6 in the region where the gate electrode 4 is present. In addition, 26 has shown the area | region where the ion was injected. Next, as shown in (e), as a result of the above ion implantation, the polycrystalline silicon in the region where the gate electrode 4 is located above becomes amorphous silicon, and as a result, the amorphous silicon region 3 becomes a polycrystalline silicon layer. 6 and extends immediately below one end of the gate electrode 4 to serve as a boundary between amorphous and polycrystalline. Next, as shown in (f), the amorphous silicon region 3 is subjected to heat treatment (low temperature annealing at about 600 ° C.) to cause solid phase growth. In this case, crystal growth occurs from the boundary surface between the amorphous silicon region 3 and the polycrystalline silicon layer 6. Therefore, by setting the dimension of the active region under the gate electrode 4 to be smaller than the maximum crystal growth possible distance, it is possible to prevent the crystal grain boundary 29 from being formed in the active region under the gate electrode 4. . In addition, 16 indicates a portion in which crystal grains are continuously formed. Next, as shown in (g), the insulating film 9 is formed on the surface of the gate electrode 4. next,
N-type (or P-type) impurities are introduced by ion implantation using the gate electrode 4 as a mask. The ion-implanted region becomes the source 23 and the drain 25. A channel region 24 is formed between the source 23 and the drain 25.
After that, the interlayer insulating film 7 is formed on the entire surface. Then (h)
As shown in FIG. 5, after the interlayer insulating film 7 and the oxide film 5 on the source 23 and the drain 25 are etched, the source contact electrode 21 and the drain contact electrode 22 are formed. Finally, the protective film 8 is formed on the entire surface. In the element formed by the above method, the crystal grain boundary 29 of the polycrystalline silicon layer 6 is formed outside the active region, that is, outside the channel region below the gate electrode 4. Therefore, in such a MOS type transistor, since there is no crystal grain boundary in the channel region 24 through which a current flows, good transistor characteristics with a low on-current can be obtained. In addition, it is possible to stably manufacture with constant characteristics with little variation. In this example, since the polycrystalline silicon by the LPCVD method was used as the gate electrode, the first amorphization (ion implantation in FIG. 1b) was performed after the gate electrode was formed. And as the gate electrode,
When a film formed at low temperature such as a photo-CVD method is used, amorphous silicon is not polycrystallized due to the temperature at the time of film formation. You can change the order. As a result, it is not necessary to perform ion implantation for amorphization through the gate insulating film, so that the device characteristics (gate breakdown voltage) can be improved.

Next, FIGS. 4 to 5 are sectional views showing a manufacturing method of a second embodiment of the present invention, showing a manufacturing method of a bipolar transistor. 4 and 5 show a series of manufacturing steps, which continue from (d) in FIG. 4 to (e) in FIG. First, as shown in FIG. 4A, the polycrystalline silicon layer 6 is formed on the insulating film 2 formed on the silicon substrate 1. At this time, the polycrystalline silicon layer 6 is N-type doped. Next, the oxide film 5 is formed on the surface.
Next, the first mask material 12 is formed. Next, implantation of Si ions 27 (first amorphization) is performed. At this time, in the region where the first mask material 12 is present in the upper portion, ions are implanted into the first mask material 12, and
Ions are implanted into the polycrystalline silicon layer 6 in the region where 2 is absent. The ion-implanted portion of the polycrystalline silicon layer 6 becomes the amorphous silicon region 3. In the above-mentioned ion implantation, the projection energy of the implantation energy is the first
It is set so as to be in the polycrystalline silicon layer 6 in the region where the mask material 12 is absent. Next, as shown in (b), the first mask material 12 is removed. Next, after the second mask material 13 is formed, the edge of the amorphous silicon region 3 (the boundary between the non-implanted portion of the polycrystalline silicon layer 6 and the amorphous silicon region 3) is removed. , The second mask material 1
The second mask material 13 is photo-etched so as to come to the lower part of 3. Next, the Si ions 27 are implanted again (second amorphization). At this time, the projected range of the implantation energy is set so as to be in the polycrystalline silicon layer 6 in the region where the second mask material 13 is present. In addition, 26 has shown the area | region where the ion was injected. Next, as shown in (c), as a result of the above-mentioned ion implantation, the polycrystalline silicon in the region where the second mask material 13 is located above becomes amorphous silicon, and as a result, the amorphous silicon region 3 becomes large. It expands to the side of the crystalline silicon layer 6 and the region immediately below one end of the second mask material 13 becomes the boundary between the amorphous and the polycrystalline. Next, as shown in (d), the amorphous silicon region 3 is solid-phase grown by heat treatment (low temperature annealing at about 600 ° C.). In this case, crystal growth occurs from the boundary surface between the amorphous silicon region 3 and the polycrystalline silicon layer 6. Therefore, by setting the dimension of the second mask material 13 to be smaller than the maximum crystal growth possible distance, it is possible to prevent the crystal grain boundaries 29 from being formed in the region below the second mask material 13. I can. In addition, 16 indicates a portion in which crystal grains are continuously formed. Next, as shown in FIG. 5E, the third mask 38 is formed only on one half surface of the element with the second mask material 13 as the center. Next, P-type impurities are introduced into the polycrystalline silicon layer 6 to form the base 34. As a method of introducing impurities in this case, there is a method of removing the glass on the surface after depositing BSG (or PSG) and diffusing it by heat treatment. When this method is used, the impurities also diffuse in the lateral direction, and the base 34 is formed just below the second mask material 13. After that, the mask 38 is removed. next,
As shown in (f), N-type impurities are introduced by the ion implantation method. The ion-implanted region becomes the emitter 33 and the collector 36. A base 34 and a collector depletion region 35 are formed between the emitter 33 and the collector 36. After that, the interlayer insulating film 7 is formed on the entire surface.
Next, as shown in (g), after etching the interlayer insulating film 7 and the oxide film 5 on the emitter 33 and the collector 36, the emitter contact electrode 31 and the collector contact electrode 32 are formed. Finally, the protective film 8 on the entire surface
To form. In the element formed by the manufacturing method as described above, the crystal grain boundaries 29 of the polycrystalline silicon layer 6 are
Exists in the collector region 36, and the crystal grain boundary 29 does not exist in the base region 34 and the collector depletion region 35. Therefore, in the NPN bipolar transistor thus manufactured, since there is no crystal grain boundary in the base region 34 through which the current flows, the leak current is small, and good transistor characteristics with a large current amplification factor can be obtained. In addition, it is possible to stably manufacture with constant characteristics with little variation. Although the NPN bipolar transistor has been described in the present embodiment, the PNP is reversed in polarity.
It is of course possible to form a bipolar transistor. Further, in the above description, the case of using Si ions for ion implantation for amorphization has been described, but any one of Si, Ar, B, Ge, P and As, or You may use the combination of them.

[0009]

As described above, according to the present invention, the polycrystalline layer is first formed, and the portion which becomes the active region of the element and one side thereof are made into the amorphous layer by ion implantation, and the amorphous layer is formed. Since the starting point of crystal growth is limited to one end of the active region when crystallizing the material, a polycrystalline silicon layer having no crystal grain boundary in the active region of the device can be obtained. Therefore, it is possible to manufacture a high-performance transistor having a higher carrier mobility as compared with the conventional manufacturing method, and it is possible to stably manufacture a constant characteristic with little variation. Further, it is possible to obtain an effect that accurate control is possible because the mask alignment is not necessary and the self-alignment is performed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a part of a manufacturing process of a first embodiment of the present invention.

FIG. 2 is a sectional view showing another part of the manufacturing process of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing another part of the manufacturing process of the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the second embodiment of the present invention.

FIG. 5 is a sectional view showing another part of the manufacturing process of the second embodiment of the present invention.

FIG. 6 is a sectional view of an example of a conventional manufacturing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 23 ... Source 2 ... Insulating film 24 ... Channel region 3 ... Amorphous silicon region 25 ... Drain 4 ... Gate electrode 26 ... Ion-implanted region 5 ... Gate oxide film 27 ... Si ion 6 ... Polycrystal Silicon layer 29 ... Crystal grain boundary 7 ... Interlayer insulating film 31 ... Emitter contact electrode 8 ... Protective film 32 ... Collector contact electrode 9 ... Insulating film 33 ... Emitter 12, 13 ... Mask material 34 ... Base 16 ... Crystal grains are continuous Formed portion 35 ... Collector depletion region 21 ... Source contact electrode 36 ... Collector 22 ... Drain contact electrode 38 ... Mask

Claims (3)

[Claims] 1. In a semiconductor device having a polycrystalline semiconductor thin film as an element region, a step of forming the polycrystalline semiconductor thin film, and a part of a portion of the polycrystalline semiconductor thin film to be an element active region is made amorphous. A step of forming a first amorphized region, a step of forming a gate electrode so as to cover a boundary portion between the first amorphized region and the polycrystalline region, and only under the gate electrode. And a step of crystallizing the first and second amorphized regions to form a second amorphized region. Production method. 2. In a semiconductor device having a polycrystalline semiconductor thin film as an element region, a step of forming the polycrystalline semiconductor thin film, and a part of the polycrystalline semiconductor thin film which becomes an element active region is made amorphous. And forming a first amorphized region, and forming a mask material so as to cover a boundary portion between the first amorphized region and the polycrystalline region and an element active region of the semiconductor device. A step of amorphizing only just under the mask material to form a second amorphized region, and a step of crystallizing the first and second amorphized regions. A method for manufacturing a semiconductor device, comprising: 3. The step of amorphizing is a method of amorphizing by ion implantation, wherein S is used as the ions.
3. The method of manufacturing a semiconductor device according to claim 1, wherein any one of i, Ar, B, Ge, P and As, or a combination thereof is used.