JPH06296019A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Objective] Regarding protection of a gate insulating film from high voltage application such as electrostatic stress in an integrated circuit using a MIS type semiconductor, without increasing junction capacitance or junction leakage amount,
Further, a structure is provided in which a high voltage due to static electricity or the like is lower than that which destroys the gate insulating film, and the charge due to the high voltage is released at an arbitrary voltage to protect the gate insulating film. A MIS type semiconductor device in which a second conductivity type well is formed in a first conductivity type semiconductor substrate, and a first conductivity type drain and a source are further formed in the well and on the substrate surface. The structure in which the depth of the well under the drain is controlled to be shallower than the depth of the well in the region other than the drain. In addition, the central bottom of the drain protrudes into the well, and the length of the protrusion is controlled. In addition, in the lower part of the central part of the drain bottom, a well region controlled to have a low concentration reaches the substrate from the drain bottom or occupies most of the region in the depth direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, in integrated circuits using MIS type semiconductors, the following methods have been adopted to protect the gate insulating film from high voltage application such as electrostatic stress.

Basically, by providing a circuit having a lower withstand voltage than the gate film in parallel with the gate insulating film, the latter circuit breaks first to release charges when applying electrostatic stress or the like to protect the gate insulating film. I am trying to As a specific example, a method using a reverse break of a diode or an off break of a transistor itself in a circuit is widely used. As a method of controlling the break breakdown voltage, there is a method of changing the impurity concentration of a low concentration region of the two types of conductivity type regions forming the junction of the diode. Normally, the impurity concentration of the substrate and the inversion prevention diffusion layer is changed.
Therefore, a semiconductor integrated circuit having a gate insulating film thickness of about 20 nm (the maximum electric field strength applied to the gate insulating film is 8 M
Since it is V / cm, it is converted to protection diode withstand voltage of 15V.
It has to be less than or equal to)) was an effective means for electrostatic stress by this method.

[0004]

On the other hand, it is necessary to make the gate insulating film thinner because of the demand for higher integration, higher density and higher speed of the semiconductor integrated circuit. As a result, the resistance of the integrated circuit to static electricity is reduced. Therefore, it is necessary to lower the breakdown voltage of the break of the protection circuit for electrostatic protection. However, if it is attempted to lower the breakdown voltage by the conventional method, the adverse effect will occur. When the impurity concentration of the substrate and the inversion prevention layer is increased by the conventional method in accordance with the demand for lowering the break breakdown voltage, the junction capacitance increases, which hinders the speedup of the device. At the same time, not only does the current leaking through the junction increase, which leads to an increase in power consumption, but there is concern that heat generation may affect the element. Therefore, when manufacturing an element in which the film thickness of the gate insulating film is less than 20 nm, there is a contradictory relationship between lowering the break breakdown voltage and reducing the junction capacitance and leakage current, and it is practically impossible to manufacture. It will be possible. Therefore,
The present invention solves the above problems, and an object of the present invention is to increase the junction capacitance and the junction leakage amount without increasing the high voltage due to static electricity or the like, which is lower than the breakdown of the gate insulating film. It is to provide a structure in which electric charges due to a high voltage are released by a voltage and a gate insulating film is protected.

[0005]

A MIS can be formed by forming a second conductivity type well in a first conductivity type semiconductor substrate and further forming a first conductivity type drain and source in the well and on the substrate surface. The type semiconductor device has a structure in which at least the depth of the well below the drain is controlled to be shallower than the depth of the well in the region other than the drain.

In a MIS type semiconductor device in which a well of the second conductivity type is formed in a semiconductor substrate of the first conductivity type and a drain and a source of the first conductivity type are further formed in the well and on the surface of the substrate, At least the central bottom portion of the drain projects into the well, and the length of the projection is controlled.

In a MIS type semiconductor device in which a well of the second conductivity type is formed in a semiconductor substrate of the first conductivity type and a drain and a source of the first conductivity type are further formed in the well and on the substrate surface, At least the lower part of the center of the drain bottom has a structure in which a well region controlled to have a low concentration reaches the substrate from the drain bottom or occupies most of the region in the depth direction. It is characterized by

A second conductivity type well is formed in the first conductivity type semiconductor substrate, and a first well is formed in the well and on the substrate surface.
A conductive type drain and source are formed, and at least the depth of the well under the drain is controlled to be shallower than the depth of the well in the region other than the drain.
In the IS type semiconductor device, a) a step of forming a second conductivity type well in the first conductivity type semiconductor substrate, and b) element isolation between the second conductivity type well and the first conductivity type well on the substrate surface. A step of forming a region, c) a step of forming a source / drain diffusion layer of a first conductivity type on the surface of a second conductivity type well, d) a step of forming a gate electrode on the surface of the substrate, and e) high energy. The step of adjusting the depth of the well at least under the drain to a desired depth by the ion implantation of.

A second conductivity type well is formed in the first conductivity type semiconductor substrate, and the first well is formed in the well and on the substrate surface.
A conductive type drain and source are formed, and at least the depth of the well under the drain is controlled to be shallower than the depth of the well in the region other than the drain.
In the IS type semiconductor device, a) a step of implanting a first conductivity type impurity ion into a part of the first conductivity type semiconductor substrate, and b) a step of epitaxially growing a silicon single crystal on the substrate, c) a step of forming wells of the second conductivity type and the first conductivity type, d) a step of forming an element isolation region between the wells of the first conductivity type and the second conductivity type on the surface of the substrate, and e) A method of manufacturing a semiconductor device, comprising the step of forming first-conductivity-type source / drain diffusion layer regions in a second-conductivity-type well.

A second conductivity type well is formed on a first conductivity type semiconductor substrate, and source and drain diffusion layers of the first conductivity type are formed in the vicinity of the well surface. At least a part of the central bottom portion of the drain is the well. A MIS having a structure in which the length of the protrusion is controlled to protrude inside
A) type semiconductor device, a) a step of forming a second conductivity type well in a first conductivity type semiconductor substrate, and b) an element between the first conductivity type well and the second conductivity type well on the substrate surface. A step of forming an isolation region, c) a step of forming a source / drain diffusion layer of a first conductivity type in the vicinity of a well surface of a second conductivity type, e) a step of forming a gate electrode on the surface of the substrate, d ) A step of projecting a part of the diffusion layer at the central bottom of the drain diffusion layer into the well with good controllability.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. The structure of the semiconductor device as an example is an N-channel transistor, the gate film thickness is 15 nm, the transistor structure is a single drain structure, the drain impurity concentration is 5 × 10 ²⁰ cm ⁻³ , the well depth is 3 μm, and the well is 3 μm. The concentration is set to 5 × 10 ¹⁶ cm ⁻³ .

1 (a), 1 (b) and 1 (c) are sectional views of a semiconductor device according to an embodiment of the present invention. 100 is a gate electrode, 101 is an N type drain diffusion layer (hereinafter, drain), 102 is an N type source diffusion layer (hereinafter, source),
103 is an element isolation region, 104 is a P-type well region, 1
Reference numeral 05 is an N-type silicon substrate, and 106 is an N-type well region.

FIG. 1A shows a first embodiment of the present invention. Reference numeral 107 denotes a region in which the well depth according to the present invention is shallower than the normal well depth, and the line segment AB is
It represents the depth from the surface of the silicon substrate, and the depth is about 1.5 μm. The line segment CD represents the depth of a normal well, and the depth is 3 μm.
According to this structure, when a high voltage such as static electricity is applied, the depletion layer spreading from the N-type drain in the depth direction of the P-type well spreads in the depth direction with the applied voltage and spreads on the N-type substrate. It can reach and escape the charge. At that time, in the case of the above structure, the applied voltage reaches about 7 V and the depletion layer reaches the substrate.
Therefore, the potential of the well can be suppressed to about 7 V at most, so that the breakdown of the gate insulating oxide film can be avoided. Further, by changing the depth A-B of the well, it is possible to set the voltage for releasing the charges to a desired value. Further, unlike the conventional technique, since the concentration of impurities in the conductivity type region in contact with the drain is not increased, the junction capacitance does not change and the leak current amount does not increase either.

FIG. 1B shows a second embodiment of the present invention. Reference numeral 108 denotes a region in which a part of the central bottom of the N-type drain according to the present invention projects into the P-type well, and line segment EF is the depth of the projecting drain from the substrate surface. In the case of the structure of this embodiment, the depth is
It is controlled to about 2 μm. According to this structure, when a high voltage is applied by static electricity, the depletion layer spreading from the protruding drain reaches the N-type substrate and allows the charge to escape,
The gate insulating oxide film is protected.

FIG. 1C shows the third embodiment of the present invention. Reference numeral 109 indicates that the well concentration of a part of the drain central bottom portion according to the present invention is lower than the normal well concentration, and in the case of the structure of this embodiment, the P-type impurity concentration is 3 ×.
It is controlled to about 10 ¹⁵ cm ^-3 . According to this structure,
The depletion layer extending from the drain spreads deeper than in the case of a well having a conventional concentration, the depletion layer reaches the substrate at about 7 V, the gate insulating oxide film is protected, and a partial but low P-type well is formed. Since the concentration is increased, the junction capacitance can be reduced. Also, the junction leak does not increase.

2 (a) to 2 (e) are sectional views showing the main steps of the first embodiment shown above, and the method for manufacturing a semiconductor device of the present invention will be described in detail. First, N-type impurity ions and P-type impurity ions are implanted into an N-type substrate using a mask. At this time, as an example of N-type impurity ion implantation, boron is added at about 5 × 10 ¹² cm ⁻² at 60 KeV.
1.5 × 10 ¹³ cm ⁻² , and as an example of P-type impurities, phosphorus is 5 × 10 ¹² cm ^{−2 to} 1.5 at 120 KeV.
^{Implant at} about 10 ¹³ cm ^-2 . Then high temperature 1000
As shown in FIG. 2, the P-well region 204 and the N-well region 206 are thermally diffused at about 3 to 6 hours at a temperature of about 1.degree.
It is formed as shown in FIG. The depth of the well is about 3 μm. Next, a thermal oxide film having a thickness of about 15 nm to 50 nm is formed on the surface of the substrate, a silicon nitride film having a thickness of about 100 nm to 300 nm is formed on the substrate, and the silicon nitride film 210 is processed by the photolithography technique and the etching technique. If impurity ion implantation is necessary for forming the inversion element layer, the implantation is performed in this step or the like. Next, a thermal oxide film is formed on the substrate surface using the silicon nitride film 210 as a mask to form an element isolation region LOCOS 203, and the silicon nitride film is removed by hot phosphoric acid. However, in the present embodiment, LOCOS isolation was used as element isolation, but other element isolation does not cause any problem. Next, cleaning and thermal oxidation are repeated to form a gate insulating oxide film having a thickness of 15 nm. Next, impurity ions are implanted to adjust the threshold voltage, and an N-type polycrystalline silicon film of about 300 nm is formed to about 300 nm by chemical vapor deposition or the like. Next, the gate electrode 200 is processed by a photolithography technique and an etching technique to obtain a structure shown in FIG. Next, element isolation LO
The COS 203 and the gate electrode 200 are used as a mask in a self-aligned manner, and N-type impurity ions, for example, phosphorus are added at 50 KeV.
Drain and source are formed by implantation. Then, the impurity concentration of the source and drain becomes about 5 × 10 ²⁰ cm ⁻³ . Next, after applying a photoresist 211 of about 3 μm or more, it is processed by a photolithography technique and an etching technique so that the drain portion becomes a window of the photoresist. Next, an N-type impurity such as boron is added at 5 to 6 MeV.
To about 10 ¹⁴ to 10 ¹⁵ atoms / cm ³ in the P type well near the N type substrate 207. In this way, a P-type well is formed on the N-type semiconductor substrate, and an N-type drain and source are formed in the well and on the substrate surface. At least the depth of the well below the drain is equal to the drain. Embodiment 1 of the present invention having a structure in which it is controlled to be shallower than the depth of the well in the region other than
To obtain a semiconductor device.

FIGS. 3A to 3E are sectional views showing the main steps of the first embodiment, and the method for manufacturing a semiconductor device of the present invention will be described in detail. First, a photoresist is applied to a part of the silicon substrate 305, the photoresist is processed by a photolithography technique and an etching technique as shown in FIG. 3A, and N-type impurities are implanted 307 using the photoresist as a mask. Impurity concentration is 5 × 10 ¹⁶ at
It should be about oms / cm ³ . Next, after removing the photoresist with sulfuric acid or the like, single crystal silicon 310 is epitaxially grown on the surface of the silicon substrate by 2.
Grow about 5 μm. Next, N-type impurity ions and P-type impurity ions are implanted into the substrate. At this time, as an example of N-type impurity ion implantation, boron is about 5 × 10 ¹² cm ^{−2 to} 1.5 × 10 ¹³ cm ^{−2 at} about 60 KeV, and phosphorus is about 120 KeV as an example of P-type impurity. 5x
Implantation is performed at about 10 ¹² cm ^{-2 to} 1.5 × 10 ¹³ cm ^-2 .
Then, the P well region 304 and the N well region 306 are formed by thermal diffusion at a high temperature of about 1000 ° C. to 1200 ° C. for about 3 to 6 hours as shown in FIG. Then, the depth of the well becomes about 3 μm. Next, a thermal oxide film having a thickness of about 15 nm to 50 nm is formed on the surface of the substrate, a silicon nitride film having a thickness of about 100 nm to 300 nm is formed on the base, and a silicon nitride film 311 is formed by photolithography and etching as shown in FIG. ). If impurity ion implantation is necessary for forming the inversion element layer, the implantation is performed in this step or the like. Next, a thermal oxide film is formed on the substrate surface using the silicon nitride film 311 as a mask to form an element isolation region LOCOS 303, and the silicon nitride film is removed by hot phosphoric acid. Then, cleaning and thermal oxidation are repeated to form a gate insulating oxide film having a thickness of 15 nm. Next, impurity ions are implanted to adjust the threshold voltage,
By chemical vapor deposition, for example, N of about 300 nm
A polycrystalline silicon film of about 300 nm is formed. next,
The gate electrode 300 is formed by the photolithography technique and the etching technique. Next, element isolation LOCOS 30
3 and the gate electrode 300 are used as a mask in a self-aligning manner, and N
A type impurity ion, for example, phosphorus is implanted at about 50 KeV to form a drain and a source. Then, the impurity concentration of the source and drain becomes about 5 × 10 ²⁰ cm ⁻³ . However, when forming the element isolation region, the gate electrode, the drain, and the source, it was performed before growing the single crystal silicon,
It is necessary to take care so that at least the drain is formed on the portion where the impurity ion implantation is performed. In this embodiment, the lower part of the drain and the region into which the impurity ions are implanted before the growth of the single crystal silicon coincides with each other. In this way, the semiconductor device of the first embodiment of the present invention could be obtained.

An embodiment of the method of manufacturing a semiconductor device of the present invention will be described with reference to FIGS. 4A to 4E which are sectional views showing the main steps of the second embodiment shown above. 4 (a)-
In the step (d), as in the case described in FIGS. 2A to 2D, P-type and N-type wells, element isolation regions, gate insulating oxide films, gate electrodes, An N type drain and source are formed. Thereafter, for example, photoresist is applied, and through the steps of photolithography and etching technique, a hole of, for example, about 0.5 μm to 0.8 μm is formed in the photoresist like 410. still,
At this time, an insulating interlayer film between the silicon substrate and the wiring may be formed by a chemical vapor deposition method or the like without using a photoresist, and a contact hole may be formed thereafter. After that,
N-type impurity ions are implanted by masking the photoresist or the insulating interlayer film. At this time, if the impurity ions are arsenic, the implantation energy is 300 KeV.
Injecting at 10 ¹⁵ to 10 ¹⁶ atoms / cm ^{2 up} to about 3 MeV to 4 MeV in a step of ˜500 KeV, a part of the central bottom of the N type drain shown in the second embodiment of the present invention is projected into the P type well. Figure 4
It was able to be obtained like 407 of (e).

[0019]

According to the semiconductor device having the structure of the present invention, it is possible to release the electric charges when a high voltage is applied,
Therefore, a highly reliable semiconductor integrated circuit can be obtained. In addition, since the voltage for releasing the charge when applying a high voltage can be set arbitrarily, compared to the conventional technology,
It becomes easy to secure a large margin of capability of the gate insulating film and the element. At the same time, it facilitates miniaturization and high integration of the device. Not only that, conventionally, while the breakdown voltage of the junction is lowered, the junction capacitance and the junction leakage current are increased, which hinders the speeding up and reliability of the circuit. Since the capacity and the amount of junction leakage current do not increase, there is no influence on the speedup and the margin of reliability. In addition, high-energy ion implantation, epitaxial growth, and conventional techniques make it possible to manufacture a semiconductor device having the above structure.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

2A to 2C are cross-sectional views of main steps of a semiconductor device of the present invention.

3A to 3C are cross-sectional views of main steps of a semiconductor device of the present invention.

4A to 4C are cross-sectional views of main steps of a semiconductor device of the present invention.

FIG. 5 is a sectional view of a conventional semiconductor device.

[Explanation of symbols]

Gate electrode 100, 200, 30
0, 400, 500 drain regions 101, 201, 30
1, 401, 501 Source region 102, 202, 30
2, 402, 502 Element isolation regions 103, 203, 30
3, 403, 503 Second conductivity type well region 104, 204, 30
4, 404, 504 First conductivity type Si substrate 105, 205, 30
5, 405, 505 First conductivity type well regions 106, 206, 30
6, 406, 506 Well region with first well of shallow well depth
107, 207 drain region of the first conductivity type extending into the well
108, 307 Area where concentration is low in the second conductivity type well
109, 407 Silicon nitride film 211, 311, 41
1 photoresist 212, 412

Claims (6)

[Claims] 1. A second-conductivity-type well is formed in a first-conductivity-type semiconductor substrate, and a first-type well is formed in the well and on the substrate surface.
In a MIS type semiconductor device formed by forming a conductive type drain and source, at least the depth of the well under the drain is controlled to be shallower than the depth of the well in regions other than the drain. A semiconductor device characterized by: 2. A MIS type semiconductor device in which a well of the second conductivity type is formed in a semiconductor substrate of the first conductivity type, and a drain and a source of the first conductivity type are formed in the well and on the surface of the substrate. And a semiconductor device having a structure in which at least the central bottom portion of the drain projects into the well and the length of the projection is controlled. 3. A MIS type semiconductor device in which a well of the second conductivity type is formed on a semiconductor substrate of the first conductivity type, and a drain and a source of the first conductivity type are formed in the well and on the surface of the substrate. And a well region controlled to have a low concentration reaches the substrate from the drain bottom or occupies most of the region in the depth direction at least under a part of the center of the drain bottom. A semiconductor device comprising: 4. A second-conductivity-type well is formed in a first-conductivity-type semiconductor substrate, and the first-conductivity well is formed on the substrate surface in the well.
A conductive type drain and source are formed, and at least the depth of the well under the drain is controlled to be shallower than the depth of the well in the region other than the drain.
In the IS type semiconductor device, a) a step of forming a second conductivity type well in the first conductivity type semiconductor substrate, and b) element isolation between the second conductivity type well and the first conductivity type well on the substrate surface. A step of forming a region, c) a step of forming a source / drain diffusion layer of a first conductivity type on the surface of a second conductivity type well, d) a step of forming a gate electrode on the surface of the substrate, and e) high energy. 2. The method for manufacturing a semiconductor device, comprising the step of adjusting the depth of at least the well below the drain to a desired depth by the ion implantation of. 5. A second conductivity type well is formed in a first conductivity type semiconductor substrate, and the first conductivity type well is formed in the well and on the substrate surface.
A conductive type drain and source are formed, and at least the depth of the well under the drain is controlled to be shallower than the depth of the well in the region other than the drain.
In the IS type semiconductor device, a) a step of implanting a first conductivity type impurity ion into a part of the first conductivity type semiconductor substrate, and b) a step of epitaxially growing a silicon single crystal on the substrate, c) a step of forming wells of the second conductivity type and the first conductivity type, d) a step of forming an element isolation region between the wells of the first conductivity type and the second conductivity type on the surface of the substrate, and e) A method of manufacturing a semiconductor device, comprising the step of forming first-conductivity-type source / drain diffusion layer regions in a second-conductivity-type well. 6. A second-conductivity-type well is formed on a first-conductivity-type semiconductor substrate, and a source-drain diffusion layer of the first-conductivity type is formed in the vicinity of the well surface, and at least a part of the central bottom of the drain is formed. MIS having a structure in which the protrusion protrudes into the well and the length of the protrusion is controlled.
A) type semiconductor device, a) a step of forming a second conductivity type well in a first conductivity type semiconductor substrate, and b) an element between the first conductivity type well and the second conductivity type well on the substrate surface. A step of forming an isolation region, c) a step of forming a source / drain diffusion layer of a first conductivity type in the vicinity of a well surface of a second conductivity type, e) a step of forming a gate electrode on the surface of the substrate, d ) A method of manufacturing a semiconductor device, which comprises the step of protruding a part of the diffusion layer at the central bottom of the drain diffusion layer into the well with good controllability.