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JPH06295937A - Mounting method of photoelectric element - Google Patents

Mounting method of photoelectric element

Info

Publication number
JPH06295937A
JPH06295937A JP5067257A JP6725793A JPH06295937A JP H06295937 A JPH06295937 A JP H06295937A JP 5067257 A JP5067257 A JP 5067257A JP 6725793 A JP6725793 A JP 6725793A JP H06295937 A JPH06295937 A JP H06295937A
Authority
JP
Japan
Prior art keywords
electrode pad
solder
substrate
solder bump
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5067257A
Other languages
Japanese (ja)
Inventor
Yoshinobu Kanayama
義信 金山
Masataka Ito
正隆 伊藤
Hiroshi Honmo
宏 本望
Junichi Sasaki
純一 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5067257A priority Critical patent/JPH06295937A/en
Priority to GB9403980A priority patent/GB2276492A/en
Publication of JPH06295937A publication Critical patent/JPH06295937A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02375—Positioning of the laser chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/046—Surface mounting
    • H05K13/0465—Surface mounting by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)

Abstract

PURPOSE:To cut down the manufacturing cost for facilitating the mass production by mounting the non-adjusted photoelectric element with high precision. CONSTITUTION:Solder bumps 2 are melted down by heating a silicon substrate 4 by tack-mounting a laser diode 1 on the solder bumps 2 formed on the silicon substrate 4 so that the electrode pads 6 and 5 on the silicon substrate 4 may be aligned in the horizontal direction by surface tension and then said electrode pads 6 and 5 may be aligned in the vertical direction by pressing down the laser diode 1 by mechanical external force against alignment bases 3 in the vertical direction to cool down the silicon substrate 4 for fixing the same 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、光通信用光モジュール
等で用いられる光電素子の実装方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a photoelectric element used in an optical module for optical communication.

【０００２】[0002]

【従来の技術】通信分野では、情報の大容量化により、
電気信号による通信から大容量化に有利な光通信への移
行が進んでいる。さらに今日では、光通信の一般加入者
系への適用も考えられており、このため、光通信用光デ
バイスの低価格化が求められている。しかしながら、光
デバイスの製造においては、光電素子夫々の光軸を高精
度に合わせて基板上に実装する必要があり、光軸調整に
多くの工数が必要とされる。そこで、低価格化に有効な
手段となる光電素子を無調整で基板上に実装する方法が
検討されている。2. Description of the Related Art In the field of communication, due to the increase in information capacity,
There is an ongoing shift from optical signal communication to optical communication, which is advantageous for large capacity. Further, today, application of optical communication to general subscriber systems is also considered, and therefore, it is required to reduce the cost of optical devices for optical communication. However, in the manufacture of an optical device, it is necessary to mount the optical axes of the photoelectric elements on the substrate with high accuracy, and a large number of man-hours are required to adjust the optical axis. Therefore, a method of mounting a photoelectric element, which is an effective means for lowering the cost, on a substrate without adjustment is being studied.

【０００３】この無調整実装法の一例として、次のよう
な方法がある。すなわち、基板上に半田バンプを形成
し、この半田バンプ上に光電素子を仮置きして半田バン
プを加熱熔融させると半田はその表面張力で光電素子と
接合した状態で表面積が最小になるように形状を変化さ
せる。その結果、光電素子は半田の表面張力によって移
動し、光電素子が半田バンプの真上にくるように位置決
めされる（セルフアライメント効果）。As an example of this non-adjustment mounting method, there is the following method. That is, when a solder bump is formed on a substrate, a photoelectric element is temporarily placed on this solder bump, and the solder bump is heated and melted, the surface area of the solder is minimized in the state where the solder is bonded to the photoelectric element. Change the shape. As a result, the photoelectric element moves due to the surface tension of the solder, and the photoelectric element is positioned so as to be directly above the solder bump (self-alignment effect).

【０００４】このセルフアライメント効果を利用した一
例が、電子情報通信学会の光量子エレクトロニクス研究
会資料１９９１年８月の４５〜５０頁に紹介されてい
る。An example of utilizing this self-alignment effect is introduced on pages 45 to 50 of August 1991, material of the Photon Electronics Research Group of the Institute of Electronics, Information and Communication Engineers.

【０００５】[0005]

【発明が解決しようとする課題】従来の光電素子の実装
方法では、セルフアライメント効果により、基板にたい
して水平方向の位置決め精度は良好である。しかし、垂
直方向を実装上必要な±１μｍの精度に位置決めするに
は、半田の体積を０．１μｇ以下の精度で制御しなくて
はならず、極めて困難であった。In the conventional method for mounting a photoelectric device, the positioning accuracy in the horizontal direction with respect to the substrate is good due to the self-alignment effect. However, in order to position the vertical direction with an accuracy of ± 1 μm required for mounting, the volume of the solder must be controlled with an accuracy of 0.1 μg or less, which is extremely difficult.

【０００６】[0006]

【課題を解決するための手段】本発明の光電素子の第１
の実装方法は、基板上に設けた第１の電極パッドの上に
半田バンプを形成し、第２の電極パッドを設けた光電素
子の前記第２の電極パッドを前記半田バンプ上に位置合
わせして仮に載置する工程と、加熱により前記半田バン
プを熔融させ熔融した半田の表面張力を利用して前記第
１の電極パッドと第２の電極パッドとの基板表面に対し
て水平方向の位置を整合させる工程と、前記光電素子を
上方より垂直に押し下げ前記第１の電極パッドの近傍に
設けた位置決め台の上面に前記光電素子の下面を押付け
て垂直方向の位置を設定した後冷却して固定する工程と
を含んで構成される。The first aspect of the photoelectric device of the present invention
In the mounting method, the solder bump is formed on the first electrode pad provided on the substrate, and the second electrode pad of the photoelectric device provided with the second electrode pad is aligned on the solder bump. And temporarily placing the solder bumps by heating and using the surface tension of the molten solder to position the first electrode pad and the second electrode pad in the horizontal direction with respect to the substrate surface. The step of aligning and pressing the photoelectric element vertically from above and pressing the lower surface of the photoelectric element against the upper surface of the positioning table provided in the vicinity of the first electrode pad to set the vertical position and then fixing by cooling And a step of performing.

【０００７】本発明の光電素子の第２の実装方法は、基
板上に設けた第１の電極パッドの上に半田バンプを形成
し、第２の電極パッドを設けた光電素子の前記第２の電
極パッドを前記半田バンプ上に位置合わせして仮に載置
する工程と、加熱により前記半田バンプを熔融させ熔融
した半田の前記第２の電極パッドの表面への濡れ広がり
を利用して前記半田バンプの厚みを徐々に減少させて前
記第１の電極パッドの近傍に設けた位置決め台の上面に
前記光素子の下面を突き当て垂直方向の位置を設定する
と同時に、熔融した半田の表面張力を利用して前記第１
の電極パッドと第２の電極パッドとの基板表面に対して
水平方向の位置を整合させる工程とを含んで構成され
る。According to a second method of mounting a photoelectric element of the present invention, a solder bump is formed on a first electrode pad provided on a substrate, and the second step of the photoelectric element provided with a second electrode pad. The step of temporarily placing the electrode pad on the solder bump by aligning it, and melting the solder bump by heating to utilize the spread of the melted solder on the surface of the second electrode pad The thickness of the optical element is gradually decreased to set the vertical position by abutting the lower surface of the optical element against the upper surface of the positioning table provided near the first electrode pad, and at the same time, the surface tension of the molten solder is used. The first
And the step of aligning the horizontal positions of the electrode pad and the second electrode pad with respect to the substrate surface.

【０００８】[0008]

【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【０００９】図１（ａ）〜（ｄ）は本発明の第１の実施
例を説明するための工程順に示した断面図である。FIGS. 1A to 1D are sectional views showing the steps in order to explain the first embodiment of the present invention.

【００１０】まず、図１（ａ）に示すように、放熱性支
持体等に用いられるシリコン基板４の上にクロム膜およ
び金膜を積層して設けた直径４５〜５５μｍの円形の電
極パッド６と、この電極パッド６の上に形成した金錫か
らなる半田バンプ２と、この半田バンプ２の近傍のシリ
コン基板４の上に二酸化珪素からなる高さ１０μｍの位
置決め台３とを形成し、クロム膜および金膜を積層して
形成した直径５０μｍの円形の電極パッド５を有する半
導体レーザダイオード１の電極パッド５を半田バンプ２
の上に位置合わせして仮に載置する。First, as shown in FIG. 1A, a circular electrode pad 6 having a diameter of 45 to 55 μm is formed by laminating a chromium film and a gold film on a silicon substrate 4 used as a heat dissipation support or the like. A solder bump 2 made of gold tin formed on the electrode pad 6 and a positioning base 3 made of silicon dioxide and having a height of 10 μm formed on the silicon substrate 4 in the vicinity of the solder bump 2. Solder bumps 2 are provided with electrode pads 5 of semiconductor laser diode 1 having circular electrode pads 5 with a diameter of 50 μm formed by laminating a film and a gold film.
Position it on the top and place it temporarily.

【００１１】ここで、電極バッド５と半田バンプ２の位
置合わせ精度は特に高くする必要がなく、接合しようと
する電極パッド５，６の直径の１／４以内の精度があれ
ばよい。Here, the alignment accuracy of the electrode pad 5 and the solder bump 2 does not need to be particularly high, and may be within 1/4 of the diameter of the electrode pads 5 and 6 to be joined.

【００１２】次に、図１（ｂ）に示すように、加熱によ
り半田バンプ２を熔融させると、熔融した半田は表面張
力により表面積が最小になるような形状になろうとして
レーザダイオード１を水平方向に移動させはじめる。Next, as shown in FIG. 1 (b), when the solder bumps 2 are melted by heating, the melted solder is made to have a shape in which the surface area is minimized due to the surface tension, and the laser diode 1 is leveled. Start moving in the direction.

【００１３】次に、図１（ｃ）に示すように、熔融した
半田の表面積が最小になった状態で電極パッド５の水平
位置が電極パッド６の位置に自動的に高精度に整合（セ
ルフアライメント）される。Next, as shown in FIG. 1 (c), the horizontal position of the electrode pad 5 is automatically and accurately aligned with the position of the electrode pad 6 (self-alignment) with the surface area of the molten solder minimized. Be aligned).

【００１４】次に、図１（ｄ）に示すように、レーザダ
イオード１を機械的外力により垂直に下方へ押下げてレ
ーザダイオード１の下面を位置決め台３の上面に押付
け、垂直方向の位置合わせを行い、その状態で実装基板
を冷却して半田を固化させ、レーザダイオード１を高精
度に位置決めできる。Next, as shown in FIG. 1 (d), the laser diode 1 is vertically pushed downward by a mechanical external force so that the lower surface of the laser diode 1 is pressed against the upper surface of the positioning base 3 for vertical alignment. In this state, the mounting substrate is cooled to solidify the solder, and the laser diode 1 can be positioned with high accuracy.

【００１５】図２（ａ）〜（ｄ）は本発明の第２の実施
例を説明するための工程順に示した断面図である。2 (a) to 2 (d) are sectional views showing the second embodiment of the present invention in process order.

【００１６】まず、図２（ａ）に示すように、第１の実
施例と同様に構成した電極パッド６、半田バンプ２、位
置決め台３を有するシリコン基板４に直径が８０μｍの
円形の電極パッド７を形成したレーザダイオード１の電
極パッド７を半田バンプ２の上に位置合わせして仮に載
置する。First, as shown in FIG. 2A, a circular electrode pad having a diameter of 80 μm is formed on a silicon substrate 4 having an electrode pad 6, a solder bump 2 and a positioning base 3 which are constructed in the same manner as in the first embodiment. The electrode pad 7 of the laser diode 1 on which 7 is formed is aligned with the solder bump 2 and temporarily placed.

【００１７】次に、図２（ｂ）に示すように、加熱によ
り半田バンプを熔融させると、熔融した半田が電極パッ
ド７の表面に濡れ広がり始める。Next, as shown in FIG. 2B, when the solder bump is melted by heating, the melted solder begins to spread on the surface of the electrode pad 7.

【００１８】次に、図２（ｃ）に示すように、熔融した
半田が更に電極パッド７の表面に濡れ広がるに従って半
田バンプ２の厚みが減少してレーザダイオード１の下面
が位置決め台３に近づき同時に熔融した半田の表面張力
により電極パッド７と電極パッド６の位置が整合される
方向に水平移動する。Next, as shown in FIG. 2C, the thickness of the solder bump 2 decreases as the molten solder spreads on the surface of the electrode pad 7, and the lower surface of the laser diode 1 approaches the positioning table 3. At the same time, the surface tension of the molten solder causes the electrode pads 7 and 6 to move horizontally in a direction in which the positions of the electrode pads 6 are aligned.

【００１９】次に、図２（ｄ）に示すように、電極パッ
ド７と電極パッド６が水平方向に整合されると共に半田
の濡れ広がりにより半田バンプの厚みが更に減少してレ
ーザダイオード１の下面が位置決め台３に接し、垂直方
向にも高精度に位置決めされる。この状態で、基板を冷
却して半田を固化させ、レーザダイオード１を固定す
る。Next, as shown in FIG. 2D, the electrode pad 7 and the electrode pad 6 are aligned in the horizontal direction, and the thickness of the solder bump is further reduced due to the spread of the wetting of the solder, so that the lower surface of the laser diode 1 is reduced. Contacts the positioning table 3 and is positioned with high accuracy in the vertical direction. In this state, the substrate is cooled to solidify the solder, and the laser diode 1 is fixed.

【００２０】[0020]

【発明の効果】以上説明したように、本発明の方法によ
れば、光電素子を容易に高精度に実装できるので、製造
コストが低くなり、大量生産も容易になるという効果を
有する。As described above, according to the method of the present invention, the photoelectric device can be easily mounted with high precision, so that the manufacturing cost can be reduced and the mass production can be facilitated.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例を説明するための工程順
に示した断面図。1A to 1D are cross-sectional views showing a process sequence for explaining a first embodiment of the present invention.

【図２】本発明の第２の実施例を説明するための工程順
に示した断面図。2A to 2D are sectional views showing a process sequence for explaining a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ レーザダイオード ２ 半田バンプ ３ 位置決め台 ４ シリコン基板 ５，６，７ 電極パッド 1 Laser diode 2 Solder bump 3 Positioning stand 4 Silicon substrate 5, 6, 7 Electrode pad

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐々木 純一 東京都港区芝五丁目７番１号日本電気株式 会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junichi Sasaki 5-7-1, Shiba, Minato-ku, Tokyo NEC Corporation

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 基板上に設けた第１の電極パッドの上に
半田バンプを形成し、第２の電極パッドを設けた光電素
子の前記第２の電極パッドを前記半田バンプ上に位置合
わせして仮に載置する工程と、加熱により前記半田バン
プを熔融させ熔融した半田の表面張力を利用して前記第
１の電極パッドと第２の電極パッドとの基板表面に対し
て水平方向の位置を整合させる工程と、前記光電素子を
上方より垂直に押し下げ前記第１の電極パッドの近傍に
設けた位置決め台の上面に前記光電素子の下面を押付け
て垂直方向の位置を設定した後冷却して固定する工程と
を含むことを特徴とする光素子の実装方法。1. A solder bump is formed on a first electrode pad provided on a substrate, and the second electrode pad of a photoelectric device provided with a second electrode pad is aligned on the solder bump. And temporarily placing the solder bumps by heating and using the surface tension of the molten solder to position the first electrode pad and the second electrode pad in the horizontal direction with respect to the substrate surface. The step of aligning and pressing the photoelectric element vertically from above and pressing the lower surface of the photoelectric element against the upper surface of the positioning table provided in the vicinity of the first electrode pad to set the vertical position and then fixing by cooling A method for mounting an optical element, comprising: 【請求項２】 基板上に設けた第１の電極パッドの上に
半田バンプを形成し、第２の電極パッドを設けた光電素
子の前記第２の電極パッドを前記半田バンプ上に位置合
わせして仮に載置する工程と、加熱により前記半田バン
プを熔融させ熔融した半田の前記第２の電極パッドの表
面への濡れ広がりを利用して前記半田バンプの厚みを徐
々に減少させて前記第１の電極パッドの近傍に設けた位
置決め台の上面に前記光素子の下面を突き当て垂直方向
の位置を設定すると同時に、熔融した半田の表面張力を
利用して前記第１の電極パッドと第２の電極パッドとの
基板表面に対して水平方向の位置を整合させる工程とを
含むことを特徴とする光電素子の実装方法。2. A solder bump is formed on a first electrode pad provided on a substrate, and the second electrode pad of a photoelectric device provided with a second electrode pad is aligned on the solder bump. And the step of temporarily placing the solder bumps on the surface of the second electrode pad by melting and melting the solder bumps by heating. The lower surface of the optical element is abutted against the upper surface of the positioning table provided in the vicinity of the electrode pad of FIG. And a step of aligning a position of the electrode pad in the horizontal direction with respect to the surface of the substrate, the method for mounting a photoelectric device.
JP5067257A 1993-03-26 1993-03-26 Mounting method of photoelectric element Pending JPH06295937A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP5067257A JPH06295937A (en) 1993-03-26 1993-03-26 Mounting method of photoelectric element
GB9403980A GB2276492A (en) 1993-03-26 1994-03-02 Mounting structure of optical element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5067257A JPH06295937A (en) 1993-03-26 1993-03-26 Mounting method of photoelectric element

Publications (1)

Publication Number Publication Date
JPH06295937A true JPH06295937A (en) 1994-10-21

Family

ID=13339720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5067257A Pending JPH06295937A (en) 1993-03-26 1993-03-26 Mounting method of photoelectric element

Country Status (2)

Country Link
JP (1) JPH06295937A (en)
GB (1) GB2276492A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
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JPH08250818A (en) * 1995-03-10 1996-09-27 Nec Corp Manufacture of semiconductor device
WO1997002596A1 (en) * 1995-06-30 1997-01-23 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
JP2009544147A (en) * 2006-07-14 2009-12-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Installation of electro-optical components aligned with optical elements
JP2011128290A (en) * 2009-12-16 2011-06-30 Hitachi High-Technologies Corp Light source device, and backlight, exposure device and exposure method using the same
JP2020166189A (en) * 2019-03-29 2020-10-08 日東電工株式会社 Optical element-mounted optical/electrical hybrid substrate and manufacturing method therefor

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JP2924953B2 (en) * 1996-11-05 1999-07-26 日本電気株式会社 Optical device mounting structure
DE19750073A1 (en) * 1997-11-12 1999-05-20 Bosch Gmbh Robert Circuit board
FR2771321B1 (en) * 1997-11-26 1999-12-17 Commissariat Energie Atomique METHOD FOR ASSEMBLING TWO STRUCTURES BY A SOLDERING CORD AND ASSEMBLY OBTAINED BY THIS METHOD
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US20050135725A1 (en) * 2003-12-23 2005-06-23 3M Innovative Properties Company Laser submounts with standoff structures
CN103368062A (en) * 2012-03-26 2013-10-23 鸿富锦精密工业（深圳）有限公司 Wafer-packaging structure and packaging method thereof
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JPS57112039A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of semiconductor device
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JPS58202540A (en) * 1982-05-21 1983-11-25 Nippon Telegr & Teleph Corp <Ntt> Method of bonding fine positioning by stand-off

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250818A (en) * 1995-03-10 1996-09-27 Nec Corp Manufacture of semiconductor device
WO1997002596A1 (en) * 1995-06-30 1997-01-23 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
US6262513B1 (en) 1995-06-30 2001-07-17 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
US6628043B2 (en) 1995-06-30 2003-09-30 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
US6754950B2 (en) 1995-06-30 2004-06-29 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
JP2009544147A (en) * 2006-07-14 2009-12-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Installation of electro-optical components aligned with optical elements
JP2011128290A (en) * 2009-12-16 2011-06-30 Hitachi High-Technologies Corp Light source device, and backlight, exposure device and exposure method using the same
JP2020166189A (en) * 2019-03-29 2020-10-08 日東電工株式会社 Optical element-mounted optical/electrical hybrid substrate and manufacturing method therefor

Also Published As

Publication number Publication date
GB2276492A (en) 1994-09-28
GB9403980D0 (en) 1994-04-20

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