JPH0629538A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress increase in the peripheral region of a semiconductor substrate (semiconductor chip) by contriving to arrange gate wiring layout. CONSTITUTION:A vertical MISFET with a semiconductor substrate as a drain region is laid out on the main surface of a center region 20 of the semiconductor substrate (a semiconductor chip 1), a second conductive type semiconductor region is laid out along the peripheral region on the main surface of a peripheral region 21 surrounding the perimeter of the center region 20 of the semiconductor substrate, and a first contact part 9b where a gate wiring 10B is connected to a gate electrode 6 of the vertical MISFET and a second contact part 9c where a wiring 10c with the same potential as a source wiring 10A which is connected to the source region of the MISFET is connected to the second conductive type semiconductor region are laid out on the peripheral region 21 of the semiconductor substrate. In this semiconductor device, the first contact part 9b and the second contact part 9c are laid out alternately in the direction of extension of the gate wiring 10B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device having a single structure on which a vertical MISFET is mounted.

[0002]

2. Description of the Related Art In a semiconductor device (power MOSFET) having a single-piece structure in which a vertical MOSFET is mounted, a gate wiring connected to a gate electrode of the MOSFET is arranged in a central region of the semiconductor chip with an increase in chip size. With
Gate wirings are also arranged in a peripheral region surrounding the central region of the semiconductor chip. This is to connect (contact) the gate wiring to the gate electrode in the peripheral region of the semiconductor chip in order to reduce the gate resistance of the MOSFET.

Regarding the semiconductor device, for example, in 1987, International Rectifier (I
International issued by nternational Rectifier)
Rectifier Application Note (Interna
National Rectifier Application Note).

[0004]

The present inventor has found the following problems as a result of studying a single structure semiconductor device (power MOSFET) on which the above-mentioned vertical MOSFET is mounted.

In the above semiconductor device, a plurality of vertical MOSFETs are regularly arranged in a matrix in the central region of the semiconductor chip and electrically connected in parallel. How is this in a limited chip area? The design point for reducing the on-resistance is arranging a large number. Therefore, in order to make the inactive region (the region where MOSFETs cannot be arranged) on the semiconductor chip as small as possible, it is necessary to devise a layout.

In the peripheral region of the semiconductor chip, a junction for securing the breakdown voltage of the element such as a guard ring portion and a field limiting portion is usually formed and is one of the inactive regions. When the gate wiring that makes contact with the gate electrode is arranged in the peripheral region of this semiconductor chip, the connection region for making contact with the gate electrode is taken in as a part of the peripheral region, so the peripheral length becomes longer and the semiconductor chip The peripheral region (inactive region) increases, which is a disadvantage for the on-resistance design.

An object of the present invention is to suppress an increase in the peripheral region (inactive region) of a semiconductor chip by devising a gate wiring in a layout in a semiconductor device having a single structure in which a vertical MISFET is mounted. To provide possible technology.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

A vertical MISFE having a drain region on the main surface of the central region of the first conductivity type semiconductor substrate.
T is disposed, a second conductivity type semiconductor region is disposed along the peripheral region on the main surface of a peripheral region surrounding the central region of the semiconductor substrate, and a gate wiring is connected to the gate electrode of the vertical MISFET. First contact portion, the MI
In the semiconductor device, each of the second contact portions connecting the wiring having the same potential as the source wiring connected to the source region of the SFET to the semiconductor region of the second conductivity type is arranged in the peripheral region of the semiconductor substrate. 1 contact part, 2nd
The contact portions are alternately arranged along the extending direction of the gate wiring.

[0011]

According to the above-mentioned means, by arranging the first contact portion and the second contact portion alternately, the occupied areas of the first contact portion and the second contact portion are offset, and the first contact portion is offset. Since the occupied area of the peripheral region of the semiconductor substrate can be reduced as compared with the case where the portion and the second contact portion are arranged in parallel, the increase of the peripheral region of the semiconductor substrate can be suppressed.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a vertical MI according to an embodiment of the present invention.
2 is a chip layout diagram showing a schematic structure of a semiconductor device having a single structure on which an SFET (power transistor) is mounted.
2 is an enlarged plan view of a region 1A surrounded by the one-dot chain line shown in FIG. 1, FIG. 3 is a sectional view of an essential part taken along the line AA shown in FIG. 2, and FIG. It is a principal part sectional view cut by the B cutting line.

As shown in FIG. 1, a semiconductor device having a single structure on which a vertical MISFET according to an embodiment of the present invention is mounted is composed of a semiconductor chip 1 having a rectangular planar shape.

In the central area (effective area or active area) 20 of the semiconductor chip 1, a plurality of vertical MISFETs (power transistors) are arranged. This multiple vertical M
The ISFETs are regularly arranged in a matrix and electrically connected in parallel. A peripheral region 21 is arranged around the central region 20 of the semiconductor chip 1. This peripheral area 21 is
Surrounding the area where the vertical MISFETs are arranged,
The planar shape is a ring shape.

The semiconductor chip 1 basically has a single-layer wiring structure (single-layer aluminum wiring structure). In the central area 20 of the semiconductor chip 1, the source wiring 10A is formed in most of the area, and the gate wiring 1 is formed in part of the area.
0B is configured. In addition, the peripheral region 2 of the semiconductor chip 1
In FIG. 1, a wiring (source field plate) 10C having the same potential as the source wiring 10A is formed in most of the area, and a gate wiring 10B is formed in a part of the area.
That is, in the semiconductor device of this embodiment, the gate wiring 10B is also arranged in the peripheral region 21 of the semiconductor chip 1 for the purpose of reducing the gate resistance.

As shown in FIGS. 2, 3 and 4, the semiconductor chip 1 is a semiconductor substrate having an n type epitaxial layer 12 formed on the main surface of an n + type semiconductor substrate 11 made of, for example, single crystal silicon. Mainly composed.

In the central region of the semiconductor substrate, that is, in the central region 20 of the semiconductor chip 1, the n-type epitaxial layer 1 is formed.
A vertical MISFET is formed on the main surface of 2. This vertical MISFET is formed on the main surface of the active region of the n-type epitaxial layer 12 surrounded by the field insulating film 4. That is, the vertical MISFET is composed of the channel forming region, the source region, the drain region, the gate insulating film 5, the gate electrode 6, and the like. The channel formation region is composed of the p-type semiconductor region 8 formed on the main surface of the n-type epitaxial layer 12. The p-type semiconductor region 8 is integrally formed with the p-type semiconductor region 8 for the purpose of ohmic connection with the source wiring 10A. The source region is composed of the n + type semiconductor region 7 formed on the main surface of the p type semiconductor region 8. The drain region is a semiconductor substrate (n + type semiconductor substrate 1
1 and n-type epitaxial layer 12). The gate insulating film 5 is formed of, for example, a silicon oxide film formed by a thermal oxidation method. The gate electrode 6 is formed of, for example, a polycrystalline silicon film. The field insulating film 4 is formed of, for example, a silicon oxide film formed by a selective oxidation method.

The p-type semiconductor region 8 (and 2) which is a channel forming region of the vertical MISFET and n + which is a source region of the vertical MISFET.
A source line 10A is connected to each of the type semiconductor regions 7. The source wiring 10A extends on the interlayer insulating film 9 in the central region 20 of the semiconductor substrate, and through the connection hole (contact portion) 9a formed in the interlayer insulating film 9, the p-type semiconductor region 8 and the n + type semiconductor region are formed. 7 connected to each. The interlayer insulating film 9 is formed of, for example, a PSG film.

In the peripheral region of the semiconductor substrate, that is, the peripheral region 21 of the semiconductor chip 1, the n-type epitaxial layer 1 is formed.
A p-type semiconductor region 3 is formed on the main surface of 2. The p-type semiconductor region 3 forms a pn junction, that is, a die-auto junction with the n-type epitaxial layer 12. The p-type semiconductor region 3 is
The vertical MI is formed along the peripheral region 21 of the semiconductor substrate.
Region where SFET is formed (central region 20 of semiconductor substrate)
Surrounds the. The p-type semiconductor region 3 is formed in the same manufacturing process as the p-type semiconductor region 2.

A wiring 10C electrically connected to the source wiring 10A is connected to the p-type semiconductor region 3 forming a diode junction with the n-type epitaxial layer 12. The wiring 10C extends over the interlayer insulating film 9 in the peripheral region 21 of the semiconductor substrate and is connected to the p-type semiconductor region 3 through the connection hole (second contact portion) 9c formed in the interlayer insulating film 9. It That is, a voltage having the same potential as that of the n + type semiconductor region 7, which is the source region, is applied to the p type semiconductor region 3.

A gate wiring 10B is connected to the gate electrode 6 of the vertical MISFET. This gate wiring 10B
Extends over the interlayer insulating film 9 in the central region 20 and the peripheral region 21 of the semiconductor substrate and is connected to the gate electrode 6 through the connection hole (first contact portion) 10b formed in the interlayer insulating film 9. .

A gate wiring 10 is formed on the source wiring 10A.
A final protective film (not shown) is formed on the entire surface of the semiconductor substrate including B and the wiring 10C. The final protective film is formed of, for example, a polyimide resin film.

In the gate electrode 10B, the connection hole (first contact portion) 9b for connecting the gate wiring 10B extending to the peripheral region 21 of the semiconductor substrate to the gate electrode 6 is along the extending direction of the gate wiring 10B. Are provided in plural. A plurality of connection holes (second contact portions) 9c for connecting the wiring 10C to the p-type semiconductor region 3 are provided along the extending direction of the wiring 10C. These connection holes 9
b and the connection hole 9c are alternately arranged along the extending direction of the gate wiring 10B. In this way, the connection holes 9b and 9c provided in the peripheral region of the semiconductor substrate are alternately arranged along the direction in which the gate wiring 10B extends, so that the connection holes 9b and 9c are respectively provided. Therefore, the peripheral length of about 20 to 25 μm can be shortened in the same mask rule as compared with the case where the connection holes 9b and 9c are arranged in parallel. That is, when the peripheral length is 150 μm and the chip size is 5.0 mm × 5.0 mm, the central region 20 is 1.7.
% Can be increased. This means that the on-resistance can be reduced by 1.7% as it is, which means an improvement in performance. Further, if the on-resistance is constant, it is equivalent to reducing the area of the central region 20 of the semiconductor substrate by 1.7%, which can be parasitic to the reduction of the semiconductor chip 1. As a result, it is possible to suppress an increase in the peripheral region 21 of the semiconductor chip (semiconductor substrate) 1.

The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0027]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor device having a single structure in which a vertical MISFET is mounted, it is possible to suppress an increase in the peripheral area of a semiconductor chip (semiconductor substrate).

[Brief description of drawings]

FIG. 1 is a vertical MISFET according to an embodiment of the present invention.
A chip layout diagram showing a schematic configuration of a semiconductor device on which a (power transistor) is mounted,

FIG. 2 is an enlarged plan view of a region surrounded by an alternate long and short dash line shown in FIG.

FIG. 3 is a sectional view of a main part taken along the line AA shown in FIG.

FIG. 4 is a sectional view of a main part taken along the line BB shown in FIG.

[Explanation of symbols]

1 ... Semiconductor chip (semiconductor substrate), 2, 3 ... P-type semiconductor region, 4 ... Field insulating film, 5 ... Gate insulating film, 6 ... Gate electrode, 7 ... N + type semiconductor region, 8 ... P-type semiconductor region,
9 ... Interlayer insulating film, 9a, 9b, 9c ... Connection hole (contact part), 10A ... Source wiring, 10B ... Gate wiring, 1
0C ... Wiring, 11 ... N + type semiconductor substrate, 12 ... N type epitaxial layer, 20 ... Central region of semiconductor chip, 21 ... Peripheral region of semiconductor chip.

Claims (1)

[Claims] 1. A vertical MISF having a drain region on the main surface of a central region of a first conductivity type semiconductor substrate.
ET is arranged, a second conductivity type semiconductor region is arranged along the peripheral region on a main surface of a peripheral region surrounding the central region of the semiconductor substrate, and a gate wiring is connected to a gate electrode of the vertical MISFET. First contact portion, M
A second wiring for connecting a wiring having the same potential as the source wiring connected to the source area of the ISFET to the second conductivity type semiconductor area
In the semiconductor device in which each of the contact portions is arranged in the peripheral region of the semiconductor substrate, each of the first contact portion and the second contact portion is alternately arranged along the extending direction of the gate wiring. Semiconductor device.