JPH06291678A - Address generating circuit for two-dimensional encoding table - Google Patents

Abstract

PURPOSE:To decrease the circuit scale and the capacity of a memory for the two-dimensional encoding table and to increase the processing speed. CONSTITUTION:This circuit is provided with coincidence detectors 1a-1f which output coincidence detection signals which vary to an active level when inputted (x) and (y) are equal to integers of 1-3. Further, the circuit is provided with large/small comparators 2a-2f which output comparison result signals which varied to the active level when (x) and (y) are below 32, 16, and 8. The circuit is provided with an escape signal generating circuit 3 which varies to the active level when there is no pair of a coincidence detection signal and a comparison result signal which are both at the active level. Furthermore, the circuit is provided with an address generation part 5 which generates address signals AD by combining discrimination addresses ADi of 1-3 of (x) and (y) with the inputted corresponding (y) and (x).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generation circuit for a two-dimensional encoding table, and more particularly to an address generation circuit for a two-dimensional encoding table when codewords are biased to values in a predetermined range of two events. Regarding the circuit.

[0002]

2. Description of the Related Art When encoding a time-series signal with a biased occurrence frequency, a unequal length code is used, in which a short code is given to a signal with a high occurrence frequency and a long code is given to a signal with a low occurrence frequency. It is known that compression encoding is possible. Such coding is called entropy coding (Huffman code is a kind of entropy code). Entropy coding has been applied in various fields such as coding of audio signals and image signals.

In variable length coding / decoding, the average code length can be minimized by coding to a bit length corresponding to the logarithm (base 2) of the reciprocal of the appearance frequency of each code. .

In particular, when a large amount of data is transmitted or stored, and if the occurrence probability of data is significantly biased, data compression by entropy coding is effective. For example, if you want to record the wind direction every day for the past 100 years:
If north, 01: northeast, 001: south, 0001: west, etc. are set, it is advantageous in data compression in a region with a lot of north winds.
It is self-evident that different code assignments will be more advantageous in the west windy regions. Similarly, when recording daily wind speeds for the past 100 years, in order of highest occurrence probability of data, 1: 10m, 01: 30m, 001: 5m,
It can be encoded as 0001: 20 m, etc.

In the above-mentioned code assignment, coding is performed by using a one-dimensional parameter such as wind direction or wind speed. In addition to this, coding having two parameters (two-dimensional coding) may be considered. I can. This is to assign short codes in descending order of occurrence probability based on the combination of both wind direction and wind speed intensity. For example, 1: north wind 10m, 01: south wind 30m, 10: northeast. It can be encoded as wind of 10 m, wind of 001: wind of 10 m, and so on.

Generally, in entropy coding, the larger the code set, the more complicated the entropy code allocation (particularly in a two-dimensional code, the code set is a direct product of two code sets). In order to deal with such a case, an "escape code" may be used for a code having a sufficiently low occurrence probability. This escape code is followed by an escape identifier as an entropy code,
It takes the form of concatenating the values of two codes (binary fixed length codes). According to the definition of this escape code, the size of the encoding table can be reduced by assigning an entropy code to a combination having a high occurrence probability and an escape code to a combination that does not occur. As an example of the escape code, the wind direction code is north: 0000, south 0001, east: 0010, west: 0011, northeast: 010.
0, northwest: 0101, and 16 wind directions are encoded using 4 bits, and wind speed is 0 m: 0 every 10 m using 6 bits.
00000, 10m: 000001, 20m: 0000
It is encoded as 10, 30 m: 000011. A low state can be encoded by connecting two codes in which the upper 4 bits are the wind direction and the lower 6 bits are the wind speed.

In addition to the escape code, there is an EOB code word as a code word having a special meaning. The EOB code indicates the end of encoding within a block, with N × N pixels serving as an encoding unit being one processing unit (block). In particular, when zero data continues to the end of the block, no coding is performed and the EOB code word is set instead. Thereby, the encoded data can be further reduced.

FIG. 7 shows the distribution of code words in a two-dimensional code for two general events, wind direction A and wind speed B.
Codewords with a high probability of occurrence are biased to areas where the value of A is small and the value of B is small. The area of the entropy code is the range shown by the diagonal lines in FIG. 7, and the other areas are regarded as the escape code.

The encoding table generally assigns each code word to each address on the memory. To reference the corresponding codeword, the assigned address must be determined. Particularly, in the two-dimensional coding table, the address of the coding table is calculated from the values of two events. Conventionally, the following example has been considered as an address generation circuit for such a two-dimensional encoding table.

One is a circuit for reading a code word corresponding to two event values from a coding table by a program. As the configuration of this example, a CP that processes a program
U is required, and an instruction memory for storing the program is required. Appropriate addresses are allocated on the memory for all code words. Program is Event A
And the value of event B are detected, and the addresses corresponding to these two parameters are output. For example, when reading the address of the code word of the north wind 10 m, A = 0001 and B = 00
0001, and the stored address of the codeword is 0
Considering the case of address 010, it is programmed to read address 0010 by the condition judgment of (A = 0001) and (B = 000001). For all code words, conditions are judged from the values of the events A and B to generate the addresses of the coding table.

It is also conceivable to input the values of the two events A and B into a hardware means such as a comparator or a detector to output the address of the coding table. That is, it is a method of generating the address of the codeword by hardware using a dedicated decoder.

Furthermore, the simplest circuit is two events A,
In this method, the value of B is regarded as an address. It is possible to generate the address of the encoding table by connecting the values of A and B with the value of the event A as the upper address and the value of the event B as the lower address. In the configuration, it is not necessary to add dedicated hardware and the address can be easily generated, but on the contrary, the memory capacity of the encoding table becomes large. For example, in the above example, a 1K word memory is required to correspond to a 10-bit address.

[0013]

In the address generating circuit of the conventional two-dimensional encoding table described above, in the circuit according to the program of the first example, the values of two events A and B are sequentially compared on the program. To output the address,
It requires a comparative calculation processing time, cannot be used for high-speed processing such as real-time image processing, and requires a system for address generation such as an instruction memory for storing programs including a CPU. Have.

When the detecting means of the second example is implemented by hardware, dedicated hardware for detecting the address of the encoding table corresponding to the values of the two events A and B is required, and There is a problem in that the circuit scale becomes large because a detection circuit is required for code words of more than 100 words.

Furthermore, the two parameters A and B of the third example.
There is a problem that the memory capacity becomes large in the simplest circuit in which the value of is regarded as a real address and the address is generated from the combination of these two values. If the values of A and B are 5 bits, a total of 10 bits requires a memory capacity of 1K words. However, in the entropy code, the code distribution is biased as shown in the figure, so 1K
About 10% of about 112 words actually have valid codewords in the word memory, which is wasteful.

An object of the present invention is to provide an address generation circuit for a two-dimensional encoding table, which has a high operation speed and can reduce the memory capacity and the circuit scale.

[0017]

Two-dimensional code of the first invention
The conversion table address generation circuit sets the value of event A to x,
The value of the elephant B is y (x, y is a positive integer), and the value of x is 1
S (S is S + log₂Maximum integer satisfying S <P,
X + log for each integer up to P)₂y ≦
P, y + lo for each integer from 1 to S of y
g₂Each of the above-mentioned x and y in the range satisfying x ≦ P
The code word corresponding to each pair and the corresponding address
Address generation circuit for two-dimensional encoding table stored in memory
And the input x and y are each from 1 to the above S.
Match detection that becomes the active level when it matches the integer in
A plurality of ones that respectively output the output signal corresponding to the integer
Matching detector and input y is from 1 of x to S
X + log for each integer of₂satisfies y ≦ P
When the comparison result signal which becomes the active level is 1 of x
To each of the integers from S to S
Number of first comparators and the input x is from 1 of the y
Y + log for each integer up to S₂ x ≦ P
When it is satisfied, the comparison result signal that becomes active level
Corresponding to each integer from 1 to S in the above y
A plurality of second comparators, and one of the coincidence detection signals
Both of them are paired with the corresponding comparison result signal.
Acti when none of the active levels are included
Escape signal output that outputs a level escape signal
Raw part and each integer from 1 of x and y to S
An identification address that generates an identification address for identifying each
Inputting each identification address of the x
Input a predetermined bit of y and each identification address of y
Combine the predetermined bits of x that have been generated with the P + 1 bits
Address generator that outputs each as an address signal
And both the x and y sides of the coincidence detection signal
If there is a blank level, mask one of them and
One is output as is, otherwise both are output as is.
Priority control unit to control
The corresponding identification based on the active level coincidence detection signal
Multiplex that selects and outputs address signals including addresses
I have a lexa.

In the address generating circuit of the two-dimensional encoding table of the second invention, the value of event A is x and the value of event B is y.
(X and y are positive integers), and 1 to S of x (S is 2)
^(PS) -1 ≧ Q-log ₂ S, the maximum integer that satisfies S,
X + log ₂ y for each integer up to P and Q)
≤P, and 1 to R of y (R is 2 ^(QR) -1 ≥P-
2D for storing code words corresponding respectively to the respective groups of x and y in the range satisfying y + log ₂ x ≦ Q for each integer up to the maximum integer satisfying log ₂ R) An address generation circuit of an encoding table, wherein when input x matches an integer from 1 to S, and when input y is 1 to R
A plurality of coincidence detectors that output a coincidence detection signal that becomes an active level when they coincide with integers up to, and the input y is from 1 of x to S
For each integer up to, the comparison result signal that becomes an active level when x + log ₂ y ≦ P is satisfied
A plurality of first comparators that respectively output corresponding integers from 1 to S of the above, and input x is y + log ₂ x ≦ for each integer from 1 to R of y above.
A plurality of second comparators that respectively output a comparison result signal that becomes an active level when Q is satisfied in correspondence with each integer of 1 to R of y, and the second comparators that respectively correspond to the coincidence detection signals. An escape signal generating circuit which outputs an active level escape signal when none of the groups having an active level is included in the pair with the comparison result signal, and 1 from x to S and 1 from y. An identification address generating circuit for generating an identification address for identifying each integer up to R is provided, and each identification address of x and a predetermined bit of y input and each identification address of y are input. an address generator that combines a predetermined bit of x with at least the larger +1 bit of P and Q and outputs as an address signal;
When there is an active level on both the x side and the y side of the coincidence detection signal, one of them is masked and the other is output as it is, and otherwise, both are output as they are, A multiplexer for selecting and outputting an address signal including the corresponding identification address according to an active level match detection signal from the priority control section.

Further, a final block detecting section for outputting an active level final block detection signal when the final block of the encoding processing unit is detected, and a code word corresponding to the final block are stored in the two-dimensional encoding table. For generating an address signal for the final block code, and an address signal from the final block code address generator when the final block detection signal is at the active level, and from the multiplexer when the inactive level. An escape code address generator for generating an address signal for storing a code word corresponding to the escape signal in a two-dimensional encoding table, and the escape signal. When is an active level, the escape signal address The address signal from the parts, when the inactive level and has a structure provided with a selection circuit for selecting and outputting the address signal from the multiplexer.

[0020]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is based on P in "Claim 1".
= 6, S = 3, and the present invention is applied to the two-dimensional coding table of the code word distribution state corresponding to FIG. 7 described in "Prior Art".

From the distribution state of the code words in FIG. 7, the event A
It can be seen that the value x of B determines the number of valid range bits of the value B of B, and the value y of the event B determines the number of valid range bits of the value x of A. For example, when x = 1, codewords are distributed in a range that can be represented by 5 bits of y. Also, x = 2
When x = 3, it is distributed in the range that can be represented by 4 bits of y, and when x = 3, it is distributed in the range of 3 bits of y. On the other hand, when y = 1, x
The distribution area can be represented by 4 bits of x when y = 2, and 3 bits of x when y = 3. This is generally x + log ₂ y ≦ P, when x = 1 to 3, y = 1 to 3
Is a region that satisfies y + log ₂ x ≦ P and P = 6. Areas other than this area are escape code areas. The address corresponding to the code word is assigned in consideration of the uneven distribution of the code words.

Further, the above-mentioned values 1 to 3 of x and y are maximum integers satisfying S = log ₂ S <P and P = 6.

The distribution states of the code words are summarized as follows.

When x = 1, y is 32 words of 1 to 32, when x = 2, 16 words of y is 1 to 16 When x = 3, 8 words of y is 1 to 8 When y = 1 , X is 1 to 32, 32 words y = 2, x is 1 to 16 16 words, y = 23, x is 1 to 8 8 words Corresponds to all the code words in such a distribution state. To display addresses in correspondence with the x, y pairs in the above range,
(1 + log ₂ 32) bits for x = 1 to 3, y = 1
Similarly, since (1 + log ₂ 32) bits are required for ~ 3, (2 + log ₂ 3) for 1 to 3 of x and y.
2) bits, that is, P + 1 = 6 bits are required.

The code word having such a distribution state is defined as x,
The configuration of this embodiment for a two-dimensional coding table stored as a memory entropy code having an address corresponding to each set of y will be described.

In this embodiment, a plurality of coincidence detectors 1a to 1a which output a coincidence detection signal which becomes an active level when each of the input x and y coincides with an integer of 1 to 3 in correspondence with the integer. 1f and the input y are
x + log ₂ for each integer from 1 to 3 of x
Large and small comparators 2a to 2c that respectively output a comparison result signal that becomes an active level when y ≦ 6 is satisfied corresponding to each integer of 1 to 3 of x, and the input x is 1 to 3 of y. For each integer up to y + log ₂ x ≦
AND-type logic gate G3, and magnitude comparators 2d to 2f which respectively output a comparison result signal which becomes an active level when 6 is satisfied corresponding to each integer of 1 to 3 of y.
1 to G36 and a NOR type logic gate G37, and when none of the pairs of the coincidence signal and the corresponding comparison result signal include an active level, the active level escape signal ES is output. The escape signal generating section 3 for outputting and an identification address generating circuit 51 for generating an identification address ADi for identifying each integer of 1 to 3 of x and y are provided, and each identification address ADi of x (11, 101, 1001), the predetermined bits on the lower side of y input, and each identification address A of y
Di (01,001,0001) and a predetermined bit on the lower side of the input x are combined into 7 bits and output as an address signal, respectively, a NOR type logic gate G41 and an AND type AND gate. Logic gate G42-
A priority control unit 4 provided with G44, which masks the y side when both the x side and the y side of the coincidence detection signal have active levels and outputs the x side as it is, and otherwise outputs both as it is. A multiplexer 6 which selects and outputs an address signal AD including the corresponding identification address according to an active level coincidence detection signal from the priority control section 4, and an output signal of the multiplexer 6 according to an active level escape signal ES. The output stop circuit 7 stops the supply to the dimension encoding table.

A data format diagram of the address signal AD output by this embodiment is shown in FIG.

The address signal AD is composed of an identification address ADi for identifying 1 to 3 of x and y and a corresponding predetermined bit on the lower side of y and x. This identification address AD
i is the most significant bit representing the x side (1) and the y side (0),
1 to 3 bits (1,0) representing 1,2,3 following this
1,001) and. The predetermined bits on the lower side of y and x corresponding to the identification address ADi can identify 32 words when x and y are 1, 16 words when x and y are 3, and 8 words when they are 3. 5 bits, 4 bits, and 3 bits on the lower side of y and x, respectively.
The hardware for realizing this is the address generator 5.

The address signal AD output from the address generator 5 is selected by the multiplexer 6 according to the active level match detection signals of the match detectors 1a to 1f and output. At this time, both x and y may match an integer of 1 to 3, and at this time, one address signal AD cannot be accurately selected. Therefore, the match detection signal of the active level on the x side is the y side. The coincidence detection signal of is masked and the x side is prioritized. This is the priority control unit 4.

On the other hand, when x = 1 to 3, x + lo
When g ₂ y ≦ 6, and y = 1 to 3, y + log
A codeword corresponding to a set of x and y including x and y that do not satisfy ₂ x ≦ 6 is processed as an escape code. These are the magnitude comparators 2a to 2f and the escape signal generating circuit 3.

In this embodiment, since the coincidence detector, the size comparator, etc. need only the maximum number of integers S that satisfy S + log ₂ S <P, the circuit scale can be reduced.
Also, the capacity of the memory for the two-dimensional encoding table is (P +
1) The number of addresses in bits is sufficient. Furthermore, since the processing is performed directly by hardware, high-speed processing in real time is possible.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In the first embodiment, the distribution state of code words is x,
In contrast to the symmetry with respect to y, this second embodiment applies the present invention to the case of asymmetry. Figure 3
In the "claim 2", P = 6, Q = 5, S =
4, the circuit of the embodiment when R = 2 is shown.
The distribution state of the code words in the target two-dimensional coding table of this embodiment is as shown in FIG.

The target two-dimensional encoding table of this embodiment is 1 to 4 of x (A is 2 ^(6-S) -1≥5-log ₂ S).
X + log ₂ for each integer up to the maximum integer that satisfies
y ≦ 6, and 1 to 2 of y (2 is 2 ^(5-R) −1 ≧ 6-1 ⁾
y for each integer up to the maximum integer satisfying og ₂ R)
Codewords respectively corresponding to each set of x and y in the range satisfying + log ₂ x ≦ 5 are stored at corresponding addresses.

The distribution of code words for the above two-dimensional coding table is summarized as follows.

When x = 1, y is 32 words of 1 to 32, when x = 2, 16 words of y is 1 to 16 When x = 3, 8 words of y is 1 to 8 When x = 4 , Y is 1 to 4 4 words x = 1, x is 1 to 16 16 words y = 2 is x 1 to 8 8 words Corresponds to all the code words in such a distribution state. To display the address in correspondence with the set of x and y in the above range, the number of bits obtained by adding 1 to the larger P and Q, that is, 7 bits are required.

Next, the circuit configuration of this embodiment will be described.

In this embodiment, when the input x matches an integer of 1 to 4, and the input y is 1 to 2
A plurality of coincidence detectors 1a to 1c, 1d, 1e and 1g which respectively output the coincidence detection signal which becomes an active level when the integers up to are coincident with the integers, and the input y is 1 to 4 of x. X + for each integer up to
A plurality of first magnitude comparators 2a to 2c, 2 which respectively output a comparison result signal which becomes an active level when log ₂ y ≦ 6 is satisfied in correspondence with each integer of 1 to 4 of x.
g and the input result x are the active level comparison result signals corresponding to the integers 1 to 2 of y and y + log ₂ x ≦ 5. A plurality of second magnitude comparators 2 for outputting respectively
e and 2f, AND-type logic gates G31 to G36 and NOR-type logic gate G37, each of which has an active level among the pairs of the match detection signal and the corresponding comparison result signal. When not included, an escape signal generating circuit 3 that outputs an active level escape signal ES, and an identification address that generates an identification address ADi for identifying each integer of 1 to 4 of x and 1 to 2 of y The generator circuit 51a is provided x
Of the input address signal AD and a predetermined bit on the lower side of the input y, and each identification address of y and the predetermined bit on the lower side of the input x are combined into 7 bits.
Address generating section 5a for outputting as a NOR logic gate G46 and AND logic gates G42 to G45.
When there is an active level on both the x side and the y side of the coincidence detection signal, one of them is masked and the other is output as it is, otherwise both are output as it is. And this priority control unit 4
A multiplexer 6 which selects and outputs an address signal AD including the corresponding identification address by the active level coincidence detection signal from a, and an output signal of the multiplexer 6 by the active level escape signal ES to the two-dimensional encoding table. An output stop circuit 7 for stopping the supply is provided.

A data format diagram of the address signal AD output by this embodiment is shown in FIG.

In this embodiment, there are some differences in the configuration, contents of the address signal AD, etc. from the first embodiment, but since the basic operation and effect are the same as in the first embodiment, this is the case. The above description is omitted.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

In this embodiment, code words having a special meaning such as a code word for escape identification and a code word of EOB (End Of Block) are stored in a specific area of the two-dimensional coding table 100, and By adding each address generation unit, the encoded output can be obtained from the two-dimensional encoding table 100 through the same path.

In the case of the first embodiment, as shown in FIG. 2, 112 words are recorded in the encoding table memory, and if a table memory with an address of 7 bits is used, 16 words worth are stored. The area is unused. That is, the upper 5 bits of the address are (1000
In the case of 1), 4 words can be represented by the lower 2 bits, 2 words can be represented by the lower 1 bit when the upper 6 bits are (100001), 2 words can be represented by the lower 1 bit when the upper 6 bits are (100000), and further the upper 5 Bit is (00
In the case of 001), 2 words can be represented by the lower 2 bits, and when the upper 6 bits are (000000), 2 words can be represented by the lower 1 bit, for a total of 16 words.

Similarly, in the case of the second embodiment,
As shown in FIG. 5, 84 words are recorded in the encoding table memory, and if a table memory with an address of 7 bits is used, an area for 44 words is unused. That is, the upper 2 bits of the address are (1
In the case of 1), 32 words can be represented by the lower 5 bits, when the upper 5 bits of the address are (10001), 4 words can be represented by the lower 2 bits, and the upper 6 bits of the address are (0000
The total of 44 words is 2 words that can be represented by the lower 1 bit when it is 00) and 2 words that can be represented by the lower 1 bit when the upper 6 bits of the address are (000001).

A code word having a special meaning such as an escape identification code word (hereinafter referred to as an escape code word) or an EOB code word indicating the end of a coding unit is assigned to this unused area.

Next, the circuit configuration of this embodiment will be described.

In addition to the first and second embodiments shown in FIGS. 1 and 3, this embodiment outputs an active level final block detection signal EOB when the final block of the encoding processing unit is detected. EOB detecting unit 8 and EO for generating an address signal ADeob for storing the code word corresponding to the final block in the two-dimensional encoding table 100.
The B code address generation unit 10, the escape code address generation unit 10 for generating the address signal ADes for storing the code word corresponding to the escape signal ES in the two-dimensional encoding table 100, and the escape signal ES are at the active level. , The address signal ADes from the escape code address generation unit 10 and the address signal ADeob from the code address generation unit 9 when the final block detection signal EOB is at the active level, the escape signal ES and the final block detection signal EOB. When both are at the inactive level, a selection circuit 11 for selecting and outputting the address signal AD from the multiplexer 6 is provided.

For example, in the first and second embodiments, the escape code word "000" is assigned to the unused area (0000010) of the two-dimensional encoding table 100.
001 ”is stored, and similarly, the unused area (000000
11) The EOB code word "10" is stored in the address. The escape code address generation unit 10 is a circuit that outputs an address “0000010” that stores this escape code word, and the EOB code address generation unit 9 is E
This is a circuit that outputs an address "0000011" that stores an OB code word.

When the escape signal ES is at the active level, the address signal AD of the address "0000010" output from the escape code address generator 10 is output.
es is selected by the selection circuit 11 and output. As a result, the escape code word “00001” can be read from the two-dimensional encoding table 100. When the final block detection signal EOB is at the active level,
The address signal ADeob of the address “0000011” output from the EOB code address generation unit 9 is selected by the selection circuit 11 and output. As a result, the EOB codeword “10” can be read from the two-dimensional encoding table 100. Further, when the escape signal ES and the final block detection signal EOB are at the inactive level, the address signal AD from the multiplexer 6 described in the first embodiment or the second embodiment is output from the selection circuit 11.

In the third embodiment, by assigning a code word having a special meaning to the address of the unused area of the address space in the first or second embodiment, the memory of the two-dimensional encoding table 100 is further increased. There is an advantage that the area can be effectively used and the amount of hardware for a code word having a special meaning can be minimized. Further, since the addresses of these encodings can be generated through the same route as in the first or second embodiment, there is an advantage that the timings of these encodings can be the same.

[0053]

As described above, according to the present invention, the necessary and sufficient number of coincidence detectors and comparators derived from the distribution state of codes and the address signals of the necessary and sufficient number of addresses similarly derived are provided. And a means for generating an output signal of the coincidence detector, and an escape signal is generated by the output signals of the coincidence detector and the comparator. Since the memory capacity of the table can be reduced and the processing can be performed directly by hardware, there is an effect that high-speed processing in real time can be performed.

Further, by generating and selecting and outputting an address signal for storing a specific code word such as an escape code word or an EOB code word in an empty area of the two-dimensional coding table, the two-dimensional coding table is generated. Since the memory area can be further effectively used and a specific code word can be output through the same path, there is an effect that the amount of hardware for these code words can be minimized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a data format diagram of an output address signal of the embodiment of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a distribution diagram of code words of a two-dimensional encoding table which is a target of the embodiment shown in FIG.

5 is a data format diagram of an output address signal of the embodiment shown in FIG.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a distribution state diagram of target codewords for explaining an address generation circuit of a conventional two-dimensional encoding table.

[Explanation of symbols]

 1a to 1g Match detector 2a to 2g Large / small comparator 3 Escape signal generating circuit 4, 4a Priority control circuit 5, 5a Address generating unit 6 Multiplexer 7 Output stop circuit 8 EOB detecting unit 9 EOB code address generating unit 10 Escape code Address generation unit 11 selection circuit 100 two-dimensional encoding table 51, 51a identification address generation circuit G31 to G37, G41 to G46 logic gate

Claims (5)

[Claims] 1. The value of event A is x, and the value of event B is y (x,
y is a positive integer, and 1 to S of x (S is S + lo)
g ₂ S <P is a maximum integer, P is a positive integer, x + log ₂ y ≦ P for each integer, and y + log ₂ x ≦ P for each integer from 1 to S of y above. An address generation circuit of a two-dimensional encoding table for storing codewords respectively corresponding to the respective sets of x and y in a satisfying range at corresponding addresses, wherein each of x and y inputted is from 1 to S. To a plurality of coincidence detectors that output a coincidence detection signal that becomes an active level when they coincide with an integer of up to, and the input y is for each integer from 1 to S of the above x. a plurality of first comparators that respectively output a comparison result signal that becomes an active level when x + log ₂ y ≦ P is satisfied, corresponding to each integer from 1 to S of x;
When the input x satisfies y + log ₂ x ≦ P for each integer from 1 to S of the above y, the comparison result signal which becomes an active level corresponds to each integer from 1 to the above S of y. Of the plurality of second comparators that respectively output each of the coincidence detection signals and the comparison result signal corresponding to each of the coincidence detection signals do not include any one of the active level, the active level escape signal. And an identification address generation circuit for generating an identification address for identifying each integer from 1 to S of x and y and an escape signal generator for outputting y Predetermined bits of x, and each identification address of y and the input predetermined bits of x are combined with the P + 1 bit and output as address signals. When there is an active level on both the dress generation section and the x side and the y side of the coincidence detection signal, one of them is masked and the other is output as it is, and otherwise, both are output as they are. An address generation circuit for a two-dimensional encoding table, comprising a control unit and a multiplexer for selecting and outputting an address signal including the corresponding identification address in response to an active level coincidence detection signal from the priority control unit. . 2. The value of event A is x, the value of event B is y (x,
y is a positive integer, and x is 1 to S (S is 2 ^(PS)
X + log ₂ y ≦ P for each integer up to the maximum integer satisfying −1 ≧ Q−log ₂ S, P and Q are positive integers, and 1 to R of y (R is 2 ^(QR) − 1 ≧ P-log ₂
Y + lo for each integer up to the maximum integer that satisfies R)
An address generation circuit of a two-dimensional encoding table, which stores codewords corresponding respectively to the respective pairs of x and y in the range satisfying g ₂ x ≦ Q at corresponding addresses, wherein the input x is A plurality of match detections that respectively output a match detection signal that becomes an active level when the input y matches the integers from 1 to S and when the input y matches the integers from 1 to R. And a comparison result signal that becomes an active level when the input y satisfies x + log ₂ y ≦ P for each integer from 1 to S of the above x, and each integer from 1 to the above S of the above x A plurality of first comparators which respectively output in correspondence with the above, and the input x is from 1 of the y to the R
For each integer up to y + log ₂ x ≦ Q, the comparison result signal that becomes the active level is y
Of the plurality of second comparators respectively corresponding to the respective integers from 1 to R and the comparison result signal corresponding to each of the coincidence detection signals, the one having the active level is selected. An escape signal generation circuit that outputs an active level escape signal when no set is included, and an identification address for identifying each integer from 1 of x to S and 1 of R to y And an identification address generating circuit for generating each identification address of x, a predetermined bit of y input, and y
An address generator for combining each identification address and the input predetermined bit of x with at least the larger one of P and Q + 1 and outputting as an address signal, and an x-side and a y-side of the coincidence detection signal. When both have active levels, one of them is masked and the other is output as it is. Otherwise, both are output as is. An address generation circuit for a two-dimensional encoding table, comprising: a multiplexer that selects and outputs an address signal including the corresponding identification address according to a signal. 3. The address generation circuit of the two-dimensional encoding table according to claim 1, further comprising an output stop circuit for stopping the supply of the output signal of the multiplexer to the two-dimensional encoding table by the escape signal of the active level. . 4. A final block detector that outputs an active level final block detection signal when a final block of an encoding processing unit is detected, and a code word corresponding to the final block is stored in a two-dimensional encoding table. For generating an address signal for the final block code, and an address signal from the final block code address generator when the final block detection signal is at the active level, and from the multiplexer when the inactive level. The address generation circuit of the two-dimensional encoding table according to claim 1, further comprising a selection circuit that selects and outputs the address signal. 5. An escape code address generator that generates an address signal for storing a code word corresponding to an escape signal in a two-dimensional encoding table, and the escape signal address when the escape signal is at an active level. 3. A selection circuit for selecting and outputting the address signal from the multiplexer when the address signal from the generator is at the inactive level.
Address generation circuit of the described two-dimensional encoding table.