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JPH06291230A - Manufacture of composite semiconductor device - Google Patents

Manufacture of composite semiconductor device

Info

Publication number
JPH06291230A
JPH06291230A JP9830493A JP9830493A JPH06291230A JP H06291230 A JPH06291230 A JP H06291230A JP 9830493 A JP9830493 A JP 9830493A JP 9830493 A JP9830493 A JP 9830493A JP H06291230 A JPH06291230 A JP H06291230A
Authority
JP
Japan
Prior art keywords
terminals
semiconductor device
composite semiconductor
soldered
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9830493A
Other languages
Japanese (ja)
Other versions
JP3258428B2 (en
Inventor
Eigo Fukuda
永吾 福田
Saburo Mori
三郎 森
Takeshi Kamiyuu
毅 上猶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Inter Electronics Corp
Original Assignee
Nihon Inter Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nihon Inter Electronics Corp filed Critical Nihon Inter Electronics Corp
Priority to JP09830493A priority Critical patent/JP3258428B2/en
Publication of JPH06291230A publication Critical patent/JPH06291230A/en
Application granted granted Critical
Publication of JP3258428B2 publication Critical patent/JP3258428B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide a method of manufacturing a composite semiconductor device wherein main terminals and signal terminals are accurately positioned even if they are increased in number and which can be easily assembled. CONSTITUTION:The intermediate spots of main terminals 3 and 4 and a signal terminal 5 are previously soldered to a printed board 16, whereby a special positioning jig can be dispensed with, and the lower ends of them can be precisely positioned to a chip mounting board 9. Therefore, a composite semiconductor device of this constitution is not increased in assembling man-hours even if it is enhanced in the number of terminals.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複合半導体装置の製造
方法に関し、特に外部に導出される端子の位置決め処理
を改良した複合半導体装置の製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a composite semiconductor device, and more particularly to a method for manufacturing a composite semiconductor device with improved positioning processing of terminals led to the outside.

【0002】[0002]

【従来の技術】この種の複合半導体装置の図5及び図6
に示す。これらの図において、複合半導体装置1の内部
には図示しないが、スイッチング素子の半導体ペレット
が6個が樹脂封止部2により封入されている。そして、
この樹脂封止部2から複合半導体装置1の外部に、直流
側主端子3及び交流側主端子4と、各スイッチング素子
の信号端子5が全部で6組外部に導出されている。な
お、図中6は放熱板、7は放熱板6の両端に明けられた
取付孔、8は放熱板6上に固着された両端開口の絶縁ケ
ースである。
5 and 6 of a composite semiconductor device of this type.
Shown in. In these figures, although not shown inside the composite semiconductor device 1, six semiconductor pellets of the switching element are encapsulated by the resin encapsulation portion 2. And
A total of 6 sets of DC side main terminals 3 and AC side main terminals 4 and signal terminals 5 of each switching element are led out from the resin sealing portion 2 to the outside of the composite semiconductor device 1. In the figure, 6 is a heat dissipation plate, 7 is a mounting hole opened at both ends of the heat dissipation plate 6, and 8 is an insulating case fixed on the heat dissipation plate 6 and having both openings.

【0003】次に、上記のように構成の複合半導体装置
の内部構造を図7に示す。図において、放熱板6上にチ
ップ搭載基板9がはんだ付けされている。このチップ搭
載基板9は、セラミック若しくは窒化アルミ板の両面に
導体層10がそれぞれ形成されている。そして、その下
面は放熱板6にはんだ付けされ、その上面には所定回路
の導体パターン11が形成され、該パターン11上に半
導体チップ12がはんだ付けされている。次に、半導体
チップ12の上部電極と導体パターン11間をワイヤボ
ンディングする(図示省略)。次に、放熱板6上にチッ
プ搭載基板9と直流側主端子3、交流側主端子4及び信
号端子5とを図示しない位置決め治具により所定の位置
に位置決めしてはんだ付けする。次に、両端開口の絶縁
ケース13を被せ、そのケース13の内側にゲル状コー
ト剤14及び封止樹脂15を順次充填し複合半導体装置
1を完成する。
Next, FIG. 7 shows the internal structure of the composite semiconductor device having the above-mentioned structure. In the figure, the chip mounting board 9 is soldered onto the heat sink 6. The chip mounting board 9 has conductor layers 10 formed on both surfaces of a ceramic or aluminum nitride plate. The lower surface is soldered to the heat dissipation plate 6, a conductor pattern 11 of a predetermined circuit is formed on the upper surface, and the semiconductor chip 12 is soldered on the pattern 11. Next, wire bonding is performed between the upper electrode of the semiconductor chip 12 and the conductor pattern 11 (not shown). Next, the chip mounting board 9, the DC side main terminal 3, the AC side main terminal 4 and the signal terminal 5 are positioned and soldered on the heat sink 6 at predetermined positions by a positioning jig (not shown). Next, the insulating case 13 having openings at both ends is covered, and the gel coating agent 14 and the sealing resin 15 are sequentially filled inside the case 13 to complete the composite semiconductor device 1.

【0004】[0004]

【発明が解決しようとする課題】ところで、上記のよう
な従来の複合半導体装置の製造方法では、直流側主端子
3,交流側主端子4及び信号端子5の数量が多くなった
場合、精度良く治具で位置決めすることも難しく、ま
た、組立工数が多くなるという解決すべき課題があっ
た。
By the way, in the conventional method of manufacturing a composite semiconductor device as described above, when the numbers of the DC side main terminals 3, the AC side main terminals 4 and the signal terminals 5 are increased, the accuracy is improved. It is difficult to position with a jig, and there is a problem to be solved that the number of assembling steps increases.

【0005】[0005]

【発明の目的】本発明は、上記のような課題を解決する
ためになされたもので、両主端子及び信号端子の数量が
多くなっても、それら各端子の位置決めが精度良くで
き、かつ、組立も容易な複合半導体装置の製造方法を提
供することを目的とするものである。
SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and even if the number of both main terminals and signal terminals is large, the positioning of each terminal can be accurately performed, and It is an object of the present invention to provide a method for manufacturing a composite semiconductor device which is easy to assemble.

【0006】[0006]

【問題点を解決するための手段】本発明の複合半導体装
置の製造方法は、放熱板上に絶縁物を介して半導体チッ
プ、主端子及び信号端子がはんだ付けされ、該放熱板の
外周部上に両端開口の絶縁ケースを配置し、前記半導体
チップ、主端子および信号端子の下部が樹脂封止される
複合半導体装置の製造方法において、前記主端子及び信
号端子を前記放熱板上にはんだ付けする前に、それら端
子の中間部を前記プリント基板にあらかじめはんだ付け
し、次いで、該プリント基板とそれら端子からなる組立
体を前記放熱板上に搭載してそれら各端子の下端をはん
だ付けすることを特徴とするものである。
According to a method of manufacturing a composite semiconductor device of the present invention, a semiconductor chip, a main terminal and a signal terminal are soldered on an radiating plate via an insulator, and the radiating plate is provided on an outer peripheral portion of the radiating plate. In a method for manufacturing a composite semiconductor device, in which an insulating case having openings at both ends is arranged, and the lower portions of the semiconductor chip, main terminals and signal terminals are resin-sealed, the main terminals and signal terminals are soldered onto the heat sink. Previously, the intermediate parts of the terminals are previously soldered to the printed circuit board, and then the assembly of the printed circuit board and the terminals is mounted on the heat dissipation plate, and the lower ends of the terminals are soldered. It is a feature.

【0007】[0007]

【作用】本発明の複合半導体装置の製造方法は、両主端
子及び信号端子の中間部をプリント基板にあらかじめは
んだ付けしておくために、位置決めのための特別の治具
を必要とせず、それら各端子の下端をはんだ付けすべき
放熱板上に精度良く位置決めすることができる。このた
め、端子の数量が多くなっても組立工数が増加すること
もない。
The method of manufacturing a composite semiconductor device of the present invention does not require a special jig for positioning because the intermediate portions of both the main terminals and the signal terminals are pre-soldered on the printed circuit board. The lower ends of the terminals can be accurately positioned on the heat sink to be soldered. Therefore, the number of assembling steps does not increase even if the number of terminals increases.

【0008】[0008]

【実施例】以下に、本発明の実施例を図を参照して説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0009】図1は本発明の複合半導体装置の製造方法
を説明するための正面図、図2はその平面図である。こ
れらの図において、板厚約2mmのプリント基板16に
は、信号端子用貫通孔17a及び主端子用貫通孔18a
が形成されている。さらにこれらの貫通孔17a,18
aに近接して独立した小孔17b,18bが設けられて
いる。また、これらの貫通孔17a,18a及び小孔1
7b,18bを取り囲むように所定の回路形成のための
導体パターン19が形成されている。なお、主端子3と
同電位となる信号端子5は、導体パターン19により接
続される。次に、上記の各部品の組立順序を説明する。
まず、図3に示すように、主端子3及び信号端子5a,
5bをプリント基板16の主端子用貫通孔18a及び信
号端子用貫通孔17aにそれぞれ挿通する。信号端子5
a,5bのうち、信号端子5aは、主端子3と同電位と
なるので、プリント基板16のみに導体パターン19を
介して接続すれば良い。
FIG. 1 is a front view for explaining a method of manufacturing a composite semiconductor device according to the present invention, and FIG. 2 is a plan view thereof. In these drawings, a through hole 17a for a signal terminal and a through hole 18a for a main terminal are provided on a printed circuit board 16 having a plate thickness of about 2 mm.
Are formed. Further, these through holes 17a, 18
Independent small holes 17b and 18b are provided near a. Also, these through holes 17a, 18a and the small hole 1
A conductor pattern 19 for forming a predetermined circuit is formed so as to surround 7b and 18b. The signal terminal 5 having the same potential as the main terminal 3 is connected by the conductor pattern 19. Next, the order of assembling each of the above parts will be described.
First, as shown in FIG. 3, the main terminal 3 and the signal terminals 5a,
5b is inserted into each of the main terminal through hole 18a and the signal terminal through hole 17a of the printed circuit board 16. Signal terminal 5
Of the a and 5b, the signal terminal 5a has the same potential as that of the main terminal 3, so that only the printed board 16 needs to be connected via the conductor pattern 19.

【0010】上記の各端子の形状を図4に基づいて説明
する。すなわち、図4は主端子3の形状を示している
が、この主端子3には基部31から枝分かれした分岐部
32が一体的に形成されている。なお、この分岐部32
は、他の信号端子5にも上記と同様に形成されている。
また、基部31の中央よりやや上部に該基部31の下方
に向かって次第に表面からの突出量が多くなるようにし
た膨出部34が形成されている。さらに、基部31の一
端には折曲脚部33が形成されている。次に、上記のよ
うに構成の各端子とプリント基板を用いて本発明の組立
順序を説明する。
The shape of each terminal will be described with reference to FIG. That is, although FIG. 4 shows the shape of the main terminal 3, the main terminal 3 is integrally formed with a branch portion 32 branched from the base portion 31. In addition, this branching unit 32
Are formed on the other signal terminals 5 in the same manner as above.
In addition, a bulge 34 is formed slightly above the center of the base 31 so that the amount of protrusion from the surface gradually increases toward the bottom of the base 31. Further, a bent leg portion 33 is formed at one end of the base portion 31. Next, the assembling order of the present invention will be described using each terminal and the printed circuit board configured as described above.

【0011】まず、プリント基板16に対して、両主端
子3,4及び信号端子5を挿通する。すなわち、プリン
ト基板16の裏面側から両主端子3,4及び信号端子5
の先端部を挿通する。この場合にそれぞれ両主端子3,
4及び信号端子5には、分岐部32が形成されているの
で、この分岐部32の先端部も透孔17b,18bに挿
通する。これらの挿通が完了すると、それぞれの基部3
1に形成した膨出部34がくさび形状となっているの
で、該膨出部32がそれぞれの貫通孔17a,18a内
に侵入して仮固定の役目を果たす。従って、はんだ付け
前に、それらの端子3,4,5がプリント基板16から
脱落するようなことがない。
First, the main terminals 3 and 4 and the signal terminal 5 are inserted into the printed circuit board 16. That is, from the rear surface side of the printed circuit board 16, both main terminals 3 and 4 and the signal terminal 5
Insert the tip of the. In this case, both main terminals 3,
Since the branch portion 32 is formed in the signal line 4 and the signal terminal 5, the tip portion of the branch portion 32 is also inserted into the through holes 17b and 18b. When these insertions are completed, each base 3
Since the bulging portion 34 formed in No. 1 has a wedge shape, the bulging portion 32 enters the respective through holes 17a, 18a and serves as a temporary fixing. Therefore, the terminals 3, 4, and 5 do not fall off the printed circuit board 16 before soldering.

【0012】こうして、プリント基板16に挿入された
各端子3,4,5は、図4に示すように導体パターン1
9にはんだ20よりはんだ付けされる。一方、半導体チ
ップ12は、従来と同様にあらかじめチップ搭載基板9
の所定位置にはんだ付けされ、さらに半導体チップ12
の上面の電極と導体パターン10間は図示しないが、ワ
イヤボンディングで配線しておく。次いで、プリント基
板16と各端子3,4,5の組立体を図1に示すよう
に、複数の位置決めピン21により両主端子3,4の折
曲脚部33及び一の信号端子5の折曲脚部53をチップ
搭載基板9の所定位置に載せる。以上の準備をした後、
放熱板6を図示しない熱板上に載せて加熱し、放熱板6
とチップ搭載基板9との間、該チップ搭載基板9と各端
子3,4,5の折曲脚部33,53との間をはんだ付け
する。なお、各はんだ付け工程で用いるはんだはそれぞ
れの用途に応じて異なる溶融温度のものを使用すること
は勿論である。また、上記の工程以降の工程は従来と同
様であるため、その詳しい説明は省略する。
Thus, the terminals 3, 4, 5 inserted into the printed circuit board 16 have the conductor pattern 1 as shown in FIG.
9 is soldered with solder 20. On the other hand, the semiconductor chip 12 is previously mounted on the chip mounting board 9 in the same manner as the conventional one.
Is soldered to the predetermined position of the semiconductor chip 12
Although not shown, the electrodes on the upper surface of the and the conductor pattern 10 are wired by wire bonding. Next, as shown in FIG. 1, the assembly of the printed circuit board 16 and the terminals 3, 4 and 5 is bent by a plurality of positioning pins 21 so that the bent leg portions 33 of both main terminals 3 and 4 and one signal terminal 5 are bent. The bent leg portion 53 is placed at a predetermined position on the chip mounting board 9. After making the above preparations,
The heat radiating plate 6 is placed on a heat plate (not shown) to heat the heat radiating plate 6.
And the chip mounting board 9 and the chip mounting board 9 and the bent leg portions 33, 53 of the terminals 3, 4, 5 are soldered. Needless to say, the solder used in each soldering process has a different melting temperature depending on the application. Further, since the steps after the above-mentioned steps are the same as the conventional ones, detailed description thereof will be omitted.

【0013】[0013]

【発明の効果】以上のように、本発明の複合半導体装置
の製造方法によれば、各端子の下端を放熱板にはんだ付
けする以前に、その中間部をプリント基板にはんだ付け
するようにしたので、概略以下のような効果を奏する。 (1)各端子のチップ搭載基板への位置合わせを精度良
く、かつ、容易に行なうことができる。 (2)多量の端子を使用する複合半導体装置であっても
あらかじめプリント基板にはんだ固着しておくために、
その状態で既に位置決めがされてしまうので、特別の治
具を使用せずに、かつ、組立工数を増加させることなく
組み立てることができる。 (3)主端子と同電位となる信号端子は、プリント基板
にはんだ付けするだけで良く、信号端子自体を短くする
ことができ、材料取りを有利にする等の利点がある。
As described above, according to the method for manufacturing the composite semiconductor device of the present invention, the intermediate portion of each terminal is soldered to the printed board before the lower end of each terminal is soldered to the heat sink. Therefore, the following effects are obtained. (1) It is possible to accurately and easily align the terminals with the chip mounting board. (2) Even in the case of a composite semiconductor device that uses a large number of terminals, in order to solder it to the printed circuit board in advance,
Since the positioning is already performed in that state, it is possible to assemble without using a special jig and without increasing the number of assembling steps. (3) The signal terminal having the same potential as the main terminal may be simply soldered to the printed circuit board, and the signal terminal itself can be shortened, which has the advantage of facilitating material removal.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の複合半導体装置の製造方法を説明する
ための部分正面図である。
FIG. 1 is a partial front view for explaining a method for manufacturing a composite semiconductor device of the present invention.

【図2】上記製造方法に使用するプリント基板の平面図
である。
FIG. 2 is a plan view of a printed circuit board used in the above manufacturing method.

【図3】上記製造方法における各端子のプリント基板へ
の差し込み状態を示す断面図である。
FIG. 3 is a cross-sectional view showing a state in which each terminal is inserted into a printed circuit board in the above manufacturing method.

【図4】上記のプリント基板への差し込み状態の部分拡
大断面図である。
FIG. 4 is a partially enlarged cross-sectional view of a state in which the printed board is inserted.

【図5】この種の複合半導体装置の外部へ導出される端
子の数量の多寡を説明するための平面図である。
FIG. 5 is a plan view for explaining how many terminals are led out of a composite semiconductor device of this type.

【図6】上記図5と同様の横断面図である。6 is a cross-sectional view similar to FIG. 5 described above.

【図7】上記複合半導体装置の内部構造を示す断面図で
ある。
FIG. 7 is a cross-sectional view showing an internal structure of the composite semiconductor device.

【符号の説明】[Explanation of symbols]

1 複合半導体装置 2 樹脂封止部 3 直流側主端子 4 交流側主端子 5 信号端子 6 放熱板 7 取付孔 8 絶縁ケース 9 チップ搭載基板 10 導体層 11 導体パターン 12 半導体チップ 13 絶縁ケース 14 ゲル状コート剤 15 樹脂封止部 16 プリント基板 17a 信号端子用貫通孔 17b 透孔 18a 主端子用貫通孔 18b 透孔 19 導体パターン 20 はんだ 21 位置決め用ピン 31 基部 32 分岐部 33,53 折曲脚部 34 膨出部 DESCRIPTION OF SYMBOLS 1 Composite semiconductor device 2 Resin sealing part 3 DC side main terminal 4 AC side main terminal 5 Signal terminal 6 Heat sink 7 Mounting hole 8 Insulation case 9 Chip mounting board 10 Conductor layer 11 Conductor pattern 12 Semiconductor chip 13 Insulation case 14 Gel-like Coating agent 15 Resin sealing part 16 Printed circuit board 17a Through hole for signal terminal 17b Through hole 18a Through hole for main terminal 18b Through hole 19 Conductor pattern 20 Solder 21 Positioning pin 31 Base part 32 Branch part 33, 53 Bending leg part 34 Bulge

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 放熱板上に絶縁物を介して半導体チッ
プ、主端子及び信号端子がはんだ付けされ、該放熱板の
外周部上に両端開口の絶縁ケースを配置し、前記半導体
チップ、主端子および信号端子の下部が樹脂封止される
複合半導体装置の製造方法において、前記主端子及び信
号端子を前記放熱板上にはんだ付けする前に、それら端
子の中間部を前記プリント基板にあらかじめはんだ付け
し、次いで、該プリント基板とそれら端子からなる組立
体を前記放熱板上に搭載してそれら各端子の下端をはん
だ付けすることを特徴とする複合半導体装置の製造方
法。
1. A semiconductor chip, a main terminal and a signal terminal are soldered on a heat dissipation plate via an insulator, and an insulating case having openings at both ends is arranged on an outer peripheral portion of the heat dissipation plate. And a method for manufacturing a composite semiconductor device in which the lower portion of the signal terminal is resin-sealed, before the main terminal and the signal terminal are soldered on the heat sink, an intermediate portion of these terminals is previously soldered to the printed board. Then, the assembly of the printed board and the terminals is mounted on the heat dissipation plate, and the lower ends of the terminals are soldered.
JP09830493A 1993-04-02 1993-04-02 Method for manufacturing composite semiconductor device Expired - Fee Related JP3258428B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09830493A JP3258428B2 (en) 1993-04-02 1993-04-02 Method for manufacturing composite semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09830493A JP3258428B2 (en) 1993-04-02 1993-04-02 Method for manufacturing composite semiconductor device

Publications (2)

Publication Number Publication Date
JPH06291230A true JPH06291230A (en) 1994-10-18
JP3258428B2 JP3258428B2 (en) 2002-02-18

Family

ID=14216192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09830493A Expired - Fee Related JP3258428B2 (en) 1993-04-02 1993-04-02 Method for manufacturing composite semiconductor device

Country Status (1)

Country Link
JP (1) JP3258428B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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