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JPH06283370A - Layered capacitor - Google Patents

Layered capacitor

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Publication number
JPH06283370A
JPH06283370A JP5071582A JP7158293A JPH06283370A JP H06283370 A JPH06283370 A JP H06283370A JP 5071582 A JP5071582 A JP 5071582A JP 7158293 A JP7158293 A JP 7158293A JP H06283370 A JPH06283370 A JP H06283370A
Authority
JP
Japan
Prior art keywords
electrode
capacitor
electrodes
floating
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5071582A
Other languages
Japanese (ja)
Other versions
JP3064732B2 (en
Inventor
Eiji Yamada
英司 山田
Takako Hashimoto
貴子 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP5071582A priority Critical patent/JP3064732B2/en
Publication of JPH06283370A publication Critical patent/JPH06283370A/en
Application granted granted Critical
Publication of JP3064732B2 publication Critical patent/JP3064732B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To relax a field concentration between a capacitor electrode and an external electrode and restrict creeping discharge from a capacitor surface, by providing a floating electrode which is inherent in an insulator outer layer in an electrically non-contact state in either electrode. CONSTITUTION:A layered type capacitor 1 in which an external electrode 3 is installed to the end is layered with a capacitor 4 and an insulator outside layer 5 which protects the capacitor 4 in the thickness direction in structure. A frame-shaped floating electrode 20, which is not electrically connected to any electrode inside the insulator outside layer 5. The floating electrode 20 is installed virtually at a position between an end part 3a of the outside electrode 3 and an end part 22a of a capacitor electrode 22. The capacitor 4 is alternately layered with capacitor electrodes 22 to 24 and dielectric layers 7 to 9. Frame-shaped floating electrodes 27 and 28 are installed inside the dielectric layers 7 and 8. This construction makes it possible to relax a field concentration between the capacitor electrodes and the outside electrodes and provide a small-sized laminated type capacitor which is excellent in voltage resistant performance without increasing the thickness of the insulator outside layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、耐電圧性に優れた積層
型コンデンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated capacitor having excellent withstand voltage.

【0002】[0002]

【従来の技術と課題】従来より、積層型コンデンサの耐
電圧性能を向上させるために種々の工夫がなされてき
た。例えば、容量電極間の誘電体層の厚さをアップさせ
て耐電圧性能を向上させるものが提案されている。しか
しながら、高耐電圧コンデンサにするためには、外形寸
法が大きくなるという問題があった。
2. Description of the Related Art Conventionally, various measures have been taken to improve the withstand voltage performance of multilayer capacitors. For example, it has been proposed to improve the withstand voltage performance by increasing the thickness of the dielectric layer between the capacitance electrodes. However, there has been a problem that the external dimensions are increased in order to obtain a high withstand voltage capacitor.

【0003】また、これとは別に特願平1−22042
1号公報及び特願平1−220422号公報記載のもの
が知られている。この積層型コンデンサは、容量電極間
の誘電体層中に、いずれの電極にも接続されていない浮
き電極を設けたものであって、容量電極端部での電界集
中を緩和することにより、高耐電圧化を図っている。し
かしながら、容量電極間の絶縁破壊電圧より、コンデン
サ表面の沿面放電電圧の方が低いため、沿面放電が先に
発生して浮き電極の効果が充分に発揮できないという問
題があった。
In addition to this, Japanese Patent Application No. 1-20442
The ones described in Japanese Patent Application No. 1 and Japanese Patent Application No. 1-220422 are known. This multilayer capacitor has floating electrodes that are not connected to any of the electrodes in the dielectric layer between the capacitance electrodes, and by relaxing the electric field concentration at the ends of the capacitance electrodes, Withstand voltage. However, since the creeping discharge voltage on the surface of the capacitor is lower than the dielectric breakdown voltage between the capacitance electrodes, there is a problem that the creeping discharge occurs first and the effect of the floating electrode cannot be fully exerted.

【0004】そこで、本発明の課題は、耐電圧性能が優
れた小型の積層型コンデンサを提供することにある。
Therefore, an object of the present invention is to provide a small-sized multilayer capacitor having excellent withstand voltage performance.

【0005】[0005]

【課題を解決するための手段と作用】以上の課題を解決
するため、本発明に係る積層型コンデンサは、(a)複
数の容量電極と、(b)前記容量電極のそれぞれと交互
に積層してコンデンサ部を構成する誘電体層と、(c)
前記容量電極と前記誘電体層を交互に積層したコンデン
サ部を保護するための絶縁体外層と、(d)前記容量電
極に電気的に接続された複数の外部電極と、(e)いず
れの電極にも電気的に接続されない状態で前記絶縁体外
層に内在した浮き電極と、を備えたことを特徴とする。
In order to solve the above-mentioned problems, a multilayer capacitor according to the present invention has (a) a plurality of capacitor electrodes and (b) alternately stacked capacitor electrodes. A dielectric layer that forms a capacitor part by (c)
An insulator outer layer for protecting a capacitor part in which the capacitance electrodes and the dielectric layers are alternately laminated, (d) a plurality of external electrodes electrically connected to the capacitance electrodes, and (e) any of the electrodes And a floating electrode that is internally provided in the outer layer of the insulator without being electrically connected.

【0006】以上の構成により、絶縁体外層に内在した
浮き電極により、コンデンサ部の最も外側に配設された
容量電極と外部電極間の電界集中が緩和され、コンデン
サ表面の沿面放電が発生しにくくなる。特に、容量電極
の端部と外部電極の端部との間での電界強度が強いた
め、浮き電極を容量電極の端部と外部電極の端部との略
間の位置に設けることにより、容量電極と外部電極間の
電界集中の緩和効果がよりアップする。
With the above structure, the floating electrode provided in the outer layer of the insulator relieves the electric field concentration between the capacitor electrode and the external electrode disposed on the outermost side of the capacitor portion, and the creeping discharge on the surface of the capacitor hardly occurs. Become. In particular, since the electric field strength between the end of the capacitance electrode and the end of the external electrode is high, the floating electrode is provided at a position approximately between the end of the capacitance electrode and the end of the external electrode, The effect of alleviating the electric field concentration between the electrode and the external electrode is further improved.

【0007】さらに、本発明に係る積層型コンデンサ
は、いずれの電極にも電気的に接続されない状態で、容
量電極間の誘電体層に内在した浮き電極を備えたことを
特徴とする。以上の構成により、容量電極相互間の電界
集中も緩和されるため、コンデンサの絶縁破壊がさらに
発生しにくくなる。
Further, the multilayer capacitor according to the present invention is characterized in that it is provided with a floating electrode which is included in the dielectric layer between the capacitance electrodes in a state where it is not electrically connected to any of the electrodes. With the above configuration, the electric field concentration between the capacitance electrodes is alleviated, so that the dielectric breakdown of the capacitor is further unlikely to occur.

【0008】[0008]

【実施例】以下、本発明に係る積層型コンデンサの実施
例を添付図面を参照して説明する。 [第1実施例、図1〜図10]第1実施例の積層型コン
デンサは、絶縁体外層及び誘電体層にそれぞれ浮き電極
を1層内在させたものである。
Embodiments of the multilayer capacitor according to the present invention will be described below with reference to the accompanying drawings. [First Embodiment, FIGS. 1 to 10] In the multilayer capacitor of the first embodiment, one floating electrode is provided in each of the insulating outer layer and the dielectric layer.

【0009】図1ないし図3に示すように、積層型コン
デンサ1は両端部に外部電極2,3を備え、コンデンサ
部4とこのコンデンサ部4を保護するための絶縁体外層
5,6を厚み方向に積み重ねて焼成した一体構造をして
いる。絶縁体外層5の内部には、図4に示すように、い
ずれの電極にも電気的に接続されない額縁形状の浮き電
極20が設けられている。以下、いずれの電極にも電気
的に接続されない電極を浮き電極とする。同様に絶縁体
外層6の内部にも、額縁形状の浮き電極21が設けられ
ている。額縁形状とする理由は、浮き電極と絶縁体外層
を広面積で接合すると、該接合部分の密着強度が弱くな
るからである。また、広面積の浮き電極と比較して電極
材料の使用量が少なくてすみ、コストアップを抑えるこ
とができるからである。絶縁体外層5,6の材料として
は、コンデンサ部4と同様の(又は別の)セラミックス
シートが用いられる。浮き電極20,21は、例えばペ
ースト状のAg,Pd,Cu,Ni,Ag−Pd等を前
記セラミックスシートの表面に印刷等の手段にて塗布す
ることによって形成されている。
As shown in FIGS. 1 to 3, a multilayer capacitor 1 is provided with external electrodes 2 and 3 at both ends thereof, and a capacitor portion 4 and insulating outer layers 5 and 6 for protecting the capacitor portion 4 are thick. It has an integrated structure that is stacked and fired in the same direction. As shown in FIG. 4, a frame-shaped floating electrode 20 that is not electrically connected to any of the electrodes is provided inside the outer insulator layer 5. Hereinafter, an electrode that is not electrically connected to any of the electrodes will be referred to as a floating electrode. Similarly, a frame-shaped floating electrode 21 is provided inside the outer insulator layer 6. The reason for forming the frame shape is that when the floating electrode and the outer layer of the insulator are joined to each other over a wide area, the adhesion strength of the joined portion becomes weak. In addition, the amount of electrode material used is smaller than that of the floating electrode having a large area, and the cost increase can be suppressed. As the material of the outer insulator layers 5 and 6, the same (or another) ceramic sheet as the capacitor portion 4 is used. The floating electrodes 20 and 21 are formed, for example, by applying paste-like Ag, Pd, Cu, Ni, Ag-Pd or the like to the surface of the ceramic sheet by printing or the like.

【0010】コンデンサ部4は容量電極22,23,2
4,25,26と誘電体層7,8,9,10を交互に積
層したものである。容量電極22の一方の端部はコンデ
ンサ部4の左側端面に露出し、外部電極2に電気的に接
続している(図5参照)。同様に容量電極24,26も
コンデンサ部4の左側端面に露出し、外部電極2に電気
的に接続している。容量電極23の一方の端部はコンデ
ンサ部4の右側端面に露出し、外部電極3に電気的に接
続している(図7参照)。同様に容量電極25もコンデ
ンサ部4の右側端面に露出し、外部電極3に電気的に接
続している。容量電極22〜26の材料としては、A
g,Pd,Cu,Ni,Ag−Pd等が用いられる。
The capacitor section 4 includes capacitance electrodes 22, 23, 2
4, 25, 26 and dielectric layers 7, 8, 9, 10 are alternately laminated. One end of the capacitance electrode 22 is exposed on the left end surface of the capacitor unit 4 and is electrically connected to the external electrode 2 (see FIG. 5). Similarly, the capacitance electrodes 24 and 26 are exposed on the left end surface of the capacitor portion 4 and are electrically connected to the external electrode 2. One end of the capacitance electrode 23 is exposed on the right end surface of the capacitor unit 4 and is electrically connected to the external electrode 3 (see FIG. 7). Similarly, the capacitance electrode 25 is exposed on the right end surface of the capacitor portion 4 and is electrically connected to the external electrode 3. The material of the capacitor electrodes 22 to 26 is A
g, Pd, Cu, Ni, Ag-Pd, etc. are used.

【0011】誘電体層7の内部には、図6に示すよう
に、額縁形状の浮き電極27が設けられている。同様に
誘電体層8,9,10のそれぞれの内部には額縁形状の
浮き電極28,29,30が設けられている。次に、浮
き電極20,21及び27〜30について詳説する。浮
き電極20,21及び27〜30は同様のサイズに設計
され、容量電極22〜26が形成する容量有効面部分よ
り若干大きく設定されている。浮き電極20,21及び
27〜30のサイズを、容量電極22〜26が形成する
容量有効面部分より大きくする理由は、電界集中の緩和
により効果的であるからである。図8に示すように、浮
き電極20は、外部電極3の端部3aと容量電極22の
端部22aの略間に設けられている。第1実施例の場
合、浮き電極20は、電極幅Xの1/2の位置が端部2
2aの位置に合わされ、かつ、絶縁体外層5の厚さdの
1/2の位置に設けられている。同様に、浮き電極21
も電極幅Xの1/2の位置が容量電極26の端部の位置
に合わされ、かつ、絶縁体外層6の厚さdの1/2の位
置に設けられている。この浮き電極20,21によっ
て、それぞれ容量電極22と外部電極3の間及び容量電
極26と外部電極3の間の電界集中が緩和され、コンデ
ンサ1表面の沿面放電が抑制される。
Inside the dielectric layer 7, as shown in FIG. 6, a frame-shaped floating electrode 27 is provided. Similarly, frame-shaped floating electrodes 28, 29, 30 are provided inside the dielectric layers 8, 9, 10, respectively. Next, the floating electrodes 20, 21 and 27 to 30 will be described in detail. The floating electrodes 20, 21 and 27 to 30 are designed to have the same size, and are set to be slightly larger than the capacity effective surface portion formed by the capacity electrodes 22 to 26. The reason why the sizes of the floating electrodes 20, 21 and 27 to 30 are made larger than the capacitance effective surface portion formed by the capacitance electrodes 22 to 26 is that it is more effective in relaxing electric field concentration. As shown in FIG. 8, the floating electrode 20 is provided substantially between the end 3 a of the external electrode 3 and the end 22 a of the capacitor electrode 22. In the case of the first embodiment, the floating electrode 20 has the end portion 2 at a position half the electrode width X.
It is aligned with the position of 2a and is provided at a position of 1/2 of the thickness d of the outer insulator layer 5. Similarly, the floating electrode 21
Also, the position of 1/2 of the electrode width X is aligned with the position of the end of the capacitor electrode 26, and is provided at the position of 1/2 of the thickness d of the outer insulator layer 6. The floating electrodes 20 and 21 alleviate the electric field concentration between the capacitance electrode 22 and the external electrode 3 and between the capacitance electrode 26 and the external electrode 3, respectively, and suppress the creeping discharge on the surface of the capacitor 1.

【0012】浮き電極27〜30は、それぞれ誘電体層
7,8,9,10の厚さcの1/2の位置に設けられて
いる。この浮き電極27〜30によって、それぞれ容量
電極22と23の間、容量電極23と24の間、容量電
極24と25の間、容量電極25と26の間の電界集中
が緩和され、容量電極間の絶縁破壊が抑制される。ここ
に、浮き電極20,21及び27〜30の電極半幅X/
2は、容量電極22,24,26の端部と外部電極3
(あるいは、容量電極23,25の端部と外部電極2)
のギャップ寸法をgとした場合、g/4〜3g/4に設
計するのが好ましい。
The floating electrodes 27 to 30 are provided at positions half the thickness c of the dielectric layers 7, 8, 9 and 10, respectively. The floating electrodes 27 to 30 alleviate the electric field concentration between the capacitance electrodes 22 and 23, between the capacitance electrodes 23 and 24, between the capacitance electrodes 24 and 25, and between the capacitance electrodes 25 and 26, respectively. Dielectric breakdown is suppressed. Here, the electrode half width X / of the floating electrodes 20, 21 and 27 to 30
2 is an end portion of the capacitive electrodes 22, 24 and 26 and the external electrode 3
(Or, the ends of the capacitance electrodes 23 and 25 and the external electrode 2)
It is preferable to design g / 4 to 3g / 4, where g is the gap size.

【0013】さらに、具体的数値を例示して説明する。
例えば、積層型コンデンサ1の外形寸法を5.7mm×
5.0mm、容量電極22,24,26の端部と外部電
極3のギャップ寸法g及び容量電極23,25の端部と
外部電極2のギャップ寸法gを0.42mm、絶縁体外
層5,6の厚さdを0.2mm、誘電体層7〜10の厚
さcを0.12mmとし、浮き電極20,21及び27
〜30の電極幅Xを変えたときのコンデンサ1内部にお
ける電界強度を評価した。図9は評価結果を表示するグ
ラフである。グラフの横軸は浮き電極幅X、縦軸は以下
の(1)式で定義される最大電界強度比である。
Further, specific numerical values will be exemplified and described.
For example, the external dimensions of the multilayer capacitor 1 are 5.7 mm ×
5.0 mm, the gap dimension g between the ends of the capacitance electrodes 22, 24 and 26 and the external electrode 3 and the gap dimension g between the ends of the capacitance electrodes 23 and 25 and the external electrode 2 are 0.42 mm, the outer insulator layers 5 and 6 Has a thickness d of 0.2 mm and the dielectric layers 7 to 10 have a thickness c of 0.12 mm.
The electric field strength inside the capacitor 1 when the electrode width X of ˜30 was changed was evaluated. FIG. 9 is a graph displaying the evaluation result. The horizontal axis of the graph is the floating electrode width X, and the vertical axis is the maximum electric field intensity ratio defined by the following equation (1).

【0014】 最大電界強度比=E1/E2 ……(1) E1:浮き電極を備えたコンデンサ1の最大電界強度 E2:浮き電極がないこと以外はコンデンサ1と同様の
構造を備えたコンデンサの最大電界強度 実線41はコンデンサ1の長手方向に関しての最大電界
強度比を表示し、実線42はコンデンサ1の幅方向に関
しての最大電界強度比を表示している。最大電界強度比
が1.0より小さければ、浮き電極20,21,27〜
30によって電界集中が緩和され、コンデンサ1の耐電
圧性能が向上したことを意味する。逆に、最大電界強度
比が1.0より大きければ浮き電極20,21,27〜
30によって電界集中が強くなり、コンデンサ1の耐電
圧性能が低下したことを意味する。グラフによれば浮き
電極幅Xを約0.3mm以上に設定することにより、電
界集中が緩和され、コンデンサ1の耐電圧性能を向上さ
せることができる。
Maximum electric field strength ratio = E 1 / E 2 (1) E 1 : Maximum electric field strength of the capacitor 1 having a floating electrode E 2 : The same structure as the capacitor 1 except that there is no floating electrode The maximum electric field strength solid line 41 of the capacitor represents the maximum electric field strength ratio in the longitudinal direction of the capacitor 1, and the solid line 42 represents the maximum electric field strength ratio of the capacitor 1 in the width direction. If the maximum electric field strength ratio is smaller than 1.0, the floating electrodes 20, 21, 27 ...
It means that the electric field concentration is eased by 30, and the withstand voltage performance of the capacitor 1 is improved. On the contrary, if the maximum electric field strength ratio is larger than 1.0, the floating electrodes 20, 21, 27 ...
It means that the electric field concentration is increased by 30 and the withstand voltage performance of the capacitor 1 is lowered. According to the graph, when the floating electrode width X is set to about 0.3 mm or more, the electric field concentration is alleviated and the withstand voltage performance of the capacitor 1 can be improved.

【0015】表1及び表2はそれぞれ直流電圧及び交流
電圧による絶縁破壊試験の試験結果を示すものである。
試験は、空気雰囲気中にセットされた試料に、100V
/秒の電圧上昇で直流電圧又は交流電圧を、試料が絶縁
破壊を生じるまで印加する方法で行った。
Tables 1 and 2 show the test results of the dielectric breakdown test with a DC voltage and an AC voltage, respectively.
The test is performed with 100 V applied to the sample set in the air atmosphere.
A direct current voltage or an alternating current voltage was applied at a voltage increase of 1 second per second until a dielectric breakdown occurred in the sample.

【0016】[0016]

【表1】 [Table 1]

【0017】[0017]

【表2】 [Table 2]

【0018】表1及び表2より、浮き電極20,21,
27〜30を設けることにより、絶縁破壊電圧が約10
%高くなることがわかる。図10及び図11は試験結果
を度数分布で表示したグラフである。グラフ中、実線が
浮き電極を備えたコンデンサ1の試験結果を示す。比較
のため、浮き電極がないこと以外はコンデンサ1と同様
の構造を備えたコンデンサの試験結果も合わせて点線で
示している。
From Tables 1 and 2, the floating electrodes 20, 21,
By providing 27 to 30, the dielectric breakdown voltage is about 10
You can see that it becomes higher. 10 and 11 are graphs in which the test results are displayed in frequency distribution. In the graph, the solid line shows the test result of the capacitor 1 provided with the floating electrode. For comparison, the test result of the capacitor having the same structure as the capacitor 1 except that there is no floating electrode is also shown by a dotted line.

【0019】[第2実施例、図12]第2実施例の積層
型コンデンサは、絶縁体外層及び誘電体層にそれぞれ浮
き電極を2層内在させたものである。図12に示すよう
に、積層型コンデンサ51は、左端部には外部電極53
が設けられており、コンデンサ部54とこのコンデンサ
部54を保護するための絶縁体外層55を厚み方向に積
み重ねた構造をしている。絶縁体外層55の内部には、
いずれの電極にも電気的に接続されない額縁形状の浮き
電極60,61が設けられている。
[Second Embodiment, FIG. 12] The multilayer capacitor of the second embodiment has two floating electrodes inside the insulator outer layer and the dielectric layer. As shown in FIG. 12, the multilayer capacitor 51 has an external electrode 53 at the left end.
Is provided and has a structure in which a capacitor portion 54 and an outer insulator layer 55 for protecting the capacitor portion 54 are stacked in the thickness direction. Inside the outer insulator layer 55,
Frame-shaped floating electrodes 60 and 61 that are not electrically connected to any of the electrodes are provided.

【0020】コンデンサ部54は容量電極70,71,
72と誘電体層57,58,59を交互に積層したもの
である。誘電体層57及び58の内部にはそれぞれ額縁
形状の浮き電極62,63,64,65が設けられてい
る。浮き電極60及び61は、外部電極53の端部53
aと容量電極70の端部70aの略間に設けられてい
る。第2実施例の場合、浮き電極60及び61は、端部
70aと外部電極53のコーナー部53bを結ぶ線上に
その端部が位置し、かつ、絶縁体外層55の厚さdを3
等分する位置に設けられている。この浮き電極60,6
1によって、容量電極70と外部電極53の間の電界集
中が緩和され、コンデンサ51表面の沿面放電が抑制さ
れる。
The capacitor section 54 includes capacitance electrodes 70, 71,
72 and dielectric layers 57, 58 and 59 are alternately laminated. Inside the dielectric layers 57 and 58, frame-shaped floating electrodes 62, 63, 64, and 65 are provided, respectively. The floating electrodes 60 and 61 are the end portions 53 of the external electrode 53.
It is provided between a and the end portion 70a of the capacitance electrode 70. In the case of the second embodiment, the floating electrodes 60 and 61 have their ends located on the line connecting the ends 70a and the corners 53b of the external electrodes 53, and the thickness d of the outer insulator layer 55 is set to 3 mm.
It is provided at equal positions. This floating electrode 60, 6
By 1, the electric field concentration between the capacitance electrode 70 and the external electrode 53 is relaxed, and creeping discharge on the surface of the capacitor 51 is suppressed.

【0021】浮き電極62,65は、浮き電極61と等
しいサイズであり、浮き電極63,64は浮き電極60
と等しいサイズである。各浮き電極62〜65は、それ
ぞれ誘電体層57,58の厚さcを3等分する位置に設
けられている。この浮き電極62〜65によって、それ
ぞれ容量電極70と71の間、容量電極71と72の間
の電界集中が緩和され、容量電極間の絶縁破壊が抑制さ
れる。従って、耐電圧性能が優れた小型の積層型コンデ
ンサが得られる。
The floating electrodes 62 and 65 have the same size as the floating electrode 61, and the floating electrodes 63 and 64 are the floating electrodes 60.
Is the same size as. The floating electrodes 62 to 65 are provided at positions that divide the thickness c of the dielectric layers 57 and 58 into three equal parts. The floating electrodes 62 to 65 alleviate the electric field concentration between the capacitance electrodes 70 and 71 and between the capacitance electrodes 71 and 72, and suppress the dielectric breakdown between the capacitance electrodes. Therefore, it is possible to obtain a small-sized multilayer capacitor having excellent withstand voltage performance.

【0022】なお、本発明に係る積層型コンデンサは前
記実施例に限定するものではなく、その要旨の範囲内で
種々に変形することができる。特に、浮き電極の形状や
配設位置は任意である。前記実施例の浮き電極の形状は
額縁形状であるが、中央部分に穴を設けない形状にして
もよい。また、浮き電極を絶縁体外層や誘電体層にそれ
ぞれ3層以上内在させてもよい。さらに、第2実施例で
は浮き電極60と61、浮き電極62と63等はサイズ
を異ならせているが、浮き電極61,62をそれぞれ浮
き電極60,63と同様のサイズにまで大きくしてもよ
い。
The multilayer capacitor according to the present invention is not limited to the above embodiment, but can be variously modified within the scope of its gist. In particular, the shape and position of the floating electrode are arbitrary. Although the shape of the floating electrode in the above embodiment is a frame shape, it may be a shape without a hole in the central portion. Further, three or more floating electrodes may be incorporated in the outer layer of the insulator or the dielectric layer. Further, in the second embodiment, the floating electrodes 60 and 61, the floating electrodes 62 and 63 and the like have different sizes, but even if the floating electrodes 61 and 62 are increased in size to the same size as the floating electrodes 60 and 63, respectively. Good.

【0023】[0023]

【発明の効果】以上の説明で明らかなように、本発明に
よれば、いずれの電極にも電気的に接続されない浮き電
極を絶縁体外層に内在しているので、容量電極と外部電
極間の電界集中が緩和され、コンデンサ表面の沿面放電
を抑えることができる。特に、浮き電極を、容量電極の
端部と外部電極の端部の略間の位置に設ければ、容量電
極と外部電極間の電界集中がより緩和できる。この結
果、絶縁体外層の厚さをアップさせることなく、耐電圧
性能が優れた小型の積層型コンデンサが得られる。
As is apparent from the above description, according to the present invention, since the floating electrode which is not electrically connected to any of the electrodes is provided in the outer layer of the insulator, the space between the capacitor electrode and the external electrode is increased. Electric field concentration is relieved, and creeping discharge on the capacitor surface can be suppressed. In particular, if the floating electrode is provided at a position approximately between the end of the capacitance electrode and the end of the external electrode, the electric field concentration between the capacitance electrode and the external electrode can be alleviated more. As a result, it is possible to obtain a small multilayer capacitor excellent in withstand voltage performance without increasing the thickness of the outer layer of the insulator.

【0024】さらに、浮き電極を容量電極間に設けるこ
とにより、容量電極相互間の電界集中も緩和され、さら
に優れた耐電圧性能を有するものが得られる。
Further, by providing the floating electrodes between the capacitance electrodes, the electric field concentration between the capacitance electrodes can be alleviated, and the one having further excellent withstand voltage performance can be obtained.

【図面の簡単な説明】[Brief description of drawings]

図1ないし図11は本発明に係る積層型コンデンサの第
1実施例を示すものである。
1 to 11 show a first embodiment of a multilayer capacitor according to the present invention.

【図1】積層型コンデンサの外観を示す斜視図。FIG. 1 is a perspective view showing the appearance of a multilayer capacitor.

【図2】図1のII−II断面図。FIG. 2 is a sectional view taken along line II-II of FIG.

【図3】図1のIII−III断面図。FIG. 3 is a sectional view taken along line III-III in FIG.

【図4】積層型コンデンサの内部構造を示す平面図。FIG. 4 is a plan view showing the internal structure of the multilayer capacitor.

【図5】積層型コンデンサの内部構造を示す平面図。FIG. 5 is a plan view showing the internal structure of the multilayer capacitor.

【図6】積層型コンデンサの内部構造を示す平面図。FIG. 6 is a plan view showing the internal structure of the multilayer capacitor.

【図7】積層型コンデンサの内部構造を示す平面図。FIG. 7 is a plan view showing the internal structure of the multilayer capacitor.

【図8】浮き電極の配設位置関係を説明するための一部
拡大断面図。
FIG. 8 is a partially enlarged cross-sectional view for explaining a positional relationship between floating electrodes.

【図9】浮き電極幅と最大電界強度比の関係を示すグラ
フ。
FIG. 9 is a graph showing the relationship between the floating electrode width and the maximum electric field strength ratio.

【図10】直流電圧による絶縁破壊の評価結果を示すグ
ラフ。
FIG. 10 is a graph showing the evaluation results of dielectric breakdown due to DC voltage.

【図11】交流電圧による絶縁破壊の評価結果を示すグ
ラフ。
FIG. 11 is a graph showing the evaluation results of dielectric breakdown due to an AC voltage.

【図12】本発明に係る積層型コンデンサの第2実施例
を示す一部拡大断面図。
FIG. 12 is a partially enlarged sectional view showing a second embodiment of the multilayer capacitor according to the present invention.

【符号の説明】[Explanation of symbols]

1…積層型コンデンサ 2,3…外部電極 3a…外部電極の端部 4…コンデンサ部 5,6…絶縁体外層 7,8,9,10…誘電体層 20,21…浮き電極 22,23,24,25,26…容量電極 22a…容量電極の端部 27,28,29,30…浮き電極 51…積層型コンデンサ 53…外部電極 53a…外部電極の端部 53b…外部電極のコーナー部 54…コンデンサ部 55…絶縁体外層 57,58,59…誘電体層 60,61,62,63,64,65…浮き電極 70,71,72…容量電極 70a…容量電極の端部 DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor 2, 3 ... External electrode 3a ... End of external electrode 4 ... Capacitor part 5, 6 ... Insulator outer layer 7, 8, 9, 10 ... Dielectric layer 20, 21 ... Floating electrode 22, 23, 24, 25, 26 ... Capacitance electrode 22a ... Capacitance electrode end 27, 28, 29, 30 ... Floating electrode 51 ... Multilayer capacitor 53 ... External electrode 53a ... External electrode end 53b ... External electrode corner 54 ... Capacitor section 55 ... Insulator outer layer 57, 58, 59 ... Dielectric layer 60, 61, 62, 63, 64, 65 ... Floating electrode 70, 71, 72 ... Capacitance electrode 70a ... End of capacitance electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数の容量電極と、 前記容量電極のそれぞれと交互に積層してコンデンサ部
を構成する誘電体層と、 前記容量電極と前記誘電体層を交互に積層したコンデン
サ部を保護するための絶縁体外層と、 前記容量電極に電気的に接続された複数の外部電極と、 いずれの電極にも電気的に接続されない状態で前記絶縁
体外層に内在した浮き電極と、 を備えたことを特徴とする積層型コンデンサ。
1. A plurality of capacitance electrodes, a dielectric layer that is alternately laminated with each of the capacitance electrodes to form a capacitor section, and a capacitor section in which the capacitance electrodes and the dielectric layers are alternately laminated is protected. An outer layer of an insulating material, a plurality of outer electrodes electrically connected to the capacitance electrode, and a floating electrode that is internal to the outer layer of the insulating material without being electrically connected to any of the electrodes. Multilayer type capacitor.
【請求項2】 絶縁体外層に内在した浮き電極が、コン
デンサ部を構成する容量電極の端部と外部電極の端部の
略間の位置に設けられていることを特徴とする請求項1
記載の積層型コンデンサ。
2. The floating electrode, which is internal to the outer layer of the insulator, is provided at a position approximately between the end of the capacitive electrode and the end of the external electrode which form the capacitor section.
The multilayer capacitor described.
【請求項3】 いずれの電極にも電気的に接続されない
状態で、容量電極間の誘電体層に浮き電極が内在してい
ることを特徴とする請求項1記載の積層型コンデンサ。
3. The multilayer capacitor according to claim 1, wherein the floating electrode is internally provided in the dielectric layer between the capacitance electrodes in a state where it is not electrically connected to any of the electrodes.
JP5071582A 1993-03-30 1993-03-30 Multilayer capacitors Expired - Lifetime JP3064732B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5071582A JP3064732B2 (en) 1993-03-30 1993-03-30 Multilayer capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5071582A JP3064732B2 (en) 1993-03-30 1993-03-30 Multilayer capacitors

Publications (2)

Publication Number Publication Date
JPH06283370A true JPH06283370A (en) 1994-10-07
JP3064732B2 JP3064732B2 (en) 2000-07-12

Family

ID=13464836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5071582A Expired - Lifetime JP3064732B2 (en) 1993-03-30 1993-03-30 Multilayer capacitors

Country Status (1)

Country Link
JP (1) JP3064732B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011135036A (en) * 2009-12-23 2011-07-07 Samsung Electro-Mechanics Co Ltd Laminated ceramic capacitor and method of manufacturing the same
US8130484B2 (en) 2007-06-27 2012-03-06 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component and mounting structure thereof
JP2021197458A (en) * 2020-06-15 2021-12-27 株式会社村田製作所 Laminated ceramic capacitor
US11557436B2 (en) 2019-10-31 2023-01-17 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor and mount structure for multilayer ceramic capacitor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8130484B2 (en) 2007-06-27 2012-03-06 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component and mounting structure thereof
JP2011135036A (en) * 2009-12-23 2011-07-07 Samsung Electro-Mechanics Co Ltd Laminated ceramic capacitor and method of manufacturing the same
US8259434B2 (en) 2009-12-23 2012-09-04 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and method of fabricating the same
US11557436B2 (en) 2019-10-31 2023-01-17 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor and mount structure for multilayer ceramic capacitor
JP2021197458A (en) * 2020-06-15 2021-12-27 株式会社村田製作所 Laminated ceramic capacitor

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