JPH06282525A - Synchronous bus device - Google Patents

Abstract

PURPOSE:To expand the allowable range of the setup time and hold time of a device connected with a synchronous bus. CONSTITUTION:A data delay time control means 102 obtains the time delay data according to a slave device 200 performing an access from a data delay time holding means 103 and controls a data delay time switching means 101. An internal clock phase control means 112 obtains the phase delay data according to the slave device 200 performing the access from an internal clock phase holding means 113 and controls an internal clock phase switching means 111.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous bus device.

[0002]

2. Description of the Related Art Generally, in a synchronous bus device, a setup time and a hold time for accessing data at an interface portion of a device connected to a bus are defined (Sun Microsystems, SBu).
S Specification B. (See O). Therefore, when designing a synchronous bus device, it is necessary to carefully consider the setup time and hold time of the transfer data, and the setup time and hold time of the transfer data of the device connected to the synchronous bus are also the specifications of the synchronous bus. Constrained to meet.

[0003]

In the above-mentioned conventional synchronous bus device, since the setup time and hold time of transfer data are fixed, the conditions of the setup time and hold time of transfer data defined by the synchronous bus device are satisfied. In order to satisfy the above, there is a problem that the design condition of the device connected to the bus may be severely restricted.

The present invention solves the above-mentioned problems of the prior art. By changing the setup time and hold time of transfer data in the synchronous bus device relatively, the setup time of transfer data in the connected device is changed. The purpose is to widen the allowable range of hold time.

[0005]

In order to achieve the above-mentioned object, the synchronous bus device of the present invention is configured so that the transfer data output from the device connected to the synchronous bus to the synchronous bus is synchronized with the synchronous data. And a data delay means for adding a predetermined delay based on the system clock of the mold bus.

More specifically, the data delay means performs access by the data delay time switching means for inserting a predetermined time delay into transfer data between the synchronous bus and the internal logic of the master device, and the master device. A slave device and data delay time holding means for holding time-delayed data corresponding to reading or writing of the access; and when the master device accesses the slave device, the delay time holding means transfers the slave device and the access And a delay time control means for determining the time delay to be inserted by the data delay time switching means based on this data.

[0007]

With the above structure, in the synchronous bus device of the present invention, the delay time of the transfer data and the relative delay time of the transfer data and the system clock are controlled, and the setup time and the hold time of the transfer data relative to the system clock are controlled. Can be changed.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In FIG. 1, 10 is a synchronous bus, 100 is a master device, and 200 and 30.
Reference numerals 0, 400, and 500 are slave devices, 101 is a data delay time control unit, 102 is a data delay time holding unit, 103 is a data delay time switching unit, and 120 is an internal logic.

Bus access in the synchronous bus device configured as described above will be described.

(1) When writing from the master device 100 to the slave device 200 (device having a long hold time).

The timing of transfer data in the bus interface section of the slave device 200 is shown in FIG. The waveform (a) in FIG. 4 is the setup time and hold time required for the slave device 200 to capture data. The waveform (b) shows the master device 100.
2 is a waveform of transfer data when the delay time is set to the minimum in the data delay time switching means 101, that is, when the delay is not inserted at all. The waveform (c) is the waveform of the transfer data when the delay time is added by the delay time switching unit 101 so that the master device 100 can access the slave device 200.

As is clear from comparing the waveforms (a) and (b) in FIG. 4, if the data delay time switching means 101 does not insert a delay, the master device 100 cannot write to the slave device 200. Therefore, in the data delay time switching means 101, a write is enabled by adding a delay to the data path and creating the waveform (c) of FIG.

This data delay time switching operation will be described in detail below. First, the internal logic 120 instructs the data delay time control means 102 to operate the slave device 20.
Notify that it is a write to 0. The data delay time control means 102 uses the data delay time holding means 103 to
At this time, the slave device 200 to be accessed and the delay time data corresponding to the write are read. The data delay time control means 102 is based on the read delay time data, and the data delay time switching means 101
To control. As a result, the delay time in the data path inside the master device can be changed.

(2) When writing from the master device 100 to the slave device 300 (having a long setup time).

The timing of transfer data in the bus interface section of the slave device 300 is shown in FIG. The waveform (a) of FIG. 5 is the setup time and hold time required for the slave device 300 to capture data. The waveform (b) shows the master device 100.
2 is a waveform of transfer data when the delay time is set to the minimum in the data delay time switching means 101, that is, when the delay is not inserted at all. The waveform (c) is the waveform of the transfer data when the delay time is added by the data delay time switching unit 101 so that the master device 100 can write to the slave device 300.

As in the case of the above (1), the data delay time switching means 101 adds a delay to the data path and creates the waveform (c) of FIG. 5 to enable writing. The means for switching the delay time is also the same as in (1).

(3) When the slave device 400 (device with short access time) is read from the master device 100, the data delay time switching means 101 of the master device 100 adds a data path delay in the same manner as in (1) above. , Enable lead.

(4) When the slave device 500 (device having a long access time) is read from the master device 100, the data delay time switching means 101 of the master device 100 adds a data path delay in the same manner as in (2) above. , Enable lead.

As described above, according to the present embodiment, a time delay can be added to the transfer data on the data path according to the slave device and access, so that the slave device connected to the synchronous bus can be set up. It is possible to expand the allowable range of time and hold time.

(Embodiment 2) FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention.

In FIG. 2, 10 is a synchronous bus, 100
Is the master device, 200, 300, 400 and 50
0 is a slave device, 111 is an internal clock phase switching means, 112 is an internal clock phase control means, 113
Is an internal clock phase holding means, and 120 is an internal logic.

Bus access in the synchronous bus device configured as described above will be described.

(1) When writing from the master device 100 to the slave device 200 (device having a long hold time).

The timing of transfer data in the bus interface section of the slave device 200 is shown in FIG. The waveform (a) in FIG. 6 is the setup time and hold time required for the slave device 200 to capture data. The waveform (b) shows the master device 100.
This is the waveform of the internal clock when the phase is delayed from the phase of the system clock by the internal clock phase switching means 111 so that the slave device 200 can write to the slave device 200. The waveform (c) is the master device 100 based on the internal clock of the waveform (b).
This is the data transferred from.

As shown in FIG. 6, when the system clock and the internal clock are in phase, the master device 10
The slave device 200 cannot write from 0. Therefore, the internal clock phase switching means 111 delays the phase of the internal clock to generate the waveform (c) in FIG. 6 to enable writing.

The operation of switching the phase of the internal clock will be described below. First, the internal logic 120 instructs the internal clock phase control means 112 to operate the slave device 200.
Signal to the light. The internal clock phase control means 112 uses the internal clock phase holding means 113 to access the slave device 20 at this time.
The phase data corresponding to 0 and write are read. The internal clock phase control means 112, based on the read phase data, the internal clock phase switching means 111.
To control. Thereby, the phase of the internal clock of the master device 100 can be changed.

(2) When writing from the master device 100 to the slave device 300 (device having a long setup time).

The timing of transfer data in the bus interface section of the slave device 200 is shown in FIG. The waveform (a) in FIG. 7 shows the setup time and hold time required for the slave device 200 to capture data. The waveform (b) shows the master device 100.
This is the waveform of the internal clock when the phase is advanced from the phase of the system clock by the internal clock phase switching means 111 so that the slave device 200 can write to the slave device 200. Waveform (c) is waveform (b)
The data transferred from the master device 100 based on the internal clock of. The means for switching the phase of the internal clock is the same as in (1).

(3) When the slave device 400 (device with short access time) is read from the master device 100, the phase switching means 111 of the master device 100 adds a delay of the data path and reads it in the same manner as in (1) above. To enable.

(4) When the slave device 500 (device having a long access time) is read from the master device 100, the phase switching means 111 of the master device 100 adds a delay of the data path and reads the same as in (2) above. To enable.

As described above, according to this embodiment, it is possible to add a phase delay to the internal clock of the master device according to the slave device and access, and by performing data transfer with this internal clock as a reference, synchronization is achieved. It is possible to expand the allowable range of setup time and hold time of the slave device connected to the type bus.

(Embodiment 3) FIG. 3 is a block diagram showing the configuration of the third embodiment of the present invention.

In FIG. 3, 10 is a synchronous bus, and 100
Is the master device, 200, 300, 400 and 50
0 is a slave device, 101 is a data delay time switching unit, 102 is a data delay time control unit, 103 is a data delay time holding unit, 111 is an internal clock phase switching unit, 112 is an internal clock phase control unit, and 113 is an internal clock phase. Holding means, 120 is an internal logic.

Bus access in the synchronous bus device configured as described above will be described. In this example,
It has both the functions of the first and second embodiments described above. The operation is performed as follows in consideration of the advantages of the first and second embodiments.

(1) When writing from the master device 100 to the slave device 200 (device having a long hold time), access is performed in the same manner as in the first embodiment.

(2) When writing from the master device 100 to the slave device 300 (device having a long setup time), access is performed in the same manner as in the second embodiment.

(3) When reading the slave device 400 (device with short access time) from the master device 100, access is performed in the same manner as in the first embodiment.

(4) When reading the slave device 500 (device having a long access time) from the master device 100, access is performed in the same manner as in the second embodiment.

Table 1 shows a comparison between the access characteristics of this embodiment and the access characteristics of the first and second embodiments.

[0041]

[Table 1]

As is clear from Table 1, in the first embodiment, when writing to a slave device having a long setup time and reading from a slave device having a long access time, the data delay time switching means 101 delays one clock or more. Access is delayed because it must be added. In the second embodiment, when writing to a slave device having a long hold time and reading from a slave device having a short access time, the operation of the master device 100 is delayed because the phase of the internal clock of the master device 100 is delayed.

On the other hand, in this embodiment, when writing to a slave device having a long hold time and reading from a slave device having a short access time, a time delay is added by the data delay means 101 as in the first embodiment.
In the case of writing to a slave device having a long setup time and reading from a slave device having a long access time, the master device 100 as in the second embodiment.
A delay is added to the phase of the internal clock of (1), an operation that complements the problems of the first and second embodiments is performed, and an excellent effect can be obtained in high-speed access.

In the present invention, the data delay time switching means 101, the data delay time control means 102, the data delay time holding means 103, the internal clock phase switching means 111, the internal clock phase control means 112, and the internal clock phase holding means 113. Although it is provided inside the master device 100, it may be provided on the synchronous bus 10 or other master device and slave device connected to the synchronous bus 10.

The number of master devices and slave devices connected to the synchronous bus device of the present invention is not particularly limited, and it goes without saying that there may be devices having both master and slave properties.

[0046]

As described above, according to the present invention, by providing the data delay means for adding a predetermined delay to the transfer data output on the bus, the setup time and the hold time of the transfer data relative to the system clock are relative. It is possible to increase the allowable range of setup time and hold time of the device connected to the synchronous bus.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronous bus device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a synchronous bus device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a synchronous bus device according to a third embodiment of the present invention.

FIG. 4 is a waveform diagram of transfer data in a write to the slave device 200 according to the first embodiment of the present invention.

FIG. 5 is a waveform diagram of transfer data when writing to the slave device 300 according to the first embodiment of the present invention.

FIG. 6 is a waveform diagram of transfer data when writing to the slave device 200 according to the second embodiment of the present invention.

FIG. 7 is a waveform diagram of transfer data when writing to the slave device 300 according to the second embodiment of the present invention.

[Explanation of symbols]

 10 Synchronous Bus 100 Master Device 101 Data Delay Time Switching Means 102 Data Delay Time Controlling Means 103 Data Delay Time Holding Means 111 Internal Clock Phase Switching Means 113 Internal Clock Phase Holding Means 120 Internal Logic 200 Slave Devices 300 Slave Devices 400 Slave Devices 500 Slave device

Claims (3)

[Claims] 1. A data delay means for adding a predetermined delay based on a system clock of the synchronous bus to transfer data output from the device connected to the synchronous bus onto the synchronous bus. A synchronous bus device characterized by the above. 2. A data delay means, a data delay time switching means for inserting a predetermined time delay in transfer data between a synchronous bus and an internal logic of a master device, a slave device accessed by the master device, and the access. Data delay time holding means for holding data of time delay corresponding to reading or writing of data, and when the master device accesses the slave device, the delay time holding means stores the time delay of the slave device and the time delay corresponding to the access. 2. The synchronous bus device according to claim 1, further comprising delay time control means for reading data and determining a time delay to be inserted by the data delay time switching means based on the data. 3. The data delay means performs internal clock phase switching means for adding a predetermined phase delay to a system clock obtained from a synchronous bus to output an internal clock serving as a reference clock of the master device, and the master device performs access. A slave device and an internal clock phase holding means for holding data of the phase delay of the internal clock corresponding to the reading or writing of the access; and the slave from the internal clock phase holding means when the master device accesses the slave device. 2. An internal clock phase control means for reading the data of the phase delay corresponding to the device and the access, and determining the phase delay to be added by the internal clock phase switching means based on this data. Record Synchronous bus device.