JPH06282246A - Liquid crystal display device and display system - Google Patents

Abstract

PURPOSE:To attain low electric power at magnified display time of a liquid crystal display device, enable magnified display by the liquid crystal display device in an upper and lower divided driving system, and select a magnified display area automatically. CONSTITUTION:In an upper and lower divided driving system where an upper side data bus 702 is inputted to the upper side and a lower side data bus 703 is inputted to the lower side, when magnified display is carried out in the longitudinal direction, a boundary line between upper and lower parts becomes discontinuous (A). In order to eliminate this, a new upper side data bus 710 and a new lower side data bus 709 having a period during which the upper side data bus 702 and the lower side data bus 703 are replaced with each other, are inputted, and a synchronous signal is also delayed, and a new upper side synchronous signal 711 and a new lower side synchronous signal 712 are inputted (B).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an enlarged display function of a liquid crystal display device.

[0002]

2. Description of the Related Art The enlargement function of a liquid crystal display (LCD) is particularly effective for portable information equipment in terms of readability. Several methods of enlarging the liquid crystal display device have been invented since ancient times. For example, JP-A-55-794
Japanese Laid-Open Patent Publication No. 92 describes a method of enlarging and displaying by collectively outputting several electrodes at the same time. Further, Japanese Patent Application Laid-Open No. 57-68979 describes a method of changing the display area by changing the number of scanning clocks to multiple times for enlarged display and further delaying the reference signal.

[0003]

However, the conventional enlarging method, including the enlarging method described above, has various problems. First, the conventional expansion method does not take into consideration the decrease in power consumption due to the decrease in the number of divisions during expansion. Second, LC by the upper and lower split drive method in which the upper side and the lower side are driven separately.
If the conventional enlargement method as described above is used as it is on D, there is a problem that when the display data of a predetermined area is enlarged, the display is discontinuous at the upper and lower boundaries. Thirdly, nothing has been proposed about automatic selection of the display area at the time of enlargement.

The present invention solves these problems and achieves low power consumption in enlarged display of a liquid crystal display device. In addition, the liquid crystal display device of the vertical split drive enables enlarged display.
Further, the enlarged display area can be automatically selected.

[0005]

In order to achieve the above object, the present invention is characterized by a liquid crystal display device or display system having the following configuration. (1) A liquid crystal pixel arranged in a matrix and a driving circuit for driving the liquid crystal pixel are provided, and a plurality of the liquid crystal pixels are electrically connected in parallel to enlarge the size of a display unit pixel. In a liquid crystal display device having a function of enlarging display data by reducing the number of time divisions, the clock frequency of the drive circuit is lowered according to the number of time divisions.

(2) In a liquid crystal display device in which liquid crystal pixels arranged in a matrix are divided into an upper block and a lower block, and pixels on both sides can be driven separately, a plurality of liquid crystal pixels are electrically connected in each block. A means for enlarging the size of the display unit pixel by connecting in parallel and enlarging the display data by lowering the time division number according to the enlargement ratio and a signal changing circuit for transferring the data signal of one block to the other block are provided. When provided and enlarged, the data signal of one block is displayed on the other block via the signal changing circuit according to the display section.

(3) A liquid crystal display device according to item (1) or (2) above, a system circuit including a central processing unit and a memory, and an image data holding device for storing display data output from the system circuit. A display area selection circuit for determining a display area displayed on the liquid crystal display device according to a display area selection signal, and an address holding a display indicating that the system circuit is waiting for input According to a program of the system circuit, a display system is obtained in which the image data holding device is searched and the display area selection signal for displaying the content of the address on the liquid crystal display device is output to the display area selection circuit.

[0008]

First, the first purpose, that is, reduction in power consumption, will be described. In the enlargement mode, some electrodes are spring-loaded to scan, so the number of divisions becomes small, which may result in low power consumption. However, the frequency of the clock pulse for scanning is not taken into consideration when displaying in the enlarged mode by the conventional method. Therefore, in the expansion mode, unnecessary clock pulses are not input.

Next, the display for the second purpose of vertical division driving will be described. For example, when data is displayed by a 640 × 400 LCD used in a personal computer or the like, as shown in FIG. 4A, data signals for the scanning electrodes in the first to 200th rows and the 201st to 400th rows are displayed. The data signals for the scan electrodes are different and the upper and lower driving methods are separately driven.
Therefore, for example, when the 21st to 220th lines are displayed in the vertical magnification mode as shown in FIG. 3, the upper side displays the 21st to 120th line data, and the lower side displays 12th to 120th lines.
The data in lines 1 to 220 must be displayed. Therefore, the lower reference signal is changed to the 120th line, and these data are input to the lower side during the period in which the data of the 121st to 200th lines, which should be originally input to the upper side, are displayed.

Next, the third method of selecting the display area will be described. In the 640 × 400 LCD used in the above-mentioned personal computer, it is 64 when the magnification is doubled.
Only 0x200 minutes of data can be displayed. At this time, the function of selecting to always display the display area in which the cursor is displayed is effective. In addition, considering whether to change the display area of the cursor position compared to the previous time is effective in terms of viewability. The embodiment shows a method of detecting the cursor position by using a basic input / output system (BIOS).

[0011]

[Example 1]

Embodiment 1 FIG. 3 shows a circuit block diagram inside an LCD scanning drive circuit according to the present invention. X counter circuit 301
Is a counter circuit using the reset signal 103 as a reference and the clock signal 102 as a basic clock signal.
When the signal 104 is low level, Y is calculated every 20 counts.
When the mode 0 signal 104 is at a high level, the Y clock signal 3 is output every 10 counts when the clock signal 303 is output.
03 is output. The X counter bus 121 is a bus including 20 count data lines output from the X counter circuit 301, and the X data bus 304 is a bus including 20 data lines output from the multiplexer circuit 120.

The multiplexer circuit 120 inputs the X counter bus 121 from the X counter circuit 301, outputs the information of the X counter bus 121 to the X data bus 304 as it is when the mode 0 signal 104 is low level, and outputs the mode 0 signal 104. Is a circuit for outputting the odd-numbered and even-numbered X data lines at the same timing. The Y counter circuit 302 is a counter circuit that uses the Y clock signal 303 as a basic clock signal and the reset signal 103 as a reset signal. The mode 0 signal 104 and the mode 1 signal 105 are the initial state of the Y counter circuit 302 to start counting and the count. Decide the end state.

The stop signal CKS315 is a signal which is the core of the present invention. The stop signal CKS315 becomes a low level only by the reset signal 103, and becomes a high level when the Y counter circuit 302 counts 10 counts of the Y clock 303. In other words, the stop signal CKS315 resets the X counter circuit 301 and the X
All the data buses 304 are set to low level. At the same time, the stop signal CKS315 is the X of the clock signal 102.
The input to the counter circuit 301 is stopped and brought to the low level. The X data bus 304 is an output data bus according to the 1st to 20th counts by the X counter circuit 301, and the Y data bus 305 is an output data bus according to the 1st to 10th counts by the Y counter circuit 302.

The decoder 1 circuit 306 to the decoder 200 circuit 308 are ANDs of the X data bus 304 and the Y data bus 305. Driver 1 circuit 312 to driver 200
Circuit 314 is the result of decoder 1 circuit 306-decoder 200 circuit 308, respectively, drive 1 signal 309-.
It is a circuit for receiving the drive 200 signal 311, and enabling the output 1 signal 106 to the output 200 signal 114 of high output.

FIGS. 1 and 2 are time charts of respective signals in the case of displaying in the normal mode and in displaying in the enlarged mode in the device having the circuit configuration of FIG. FIG. 1 shows the case where the mode 0 signal 104 is at low level, which corresponds to the normal mode. The output 1 signal 106 is output in synchronization with the rising edge of the first clock signal 102 based on the reset signal 103, and the output 2 signal 107 is output in synchronization with the rising edge of the second clock signal 102 based on the reset signal 103. Output. Output 4 in the same way
The 1st signal 109 is the 41st, and the 42nd output 110 is the output in synchronization with the rising edge of the 42nd clock signal 102,
In the end, the output 200 signal 114 is sequentially output in synchronization with the rising edge of the clock signal 102.

FIG. 2 shows the case where the mode 0 signal 104 is at the high level, which corresponds to the expansion mode. Reset signal 10
Based on 3, the output 1 signal 106 and the output 2 signal 107 are simultaneously output in synchronization with the first rising edge of the clock signal 102. Hereinafter, the output 41 signal 109 and the output 42 signal 11 are output while simultaneously outputting the odd-numbered and even-numbered output terminals.
0 is output simultaneously in synchronization with the rising edge of the 21st clock signal 102, and finally, output 119 signal 112 and output 200 signal 112 are sequentially output in synchronization with the rising edge of the 100th clock signal 102. In this case, the number of divisions is 100, which is half of the original 200 divisions.
The data is divided and only the data corresponding to the 1st to 100th rows is enlarged and displayed twice in the vertical direction. The output waveform in FIG. 3 is actually a waveform for AC driving for preventing deterioration of the LCD, but is omitted for simplicity.

[0017]

Example 2

[Embodiment 2] Next, an embodiment will be described in the case of a vertical division drive system in which data input to a liquid crystal display device is divided into upper and lower parts. Before describing the configuration of the present embodiment, a configuration for performing conventional vertical split drive will be described for comparison with the present embodiment. FIG. 4A is a schematic diagram when data input to the LCD capable of displaying 400 lines is divided into upper and lower 200 lines. Input the upper data bus 702 (4 parameter input) for transferring data of 1 to 200 lines as the upper data, and input the data from 201 to 40 as the lower data.
Lower data bus 703 for transferring data for 0 rows
(4-parameter input) is input. The same sync bus 7 is used for both scanning and data display on the upper and lower sides.
06 is input, and data for 1 to 400 lines is displayed as a whole by scanning 200 divisions simultaneously on the upper and lower sides.

FIG. 4B is a schematic diagram of a system corresponding to the upper and lower split drive system, which can be enlarged and displayed based on the present invention. Here, the data conversion circuit 708 is the synchronous bus 70.
6, upper data bus 702 and lower data bus 703
, The upper synchronization bus 711, the lower synchronization bus 712,
This is a circuit that outputs the new upper data bus 710 and the lower data bus 709. For example, when the enlarged display is performed from the 20th line, the new upper data bus 711 is the upper data bus 70.
2 and the new upper sync bus 710 remains the conventional upper sync bus 702. On the other hand, the new lower data bus 709 has to become the data of 21 to 220 rows, and therefore the upper data bus and the lower data bus must be switched during the scanning. Therefore, the new lower synchronization bus 709 also needs to shift the timing of the 706 for an appropriate period.

FIG. 5 is a timing chart of the upper display area when the data from the 21st row is doubled.
Here, the new reset signal 123 is a signal generated in synchronization with the 20th clock signal 102 for scanning the 20th row. The output 1 signal 106 and the output 2 signal 107 are simultaneously output in synchronization with the rising edge of the 21st clock signal 102. Hereinafter, the output 41 signal 109 and the output 42 signal 1 are output while simultaneously outputting the odd-numbered and even-numbered output terminals.
10 simultaneously outputs in synchronization with the rising edge of the 41st clock signal 102, and finally the output 119 signal 112 and the output 200 signal 112 are the 120th clock signal 102.
The signals are sequentially output until they are output at the same time in synchronization with the rising edge of. In this case, the data corresponding to the 21st to 120th rows is enlarged and displayed twice in the vertical direction. The new upper data bus 710 is always the upper data bus 702. The output waveform in FIG. 5 is actually a waveform for AC driving to prevent deterioration of the LCD, but is omitted for simplicity.

FIG. 6 is a timing chart of the lower display area when the data from the 21st line is doubled.
Here, the new and new reset signal 804 is the reset signal 103
Is used as the reset signal. 12 based on the reset signal 103
The output 201 signal 406 and the output 202 signal 407 are simultaneously output in synchronization with the rising edge of the first clock signal 102. Hereinafter, the output 241 signal 409 and the output 242 signal 4 while simultaneously outputting the odd-numbered and even-numbered output terminals
10 are simultaneously output in synchronization with the rising edge of the 141st clock signal 102, and finally the output 399 signal 411 and the output 400 signal 412 are the 20th clock signal 102.
The signals are sequentially output until they are output at the same time in synchronization with the rising edge of.

The data control signal 801 corresponds to the upper data bus 7.
02 and a signal for switching the lower data bus 703, which becomes a high level at the rising of the 121st clock signal 102 based on the new and new clock signal 804 and the clock signal 103, and at the rising of the 201st clock signal 102. Become low level. Clock control signal 802
Is a signal for limiting the input clock signal 102, and becomes a high level at the rising edge of the first clock signal 102 with respect to the reset signal 103 and becomes a low level at the rising edge of the 201st signal. The new lower data bus 709 becomes the upper data bus 702 when the data control signal 801 is at the low level, and becomes the lower data bus 703 when it is at the high level.

FIG. 7 is a detailed circuit diagram of a driving unit for displaying the lower side of the data change circuit 708. The second counter circuit 934 is an ordinary binary counter and receives the new clock signal 904 as a clock signal and the new reset signal 123 as a reset signal. The second counter circuit 934 has a total of 8 from Q0 output 935 to Q7 output 942.
The input clock can be counted from 0 to 255 by the terminal output. The NOR2 circuit 950, the AND3 circuit 951, and the AND4 circuit 952 are output decoders of the second counter circuit 934, and Q2 output 937 (4 counts), Q
5 outputs 940 (32 counts), Q6 outputs 941 (64
And that other terminals are low level.

The AND5 circuit 953 is an AND4 circuit 952.
The 120th signal of the clock signal 102 can be detected by ANDing the clock signal 102 with this, and this signal becomes the new / new reset signal 804. FF1 circuit 931
The FF2 circuit 932 is a circuit called a normal flip-flop. The FF1 circuit 931 outputs the data control signal 801 which becomes high level at the rising edge of the new / new reset signal 804 and becomes low level at the rising edge of the decode 201 signal 933. Here, the decode 201 signal 93
Reference numeral 3 is an output when the 201st clock signal 102 is detected by the decoder unit in FIG.

The FF2 circuit 932 is at a high level at the rising edge of the reset signal 103, and is at a low level at the rising edge of the decode 201 signal 933.
Is output. The multiplexer A circuit 954 outputs the lower 0 data 900 as the new lower 0 data 920 when the data control signal 801 is at the low level, and the data control signal 8
When 01 is high level, upper 0 data 910 is new lower 0
It is output as data. Similarly, the multiplexer B circuit 955 to the multiplexer D circuit 957 output the lower one data 901 to the lower one data 901 when the data control signal 801 is at the low level.
Lower 3 data 903 to new lower 1 data 921 to new lower 3
When the data control signal 801 is at a high level, the upper data 1 911 to the upper 3 data 9 are output.
13 is output as new lower side 1 data 921 to new lower side 3 data 923.

The AND6 circuit ANDs the clock control signal 802 and the clock signal 102 to obtain the new clock signal 9
40 is output. By the above, enlarged display is possible.
Further, in the present embodiment, the data display of the 21st to 220th rows has been described, but in the case of the display from the 101st row or more by the new reset signal 123, the same operation for switching the new upper data bus 710 is performed. Circuit is required. For example, when the enlarged display is performed from the 120th row, the new upper data bus 710 must become the data of 121 to 220 rows. Therefore, the upper data bus 702 and the lower data bus 703 must be switched during scanning. I won't. In this case, the new lower data bus 709 remains the lower data bus 703. The reset signal for the lower side remains the new and new reset signal 804.

[0026]

Example 3

[Embodiment 3] Next, an embodiment of a method of determining a display area in the enlargement mode will be described. FIG. 8 is a schematic diagram of the entire personal computer system based on the present invention. The system bus 601 in the figure is a comprehensive bus including address lines, data lines, and control lines. The system circuit 602 is an IBM-XT compliant circuit excluding a display controller, and is an Intel 8088.
It is composed of a central processing unit such as and a memory. The display controller 603 is a display control circuit usually called CGA (color graphic adapter) having a modification degree of 640 columns × 200 rows. The display controller 603 receives the VR via the display bus 614 according to an instruction from the system circuit 602.
Input and output the data contents of AM604, and VRAM60
LCD data 608 and sync signal 6 based on the data of 4
09 is generated.

The VRAM 604 is a display data buffer memory, and an ordinary SRAM (static random access memory) or DRAM (dynamic random access memory) is used. The decoding circuit 605 is the CPU bus 6
This is a decoding circuit that detects an address 200H (hexadecimal 200) in the I / O space at the timing of writing the address in 01 at the I / O space write time and normally sets the low-level decode signal 613 to the high level. Latch gate circuit 606
Is a latch circuit such as 74HC77, and CPU bus 60
Only the lower 2 bits of the data in 1 are latched at the timing when the decode signal 613 is at the high level, and the mode bus 607
Output as.

The reset signal shift circuit 610 delays the reset signal in the synchronizing signal 609 according to the contents of the mode bus 607 and outputs it as a new synchronizing signal 611. When the 0th bit and the 1st bit of the mode bus 607 are both low level, the data corresponding to 1 to 100 rows is displayed, and when the 0th bit is high level and the 1st bit is low level, it corresponds to 21 to 120 rows. Data is displayed. If the 0th bit is low level and the 1st bit is high level, 101
Display data corresponding to ~ 200 lines. The LCD drive circuit 612 is a conventional circuit for inputting the LCD data 608 and the new sync signal 611 to display the LCD.

FIG. 9 is a flowchart of a cursor detection software program in the text mode (80 columns × 25 lines character display). The operation A502 is an operation for detecting the display position of the cursor, and when 03 is assigned to the AH register and the interrupt 10H (hexadecimal 10) which is the display service routine in the BIOS is executed, the contents of the DH register become the cursor. It becomes a display line. This content is substituted into the GYO variable. In judgment A503, if GYO is above the 7th line, operation B508 assigns 0 to the SW variable and operation E
And determination B504 in other cases. If GYO is lower than the 18th line in judgment B504, S is selected by operation C509.
Substituting 2 for the W variable and performing the operation E, and otherwise makes a determination C50.
Do 5.

In the judgment C505, if the OLD_GYO, which is the display line of the cursor one before, is above the 10th line, the operation B is performed.
By this, 0 is substituted for the SW variable, the operation E is performed, and otherwise, the determination D506 is performed. In determination D506, if OLD_GYO, which is the previous cursor display line, is above the 16th line, operation B is performed to substitute 0 for SW variable by operation B, and operation D507 is performed otherwise. In operation D507, 1 is assigned to SW, operation E is performed, and in other cases, determination B504 is performed. In operation E510, the address is output to the address 200H in the I / O space, and GYO is set to OLD_GYO.

Here, in the operation E510, outputting SW to the address 200H in the I / O space means that FIG.
In other words, the decode signal 613 in is set to a high level, the latch gate circuit 606 is opened, and the contents of SW are output to the mode bus. In other words, SW is 0
1 to 100 rows for SW, 21 to 120 for SW 1
When the row and SW are 2, it corresponds to displaying 101 to 200 rows. If this program is added to the interrupt 08H executed at 18 Hz, the display line of the cursor is detected periodically and the optimum display area is enlarged and displayed. Although this time, the cursor is used in the text mode, the display area can be changed by the same method for the input position of the mouse cursor or the like in the graphic mode.

[0032]

When the liquid crystal display device is constructed as in the present invention, the power consumption is reduced because the number of clock frequencies is low during the enlarged display. Further, even in the liquid crystal display device of the vertically divided drive, the image can be enlarged and displayed without discontinuity of the image at the boundary. Further, by combining this liquid crystal display device with a personal computer system provided with means for selecting a region to be enlarged and displayed, a display system that is easy to use and has a wide range of applications can be made.

[Brief description of drawings]

FIG. 1 is a timing chart of the first embodiment in a normal mode.

FIG. 2 is a timing chart of the first embodiment in the case of an expansion mode.

FIG. 3 is a circuit block diagram of the first embodiment.

FIG. 4 is a schematic view of a vertical split drive LCD according to a second embodiment.

FIG. 5 is an upper timing chart of the second embodiment.

FIG. 6 is a lower timing chart of the second embodiment.

FIG. 7 is a data change circuit diagram of the second embodiment.

FIG. 8 is a circuit block diagram of a third embodiment.

FIG. 9 is a flowchart of the third embodiment.

[Explanation of symbols]

 102 clock signal 103 reset signal 106 output 1 signal 120 multiplexer circuit 123 new reset signal 302 Y counter circuit 315 CKS 708 data change circuit 709 new lower data bus 502 operation A 510 operation E 605 decode circuit 606 latch gate circuit 804 new new reset signal

Claims (3)

[Claims] 1. A liquid crystal pixel arranged in a matrix and a drive circuit for driving the liquid crystal pixel, wherein a plurality of the liquid crystal pixels are electrically connected in parallel to enlarge the size of a display unit pixel and to increase the enlargement ratio. A liquid crystal display device having a function of enlarging and displaying display data by lowering the number of time divisions accordingly, wherein the clock frequency of the drive circuit is lowered according to the number of time divisions. 2. A liquid crystal display device in which liquid crystal pixels arranged in a matrix are divided into an upper block and a lower block, and pixels on both sides can be driven separately, and a plurality of liquid crystal pixels are electrically arranged in parallel in each block. A unit for connecting and enlarging the size of the display unit pixel and reducing the number of time divisions according to the enlarging ratio to enlarge and display the display data and a signal changing circuit for transferring the data signal of one block to the other block are provided. A liquid crystal display device, wherein a data signal of one block is displayed on the other block via the signal changing circuit according to a display section during enlarged display. 3. The liquid crystal display device according to claim 1, a system circuit including a central processing unit and a memory, an image data holding device for storing display data output from the system circuit, and the liquid crystal display. A display area selection circuit for determining a display area to be displayed on the device in accordance with a display area selection signal is provided, and an address holding a display indicating that the system circuit is waiting for input is set to an address of the system circuit. A display system characterized in that the display area selection signal is output to the display area selection circuit for searching the inside of the image data holding device according to a program and displaying the contents of the address on the liquid crystal display device.