JPH0627784B2 - IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] The present invention reduces the number of unused pins (dead pins) when testing an IC (semiconductor integrated circuit), and achieves high precision and flexibility by integrating functions for each pin. I tried to get Tay
The present invention relates to a C test device.

[Background of the Invention]

Conventionally, a test pattern has been stored in a large-capacity buffer memory for a logic LSI (large-scale integrated circuit) and is generated from the buffer memory by a sequence controller that controls the generation order of the test pattern. There is known an IC test apparatus which applies a test pattern to an IC under test to perform a test.

A block diagram of an example of such a conventional IC test apparatus is shown in FIG.

This conventional apparatus includes a sequence pattern generator 3 including the above pattern buffer memory and a sequence controller, an algorithmic pattern generator 2 for testing a memory section in a logic circuit, and a clock signal to these pattern generators. Rate signal 10A and IC under test
Timing signal 1 for generating a phase signal 10B for generating a waveform to be applied to the output, output 12 of the sequence pattern generator 3 and output 1 of the algorithmic pattern generator 2.
Selector 1 for selecting 1, waveform data 5 for generating an applied signal waveform to the IC under test from the selected and output pattern data 13 and the phase signal 10B described above, and a driver for sending a signal 14 to the IC under test 6, IC under test
Of the response signal waveform 15 from the analog comparator 7 for generating the logic signal (1,0) output 16 and the response output 16 of the IC under test converted to the logic level and the test pattern generated as the test pattern. A logical comparator 8 that compares the expected value 13 with the expected value to determine whether the response output is good or bad, and an output that is a failure (fail) as a result of comparison with the expected value, an applied test pattern at that time, and the like are stored and It is composed of a file memory 9 used for the operation mode analysis of the above.

In such a conventional IC test apparatus, first, the IC to be tested is
Prepare the driver 6 and the analog comparator 7 for the number of pins of
If the IC under test includes a memory, the output pin of the driver 6 which can be output by the algorithmic pattern generator 2 and the memory output data are input so that the algorithmic pattern can be applied for the memory test. The analog comparator 7 is connected to the memory access pins (address input, data input, data output,
Read / write control input, etc.).

The remaining pins of the IC under test are the drivers 6 and 6, respectively.
Although it is connected to the analog comparator 7, in general, the test apparatus has a driver 6 and an analog comparator 7 for each pin, and switching of input / output is performed according to the signals from the pattern generators 2 and 3. Is often used as a so-called I / O pin structure.

The IC under test is connected to the test apparatus as described above, and after the test is started, the test pattern from the sequence pattern generator 3 or the algorithmic pattern generator 2 is waveform-shaped by the phase signal 10B from the timing generator 1. The signal 14 is input to the IC under test, and its response signal 15 is sent to the logical comparator 8 for acceptability judgment via the analog comparator 7, and the result is stored in the fail memory 9.

Now, consider a gate array having a built-in memory as an IC under test.

FIG. 2 is a pin configuration diagram of a typical gate array for a 28-pin gate array having a built-in memory section and a logic section around it. Fig. 2
The gate arrays of (a) and (b) have the same number of pins,
The pin configuration is completely different depending on the position of the memory and the circuit configuration of the logic section. Therefore, in the conventional IC test apparatus shown in FIG. 1, when a gate array, which has a very large variety of pins in a pin configuration, is to be tested, the allocation of the algorithmic pattern output pins is determined. It is necessary to prepare an extremely large number of puff performance boards for mounting the test ICs and connecting them to the ICs to be tested in accordance with the number of ICs to be tested. Therefore, the setup time and labor are increased, and the total throughput of the test apparatus is reduced.

On the other hand, one set of the pattern generators 2 and 3 simultaneously accesses each driver for each pin of the test apparatus. Therefore, when testing the IC under test with the number of pins equal to or less than the number of pins possessed by the test apparatus, the remaining pins that are not connected to the IC under test remain unused as dead pins.

For example, in a test apparatus having a 200-pin channel (a so-called I / O channel in which a driver and an analog comparator are a set), when testing a 120-pin IC under test, the remaining 80 channels are tested. Is a dead channel, and the pin utilization rate is 120
/200=0.6 (60%). In other words, 40% of the test equipment is idle.

In recent years, the tendency of increasing the number of pins per LSI requires a test apparatus to have a multi-pin (multi-channel) configuration.
It is difficult to maintain a high pin utilization rate because the number of I pins has been varied.

Therefore, as a method of using the test apparatus for improving the pin utilization rate, there is a method of simultaneously testing a plurality of the same product types. That is, it is easily conceivable that if the test device is an IC to be tested with 200 channels and 50 pins, up to four ICs can be tested simultaneously. However, L for logic
When targeting an SI, in particular, an LSI with a built-in clock commonly called a one-chip microcomputer, it is necessary to operate the test device in synchronization with the clock output from the IC under test. In the configuration of the conventional test apparatus, since there is only one timing generator that controls the synchronization, even if the number of pins is satisfied, the above-mentioned 4
It can be seen that it is not possible to carry out the simultaneous test of 150 pieces, and 150 of the 200 pins become dead pins.

As mentioned above, the two points of the pin allocation for testing the memory in the logic and the problem of the pin utilization rate have been described. However, the above two problems are combined with the simultaneous testing of a large number of LSIs for the logic built-in memory. It is inevitable that there will be problems in this form.

[Object of the Invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to perform a test of a memory / logic mixed LSI having an arbitrary number of pins, or a simultaneous test of a memory LSI and a logic LSI, and at the same time timing timing signal accuracy. Further, it is an object of the present invention to provide an IC test apparatus capable of improving the pin utilization rate by preventing the generation of unused pins, easily setting the number of pins arbitrarily.

[Outline of Invention]

The IC test apparatus according to the present invention provides a sequence control means for generating data / control signals corresponding to a desired number of ICs under test and a data / control signal output to a test unit in which the functions are integrated for each arbitrary pin. The IC to be tested is provided with a signal selecting means that can be assigned.
By providing a test unit corresponding to each pin of, the timing signals can be set easily, and the timing signal distribution is improved by simplifying the timing signal distribution to the minimum. Within the range of the number of pins that the test equipment has, different types (number of pins,
By making it possible to simultaneously test a plurality of ICs (having different functions), it is possible to minimize the occurrence of dead pins and improve the pin utilization rate.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

First, FIG. 3 is a block diagram of an embodiment of the IC test apparatus according to the present invention.

Here, 21 is a control unit, 22-1 to 22-3 are timing generators (rate generators) related to the sequence control means,
23-1 to 23-3 are also sequence controllers, 24 is a register, 25 is a signal selecting means, 26-1 to 26-n are multiplexers for forming signal selecting signals, 27-1 and 27-2.
7-n is a test unit, and 28 to 34 are various signals related to the above-mentioned devices.

In this embodiment, a plurality of sets (three sets in FIG. 3) of timing generators (rate generators) 22-1, 22-2, 22-3 are provided.
And sequence controller 2 for generating test patterns
3-1, 23-2, 23-3, and output data and control signals thereof are supplied to the test units 27-1 to 27-n (n is the number of pins for testing) via the signal selecting means 25. , And the three ICs under test ₁ , IC ₂ , IC ₃ having different numbers of pins and different functions can be tested at the same time.

Therefore, each of the test units 27-1 to 27-n is provided with a test pattern buffer memory, a phase generator required for waveform shaping, and a phase generator independently for each test pin.
This is a module with a built-in arithmetic unit, a driver, and an analog comparator for generating patterns in the algorithm.

On the other hand, sequence controllers 23-1, 23-2, 23-3
Read test pattern control signals 28-1, 28-2 from timing (rate) generators 22-1, 22-2, 22-3 according to the contents described in the microprogram. , 28-3 in synchronization with the test units 27-1 to 27-
It is also called a vector generator because it outputs the address of the pattern buffer memory in n and the operation execution control memory.

The signal selecting means 25 includes test units 27-1 to 27-.
n is provided as an input section for each test unit 2
It is configured by multiplexers 26-1 to 26-n provided corresponding to 7-1 to 27-n.

The multiplexers 26-1 to 26-n select any one of the data from the sequence controllers 23-1, 23-2 and 23-3 and the control signals 29-1, 29-2 and 29-3. Is. The selection signal 31 outputs which sequence controller output and which test unit 27-1 to 27-n.
Before the test, or in the middle of the test as needed, whether to connect to is provided as an output signal of the register 24 that stores the control signal 30 from the control unit 21 that controls the entire test apparatus. Thereby, a plurality of ICs under test IC _{1 to} IC
₃ , the plurality of sequence controllers 23-1 to 23-3
The test units 27-1 to 27-n controlled by can be arbitrarily allocated.

Next, FIG. 4 is a block diagram of an embodiment of the test unit in FIG. 3, showing the test unit 27-2 in FIG. 3 as an example.

Here, 35 is a phase generator, 36 is a pattern buffer memory, 37 is a condition set memory, 38 is an operation unit, 39 is a selector, 40 is a driver, 41 is an analog comparator, 42 is a decision unit, and 43 is File storage memory, 44 is a controller, 45-53, 53A, 54-
Reference numeral 59 is a signal relating to each of the above devices.

At the selection output 32-2 from the multiplexer 26-2 in the signal selecting means 25 shown in FIG. 3, the control signals from the sequence controllers 23-1, 23-2 and 23-3 (all having the same configuration). , Including the rate signals from the timing generators (rate generators) 22-1 to 22-n,
The address 46 of the pattern buffer memory 36, the operation execution instruction memory address 48 in the arithmetic unit 38 for generating the algorithmic pattern, and the logic condition for setting the memory peripheral memory when testing the IC for the memory built-in logic There are an address 47 to a condition set memory 37 which stores data, a control signal 45 to a face generator 35 which generates a control signal to a waveform formatter which performs timing waveform shaping on pattern data, and the like.

In the test unit 27-2 of this embodiment in which the functions are integrated for each pin, the pattern buffer memory 36 for generating the sequential pattern and the algorithmic pattern are generated as the source of the test pattern as described above. There is provided an arithmetic unit 38 for carrying out the above, and a condition set memory 37 for generating a memory test condition pattern in the IC under test in which the memory and the logic are mixed, and depending on the role as a pattern unit, Any one of the devices is selected by the selector 29. The selection of the pattern generation may be performed only before the start of the test, or may be switched in real time during the test.

This switching is carried out when one of the control signals 59 from the controller 44 in the main test unit is used based on the control signal 30 from the control unit 21 or the control output 32-2 from the sequence controller is used. In particular, the latter is used for real-time switching.

The selector 39 has a function of selecting pattern data, and also waveform shaping (waveform format) of the selected pattern data in response to the phase signal 49 from the phase generator 35.
It has a built-in waveform format.

The test pattern signal from the waveform formatter is O
It is sent as an applied signal 55 (34-2) to the IC under test through the driver 40 capable of N / OFF (connection / disconnection).
If this pin is an input pin that receives a response signal from the IC under test, the driver 40 is turned off by the driver ON / OFF signal 54 from the waveform formatter, and its response signal 34-2 is an analog comparison. It is input to the device 41 and converted into a logic signal 56.

Here, the determiner 42 that performs the pass / fail determination uses the logic signal 56.
And the applied signal (corresponding to the output 53 from the formatter in the selector 39 in this unit) applied from another test unit, the delay time until the response signal from the IC under test ₁ is returned. The expected value data 53A given in consideration are compared, and a pass / fail judgment result (generally a fail result) 57 is output.

Then, the fail data 57 is stored in the fail storage memory 43, and a failure analysis is performed by the control unit 21 of the test apparatus.

In this case, this test unit 27-2 is the IC to be tested.
_If the response data from the memory (or the memory unit) is 1, the storage data 5 to the file storage memory 43
Since it is desired that 7 is stored at an address corresponding to the memory address given to the IC under test ₁ , not only this test unit 27-2 but also the memory (or memory section) of the IC under test ₁ is tested. The address 58 is input to the file storage memory 43 from another test unit which supplies the address. In addition,
Since the test unit 27-2 serves as a supply source of an address to the memory (or memory section) of the IC under test ₁ , the expected value data 53A can be output to the outside as the address data. There is.

As described above, the test unit has its functions integrated, and the controller 44, which is a means for controlling the internal control and the data transfer with the outside, is
A microsequencer controlled by a microprocessor or microprogram can be used.

In addition, for the purpose of improving the timing accuracy, the phase generator for each test unit enables adjustment of the timing skew for each pin. That is, an analog comparison is made of the skew between the test units of the pattern data sent from the driver 40, the skew due to the difference in various waveform formats, the skew caused by the ON / OFF of the driver 40, and the response signal from the IC under test _1. In the past, a programmable delay circuit has been arranged at each required location in order to prevent a skew that occurs when the converter 41 converts to a logic level, but in the present embodiment, measurement is made beforehand for each test rate. This is to enable generation of a phase signal in which the skew correction described above is added.

Further, the judgment output 57 from the pass / fail judgment unit 42 is given to the phase generator 35 so that the generation of the face signal can be controlled during the timing measurement such as the skew measurement or the delay measurement of the IC under test _1. There is.

This pass / fail judgment result and the number of files are the I
Although not shown in the drawing as the pass / fail judgment information of C, the sequence controller 23-1 which manages its own test unit from the judge 42 or the fail memory 43.
It is also possible to feed back to 23-3 and use them for sequence control. Of course, this feedback can also be performed via the controller 44.

The arithmetic unit 38, which generates an algorithmic pattern for each pin, uses another test unit (for example, 27-) which is higher or lower than the main test unit 27-2.
1 or 27-3) and carrier delivery signal 33-
It also sends and receives 1, 33-2. This signal is weighted for each bit like a memory address as data, and is processed as one set.

Finally, FIG. 5 is a block diagram of an embodiment of the arithmetic unit in FIG.

Here, 60 is a controller, 61 is a control memory, 6
Reference numerals 2 and 63 are data storage registers, 64 and 65 are multiplexers, 66 and 67 are arithmetic units, 68 and 69 are registers, 70 is a multiplexer, and 71 to 81 are various signals related to the above-mentioned devices.

The calculation unit 38 is a sequence controller 23-1 to 23-.
From the control memory 61, which receives the control signal 48 from the controller 3 to instruct the arithmetic control, the data storage registers 62 and 63 which store the data given from the control memory 61, and the data from the registers 62 and 63 and the control memory 61. Multiplexers 64 and 65 for switching to the direct data of
Arithmetic units 66 and 67, registers 68 and 69 for storing output data thereof, and a multiplexer 70 for selecting output data 79 and 80 from the registers 68 and 69.
And the arithmetic units 66, 67 and other registers,
The controller 60 controls the multiplexer. The controller 60 controls the delivery of carrier delivery signals 33-1 and 33-2 to / from another test unit. Also, the multiplexer 7
Output data 52 from 0 is input to the selector (formatter) 39 described with reference to FIG.

In this embodiment, the arithmetic units 66 and 67 are mainly used to
The operation parts of the set are configured in parallel.
Can be used separately for addresses and data. That is, when performing address multiplexing as in the case of a dynamic memory, the left and right sides of the operation part in FIG. 5 are individually used for the operation of the X address and the Y address. When the address and data are multiplexed as in the microprocessor, the left and right are individually used for address and data operations.

Although the configuration of the test unit for consolidating the functions has been described above, in order to achieve the object of the present invention, the phase generator 35 and the arithmetic unit 38 for generating the algorithmic pattern are the rate generator and the sequence generator, respectively. It can also be realized by a configuration integrated with the controller.

Further, in the embodiment shown in FIG. 3, as the sequence control means, three sets each including three timing generators 22-1 to 22-3 and sequence controllers 23-1 to 23-3 are used. As an example, a plurality of sequence controllers, for example, three sequence controllers are subordinated to one timing generator,
Further, even if a plurality of, for example, two sequence controllers are subordinate to each of the plurality of timing generators so that the plurality of sequence controllers are integratedly controlled by one timing generator, Of course, the same test as the above-mentioned embodiment of the present invention can be performed. Furthermore, it is also possible to perform coordinated control of the sequence controllers in synchronization with each other. According to this structure, in addition to the test execution of a plurality of ICs under test by the plurality of sets of sequence control means described above, an LSI provided with a plurality of chips in one device called a multi-chip device. Each of the chips in question is tested with an individual sequence controller, and even with one chip device, for example, the memory part and the logic part of the gate array shown in FIG. 2 are tested with individual sequence controllers. Further, it becomes possible to test and execute a large number of identical LSIs in parallel by one set of sequence control means.

As described above, one set or a plurality of sets of timing generators,
Since the combination of signals from the sequence controller (which may include an algorithmic pattern generator) can be distributed arbitrarily to the pin-corresponding test unit, the following effects can be obtained.

(1) The occurrence of dead pins can be suppressed to a minimum.

(2) It is possible to simultaneously test a plurality of ICs of the same type, different types of ICs such as memories having different test rates and test patterns, different types of ICs such as logic, and memory / logic composite ICs.

(3) As a result, one test device can function as a plurality of test devices, resulting in extremely high investment efficiency. This is because the price of one set of the combination of the timing generator and the sequence controller is far cheaper than the price of one set of the test apparatus of the full system.

(4) Even in the test system in which the test device is synchronized with the clock from inside the IC, it is possible to test a plurality of ICs at the same time, which improves the test throughput of so-called one-chip microcomputers.

(5) Puff performance boards can be used in common even for multi-product ICs such as gate arrays.

(6) By integrating functions for each pin, pin expandability and
The expansion does not impair the timing accuracy, and standardization can reduce the cost of the test apparatus.

(7) By enabling simultaneous testing of a wide variety of ICs,
One test device can be shared for engineering and production.

(8) By providing a redundant test unit, the internal controller 44 performs self-diagnosis for each test unit, and when the abnormality is detected, the control unit 21 of the test apparatus is used to change the connection of the test unit to reduce the downtime. It becomes possible to do so.

〔The invention's effect〕

As described above in detail, according to the present invention, it is possible to simultaneously test a memory / logic mixed LSI having an arbitrary number of pins, or a memory and a logic LSI, and prevent the occurrence of dead pins. In addition, since it is possible to realize an economical IC test device that can improve the pin utilization rate,
Along with the economicalization of the test equipment, remarkable effects can be obtained in improving the efficiency, precision and flexibility of the LSI and IC tests.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a conventional IC test apparatus, FIG. 2 is a pin configuration diagram of a typical gate array, and FIG. 3 is a block diagram of an example of an IC test apparatus according to the present invention. 4, FIG. 4 is a block diagram of an embodiment of the test unit in FIG. 3, and FIG. 5 is a block diagram of an embodiment of the arithmetic unit in FIG. 21 ... Control unit, 22-1 to 22-3 ... Timing generator, 23-1 to 23-3 ... Sequence controller, 24
...... Register, 25 ...... Signal selection means, 26-1 to 26
-N ... multiplexer, 27-1 to 27-n ... test unit, 28 to 34 ... various signals, 35 ... phase generator, 36 ... pattern buffer memory, 37 ...
Condition set memory, 38 ... Calculation unit, 39 ...
... Selector, 40 ... Driver, 41 ... Analog comparator, 42 ... Judgment device, 43 ... File storage memory, 4
4 ... Controller, 45-59 ... Various signals, 60 ...
... Controller, 61 ... Control memory, 62, 63 ...
Data storage memory, 64, 65 ... Multiplexer, 6
6, 67 ... Operation unit, 68, 69 ... Register,
70 ... Multiplexer, 71-81 ... Various signals.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiko Hayashi, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Institute of Industrial Science (72) Inventor Shinya Niizaki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Banchi Co., Ltd. Hitachi, Ltd., Production Engineering Laboratory

Claims (7)

[Claims] 1. A test unit in which at least a function for storing a test pattern and a function for generating a pattern in an algorithmic manner are integrated for each pin of an IC under test, and each test pattern corresponding to each of a plurality of ICs under test. IC test comprising sequence control means for generating data / control signals according to the above, and signal selection means for allocating / distributing the data / control signal output generated by the sequence control means to each of the above test units. apparatus. 2. The sequence control means according to claim 1, wherein the sequence control means includes at least one timing generator for generating a desired test rate signal and the test unit in synchronization with the test rate signal. And a plurality of sequence controllers for generating data / control signals for reading the test pattern in I.
C test equipment. 3. The signal selecting means according to claim 1, wherein said signal selecting means is composed of respective multiplexers for distributing data / control signals from respective sequence controllers to respective test units according to the selecting signals. Is I
C test equipment. 4. The IC test apparatus according to claim 1, further comprising a phase generator for generating a phase signal of at least one edge for each test unit corresponding to each pin of the IC under test. 5. The test unit according to claim 1, claim 2, claim 3, or claim 4, wherein the test unit determines its test pattern according to the test content of the pin of the corresponding IC under test. Pattern buffer memory to store,
Similarly, a condition set memory that stores data for setting the logic condition of the IC under test, and an arithmetic unit that similarly generates an algorithmic pattern,
A selector that selects one of the outputs of the above three devices and outputs it as a test applied signal and outputs an expected value data signal based on a phase signal is compared with the expected value data and a response signal to the test applied signal. An IC test apparatus comprising a judging device for outputting a pass / fail judgment result and a fail storage memory for storing the pass / fail judgment result. 6. The arithmetic unit according to claim 5, wherein the arithmetic unit of the test unit stores a control memory for instructing arithmetic control based on a control signal, and data supplied from the control memory. An IC comprising a data storage register, a multiplexer for switching the data and the data from the control memory, an arithmetic unit for performing a desired arithmetic operation on the output data, and a register for storing the output data. Test equipment. 7. The apparatus according to claim 6, wherein the arithmetic section of the arithmetic section comprises a plurality of sets each including a data storage register, a multiplexer, an arithmetic unit and one register. An IC test apparatus which is configured so that each output from the register can be selected and used according to a desired use such as address / data distinction or address division.