JPH06275823A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device which suppresses punch-through, has a short channel effect, has a small substrate bias effect, has a high junction breakdown voltage at the source and drain, and has a small junction capacitance. A semiconductor substrate 1 of a first conductivity type, a gate insulating film 2 formed on the surface of the semiconductor substrate 1, and a gate electrode 3 selectively formed on the surface of the gate insulating film 2.
Source and drain regions 6s and 6d of the second conductivity type selectively formed on the semiconductor substrate 1 on both sides of the gate electrode 3, and the source and drain regions 6s and 6s.
6d and insulating regions 4s and 4d selectively formed near the bottoms of the source and drain regions 6s and 6d below both ends of the channel region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have become more and more miniaturized due to higher integration, and it is becoming difficult to maintain the characteristics thus far. In a conventional semiconductor device, a depletion layer extending from a source and a drain is connected, and a short circuit between the source and the drain (punch through phenomenon) is a major obstacle.

An example of a conventional semiconductor device will be described below with reference to the drawings. FIG. 3 shows a conventional semiconductor device,
In particular, it shows a method of manufacturing an n-channel MOS type semiconductor device. First, after performing the element isolation process on the p-type semiconductor substrate 1, in order to form the punch through stop region 7,
Ion implantation B1 (here, boron) is performed, and then the gate insulating film 2 is formed (FIG. 3A).

Next, after depositing a polysilicon film, etching is performed to form the gate electrode 3, and the LDD region (n ⁻
In order to form layers 5s and 5d, low-concentration ion implantation B2 (here, phosphorus) is performed using the gate electrode 3 as a mask (FIG. 3B). After that, the CVD-SiO ₂ film 17 is deposited (FIG. 3C). Then, the CVD-SiO ₂ film 1
7 anisotropically etched to form a CVD-
The SiO ₂ film 17 is removed, and CV is applied to the peripheral portion of the gate electrode 3.
Sidewalls 18 are formed by the D-SiO ₂ film 17 (FIG. 3D).

Next, in order to form the original source and drain regions (n ⁺ layers) 6s and 6d, the gate electrode 3 is formed.
And high-concentration ion implantation B3 (arsenic here) is performed using the sidewall 18 as a mask (FIG. 3E). At this time, the side wall 18 made of the CVD-SiO ₂ film 17 is formed.
Prevents ion implantation into the surface of the semiconductor 1 and LD is provided between the source and drain regions (n ⁺ layers) 6s and 6d and the channel.
The D regions (n ⁻ layers) 5s and 5d are left.

Finally, heat treatment is performed to form an n-channel LDD structure MOS type semiconductor device having a punch through stop region 7 shown in FIG. 3 (f). As described above, in the conventional semiconductor device, the punch through stop region 7 is used.
With this, the depletion layer spreading from the source and drain is suppressed, the short circuit between the source and the drain is prevented, and the short channel effect is suppressed.

On the other hand, p using an n ⁺ polysilicon gate
The channel MOS type semiconductor device uses a buried channel structure of the same conductivity type as the source and drain regions. However, with such an embedded structure, the source
Punch-through between drains easily occurs, and p ⁺
When the source and drain regions are formed by normal boron, the diffusion coefficient of boron is large, and the source and drain junction depth is increased in addition to the lateral intrusion from the gate end. is there.

Therefore, in order to deal with the above problem,
As disclosed in Japanese Patent Laid-Open No. 3-138951, FIG.
Thus, a p-channel MOS type semiconductor device having a structure using such an EPS (Effective Punchthrough Stopper) has been obtained. FIG. 4 shows a method for manufacturing a conventional semiconductor device, particularly a p-channel MOS type semiconductor device.

First, an element isolation step is performed on the n-type semiconductor substrate or the n-well 1, a p-type buried channel 8 is formed, then a gate insulating film 2 is formed, and then a polysilicon film is deposited. The gate electrode 3 is formed by etching (FIG. 4A). Next, the EPS area (n
^In order to form the ⁺ layers) 9s and 9d, low-concentration ion implantation A1 (here, phosphorus) is performed using the gate electrode 3 as a mask (FIG. 4B). Here, the ion implantation uses a large-angle ion implantation method.

After that, a CVD-SiO ₂ film 17 is deposited (FIG. 4C). Then, the CVD-SiO ₂ film 17 is anisotropically etched to form the CVD-Si formed on the flat portion.
The O ₂ film 17 is removed, and CVD-formed on the periphery of the gate electrode 3.
Sidewalls 18 made of SiO ₂ film 17 are formed (FIG. 4D). Next, in order to form the source and drain regions (n ⁺ layers) 6s and 6d, the gate electrode 3 is formed.
Then, high-concentration ion implantation B3 (here, B (boron or BF ₂ ) is performed using the sidewall 18 as a mask (FIG. 4E)).

Finally, heat treatment is performed to form p having an EPS region.
A channel MOS type semiconductor device is formed. As described above, in the conventional EPS type MOS semiconductor device, E
With the structure having the PS region, the EPS regions (n ⁺ layers) 9s and 9d play a role of suppressing the spread of the depletion layer from the source and the drain, and have the effect of suppressing the short channel effect and the punch through phenomenon. Have.

[0012]

However, the above structure has the following drawbacks. (1) If a high-concentration punch-through stop region is provided under both ends of the channel portion (positions near the bottoms of the source and drain), the threshold voltage V _{t of the} semiconductor device fluctuates due to the potential difference between the source and the substrate. (Shift higher)
Due to the effect of the substrate bias, the semiconductor device cannot be turned on.

(2) Punch through stop area and EPS
A high-concentration impurity region such as a region is in contact with source and drain regions having different conductivity types, so that the junction breakdown voltage is lowered. (3) The spread of the depletion layer on the junction surface is suppressed, the junction capacitance increases, and the operating speed decreases.

In view of the above problems, the present invention is a high-performance semiconductor which suppresses punch-through, has a short channel effect, has a small substrate bias effect, has a high junction breakdown voltage at the source and drain, and has a low junction capacitance. An apparatus and a manufacturing method thereof are provided.

[0015]

According to another aspect of the present invention, there is provided a semiconductor device, wherein a semiconductor substrate of a first conductivity type, a gate insulating film formed on a surface of the semiconductor substrate, and a surface of the gate insulating film are selected. Of the second conductive type selectively formed on the semiconductor substrate on both sides of the gate electrode, and both ends of the channel region between the source and drain regions. And an insulating region selectively formed near the bottom of the source and drain regions.

A method of manufacturing a semiconductor device according to claim 2 is
A step of forming a gate electrode on a gate insulating film formed on a portion of the surface of the first conductivity type semiconductor substrate to be an active region of the semiconductor device, and ion implantation by tilting the surface of the semiconductor substrate using the gate electrode as a mask. A step of forming an insulating region, a step of forming a second conductivity type source and drain region by performing ion implantation using the gate electrode as a mask, and then an insulating region and a second conductivity type source and drain region. And a step of heat-treating the semiconductor substrate on which is formed.

A method of manufacturing a semiconductor device according to claim 3 is
A step of forming a gate electrode on a gate insulating film formed on a portion of the surface of the first conductivity type semiconductor substrate to be an active region of the semiconductor device, and ion implantation by tilting the surface of the semiconductor substrate using the gate electrode as a mask. And forming an insulating region, using the gate electrode as a mask to tilt the surface of the semiconductor substrate to perform ion implantation to form the first source and drain regions of the second conductivity type, and covering the side surface of the gate electrode. A step of forming an insulating film on the substrate, a step of forming second source and drain regions of the second conductivity type by performing ion implantation using the gate electrode whose side surface is covered with the insulating film as a mask, and then forming an insulating region. And heat treating the semiconductor substrate in which the first and second source / drain regions of the second conductivity type are formed.

[0018]

According to the present invention, the insulating regions provided under the ends of the channel region in the vicinity of the bottoms of the source and drain regions suppress the diffusion of impurities due to the heat treatment at the time of forming the source and drain, and thus the short channel In addition to suppressing the depletion, the depletion layer spreading from the source and drain is suppressed, so punch-through is suppressed and the short channel effect is suppressed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIGS. 1A to 1D are process sectional views showing a method of manufacturing a single drain structure n-type semiconductor device according to a first embodiment of the present invention. This single drain structure n-type semiconductor device has a p-type semiconductor substrate 1 and a gate insulating film 2 formed on the surface of the p-type semiconductor substrate 1, as shown in FIG.
A gate electrode 3 selectively formed on the surface of the gate insulating film 2, and n-type source and drain regions 6s and 6d selectively formed on the p-type semiconductor substrate 1 on both sides of the gate electrode 3. And the source and drain regions 6
Insulating regions 4s and 4d selectively formed at positions near the bottoms of the source and drain regions 6s and 6d below both ends of the channel region between s and 6d.

A method of manufacturing a single drain structure n-type semiconductor device according to the first embodiment of the present invention will be described below with reference to FIG. First, the p-type semiconductor substrate 1 is subjected to an element isolation step, then the gate insulating film 2 is formed, and then a polysilicon film is deposited and then etched to form the gate electrode 3 (FIG. 1A).

Next, in order to form the insulating regions 4s and 4d, ion implantation A1 is performed by the large-angle ion implantation method using the gate electrode 3 as a mask (FIG. 1B). Here, the angle θ formed by the direction perpendicular to the surface of the p-type semiconductor substrate 1 and the ion implantation direction is 20 to 45 so that the implanted ions largely enter the channel region under the gate insulating film 2.
Drive in as a degree. First, vertical to the channel width direction,
In the channel length direction, the p-type semiconductor substrate 1 is tilted so as to enter the source direction (arrow A1 in the solid line in FIG. 1B), and then tilted so as to enter the other drain direction (FIG. 1 (b) dashed arrow A
1 '), achieve the desired ion implantation dose. Here, oxygen is used.

Next, the source and drain regions (n ⁺
In order to form the layers 6s and 6d, high-concentration ion implantation B3 (here, arsenic) is performed using the gate electrode 3 as a mask (FIG. 1C). Finally, heat treatment is performed to form an n-channel single drain structure MOS semiconductor device having insulating regions 4s and 4d shown in FIG. 1 (d).

As described above, according to this embodiment, the insulating regions 4s and 4d are formed symmetrically with respect to the gate electrode 3 by the large-angle ion implantation method, so that the characteristics of the semiconductor device are symmetrical. It is possible to obtain the insulating regions 4s and 4d having a sufficient size for suppressing the depletion layer spreading from the source and drain. Further, it is possible to prevent a short circuit between the source and the drain without increasing the substrate concentration, suppress the short channel effect, reduce the substrate bias effect, reduce the junction capacitance, and realize a high-performance semiconductor device.

The insulating region 4 in the first embodiment is
Although the ions of the ion implantation A1 for forming s and 4d are oxygen, it is needless to say that nitrogen or other ions having an insulating property in the implantation region can be applied. Further, although the first embodiment relates to the n-type semiconductor device, it goes without saying that it can also be applied to the p-type semiconductor device. Further, it goes without saying that the present invention can also be applied to an LDD structure.

[Second Embodiment] FIGS. 2A to 2C are process sectional views showing a method of manufacturing an LDD structure n-type semiconductor device according to a second embodiment of the present invention. As shown in FIG. 2E, this LDD structure n-type semiconductor device has a p-type semiconductor substrate 1 and a gate insulating film 2 formed on the surface of the p-type semiconductor substrate 1.
A gate electrode 3 selectively formed on the surface of the gate insulating film 2, and low-concentration n-type source and drain regions selectively formed on the p-type semiconductor substrate 1 on both sides of the gate electrode 3. 5s and 5d, the same original n-type source and drain regions 6s and 6d, and the source and drain regions 5s, 5d and 6 below both ends of the channel region between these source and drain regions 5s, 5d, 6s and 6d.
Insulating regions 4s and 4d selectively formed near the bottom of s and 6d.

A method of manufacturing an LDD structure n-type semiconductor device according to the second embodiment of the present invention will be described below with reference to FIG. First, an element isolation process is performed on the p-type semiconductor substrate 1, a gate insulating film 2 is formed, and then a polysilicon film is deposited and then etched to form a gate electrode 3 (FIG. 2A).

Next, in order to form the insulating regions 4s and 4d, ion implantation A1 is performed by the large-angle ion implantation method using the gate electrode 3 as a mask (FIG. 2B). Here, the angle θ formed by the direction perpendicular to the surface of the p-type semiconductor substrate 1 and the ion implantation direction is 20 to 45 so that the implanted ions largely enter the channel region under the gate insulating film 2.
Drive in as a degree. First, vertical to the channel width direction,
In the channel length direction, the p-type semiconductor substrate 1 is tilted so that it enters the source direction (solid arrow A1 in FIG. 2B), and then tilted so that it enters the other drain direction (fig. 2 (b), dashed arrow A
1 '), achieve the desired ion implantation dose. Here, nitrogen is used.

After that, in order to form the first source and drain regions 5s and 5d to be LDD regions, ion implantation A2 is performed by the large-angle ion implantation method using the gate electrode 3 as a mask (FIG. 2C). In this case as well, the impurities should enter the channel region under the gate insulating film 2 to a large extent.
The angle between the direction perpendicular to the surface of the p-type semiconductor substrate 1 and the ion implantation direction is set to θ of 20 to 45 degrees.
First, it is perpendicular to the channel width direction and is tilted so as to enter the source direction in the channel length direction, and is implanted into the surface of the p-type semiconductor substrate 1 (solid line arrow A2 in FIG. 2C), and then the other drain. The implant is performed by inclining so as to enter the direction (arrow A2 'of the broken line in FIG. 2C), and the desired ion implantation amount is achieved. Here, phosphorus is used.

After that, a CVD-SiO ₂ film 17 is deposited (FIG. 2 (d)). Then, the CVD-SiO ₂ film 17 is anisotropically etched to form the CVD-Si formed on the flat portion.
The O ₂ film 17 is removed, and CVD-formed on the periphery of the gate electrode 3.
Sidewalls 18 made of SiO ₂ film 17 are formed (FIG. 2E). Next, in order to form the original source and drain regions (n ⁺ layers) 6s and 6d, high-concentration ion implantation B3 (arsenic here) is performed using the gate electrode 3 as a mask (FIG. 2 (f)).

Finally, heat treatment is applied to the insulating regions 4s and 4d.
Forming an n-channel LDD structure MOS type semiconductor device. This embodiment also has the same effect as the above embodiment. Incidentally, in the second embodiment, the insulating regions 4s, 4s
Although the ion of the ion implantation A1 for forming d is nitrogen, it is needless to say that oxygen or other ions having an insulating property in the implantation region can be applied. Further, although the second embodiment relates to the n-type semiconductor device, it goes without saying that it can be applied to the p-type semiconductor device.

Further, as the large tilt ion implantation method, the semiconductor substrate surface is tilted with respect to a plane perpendicular to the ion beam, and the semiconductor substrate is rotated by itself with respect to the beam scanning plane (first and second embodiments). ) In addition, an angle between the surface of the semiconductor substrate and a plane perpendicular to the ion beam is provided, and the rotation angle of the semiconductor substrate for each n times of ion implantation is about 3 times.
It may be an integral multiple of 60 degrees / n.

In the above embodiment, the step of forming an insulating region by tilting the surface of the semiconductor substrate using the gate electrode as a mask, and the step of tilting the surface of the semiconductor substrate using the gate electrode as a mask to perform ion implantation. And a step of forming first source and drain regions of the second conductivity type,
By making the ion implantation angle different,
Although the positions of the source and drain regions are made different, the positions of the insulating region and the first source and drain regions can also be made different by making the implantation angles different and the implantation energy different. .

[0033]

According to the present invention, by forming the insulating region by the large-angle ion implantation method, the insulating region having a sufficient size for suppressing the depletion layer spreading from the source and the drain can be secured. Further, it is possible to prevent a short circuit between the source and the drain without increasing the substrate concentration, suppress the short channel effect, reduce the substrate bias effect, and reduce the junction capacitance.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing a method of manufacturing a conventional single drain structure n-type semiconductor device.

FIG. 4 is a process cross-sectional view showing a method for manufacturing a conventional EPS structure p-type semiconductor device.

[Explanation of symbols]

1 semiconductor substrate 2 gate insulating film 3 gate electrode 4s, 4d insulating region 5s, 6s source region 5d, 6d drain region 17 CVD-SiO ₂ film 18 sidewall

Claims (3)

[Claims] 1. A semiconductor substrate of a first conductivity type, a gate insulating film formed on the surface of the semiconductor substrate, a gate electrode selectively formed on the surface of the gate insulating film, and a gate electrode of the gate electrode. A source and drain region of the second conductivity type selectively formed in the semiconductor substrate on both sides, and a position near the bottom of the source and drain region under both ends of the channel region between the source and drain regions. And an insulating region formed on the semiconductor device. 2. A step of forming a gate electrode on a gate insulating film formed on a portion of a surface of a first conductivity type semiconductor substrate to be an active region of a semiconductor device, and the semiconductor substrate using the gate electrode as a mask. Tilting the surface to perform ion implantation to form an insulating region; ion implantation using the gate electrode as a mask to form second conductivity type source and drain regions; and then the insulating region and the And a step of heat-treating the semiconductor substrate having the second conductivity type source and drain regions formed therein. 3. A step of forming a gate electrode on a gate insulating film formed on a portion of a surface of the first conductivity type semiconductor substrate to be an active region of a semiconductor device, and the semiconductor substrate using the gate electrode as a mask. Inclining the surface to perform ion implantation to form an insulating region, and using the gate electrode as a mask to tilt the surface of the semiconductor substrate to perform ion implantation to form first source and drain regions of the second conductivity type. A step of forming an insulating film so as to cover the side surface of the gate electrode, and performing ion implantation by using the gate electrode whose side surface is covered with the insulating film as a mask,
Of the semiconductor device, and then heat treating the semiconductor substrate on which the insulating region and the first and second source / drain regions of the second conductivity type are formed. Production method.