JPH06275796A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the α-ray soft error resistance of a miniaturized SRAM and improve the operation reliability. A p-type buried layer 19 is provided in the p ⁻ -type well 2 in the region where the transfer MISFETs Qt ₁ and Qt ₂ and the drive MISFETs Qd ₁ and Qd ₂ are formed.
The minority carriers generated by the lines are prevented from entering the memory cell MC, and the transfer MISFETs Qt ₁ , Qt
By not providing the p-type channel stopper region 5 under the field insulating film 4 surrounding t ₂ , the p-type channel stopper region 5 and the p-type buried layer 19 are not overlapped, and the transfer MISFETs Qt ₁ , Qt _{2 are formed.} To prevent the threshold voltage from rising.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an SRAM (Static Random Access Memory).
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having the above.

[0002]

2. Description of the Related Art An SRAM as a semiconductor memory device includes a flip-flop circuit arranged in a region where complementary data lines and word lines intersect with each other and two transfer MISFETs (Metal).
(Insulator Semiconductor Field Effect Transistor)
And constitute one memory cell.

Japanese Unexamined Patent Publication No. 3-234055 discloses that two flip-flop circuits of the above memory cell are used for driving MI.
A so-called complete CMOS structure SRAM composed of an SFET and two load MISFETs is described.

In the SRAM described in the above publication, the gate electrode of the driving MISFET is formed by the first conductive film (polycrystalline silicon film) formed on the main surface of the semiconductor substrate, and is also formed on the main surface of the semiconductor substrate. The second conductive film (polycide film in which a polycrystalline silicon film and a refractory metal film are laminated) is used for transfer M
The gate electrode of the ISFET (and the word line connected to the gate electrode) is formed, and the third conductive film (polycrystalline silicon film) formed above the first and second conductive films is used as the gate electrode of the load MISFET. And the fourth conductive film (polycrystalline silicon film) formed above the third conductive film forms the channel region, drain region and source region of the load MISFET. That is, this SRAM
Has a memory cell having a stack structure in which a load MISFET is formed on a drive MISFET.

By the way, in a semiconductor memory device such as the SRAM described above, in order to suppress a malfunction of a memory cell due to an α ray penetrating into the semiconductor substrate, that is, a so-called soft error, a semiconductor substrate (well) in a memory cell forming region is suppressed. ), A buried type semiconductor region (hereinafter referred to as a buried layer) of the same conductivity type as the well and having a relatively high impurity concentration is provided in a region of a predetermined depth, and minority carriers generated by α rays enter the memory cell. Measures are taken to prevent this. An SRAM having a buried layer of this type is described in Japanese Patent Laid-Open No. 61-97961.

[0006]

DISCLOSURE OF THE INVENTION The inventors of the present invention have miniaturized an SRAM provided with a buried layer as described above.
We found the following problems.

In the case of SRAM, information is written in the memory cell at a write level lower than the power supply voltage (Vcc) by the threshold voltage (Vth) of the transfer MISFET (a state in which a back bias is applied). Be seen. Therefore, in order to secure a large margin of the power supply voltage (Vcc), it is necessary to reduce the threshold voltage of the transfer MISFET including the substrate effect (threshold voltage in the state where the back bias is applied).

The threshold voltage of the above-mentioned transfer MISFET is determined by the impurity concentration of the substrate (well), especially the transfer MIS.
It depends on the impurity concentration of the region where the FET channel is formed, and the higher the impurity concentration, the higher the threshold voltage. Therefore, in order to lower the threshold voltage of the transfer MISFET, it is effective to lower the impurity concentration of the well.

However, as the memory cells of the SRAM are miniaturized, the space between the field insulating films surrounding the transfer MISFET becomes narrower. Therefore, a channel stopper for preventing inversion formed under the field insulating film is formed. One end of the region extends to the well below the transfer MISFET. As a result, the channel stopper region and the buried layer having the same conductivity type partially overlap with each other, and the impurity concentration of the well under the transfer MISFET is increased.

As described above, if an attempt is made to miniaturize the SRAM having the conventional structure in which the buried layer is provided in the well for the purpose of improving the α-ray soft error resistance of the memory cell, the impurity concentration of the well becomes high, and the transfer MISFET has a high impurity concentration. Since the threshold voltage rises, the power supply voltage margin at the time of writing decreases, and the operation reliability of the memory cell deteriorates.

An object of the present invention is to make α of a miniaturized SRAM.
It is to provide a technique capable of improving line soft error resistance.

Another object of the present invention is to miniaturize SRAM.
It is to provide a technology capable of improving the operational reliability of the.

Another object of the present invention is to provide a technique capable of achieving the above object without increasing the number of manufacturing steps of the SRAM.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

The typical ones of the inventions disclosed in the present application will be outlined below.

Transfer MI formed on the main surface of the semiconductor substrate
An SRAM in which a memory cell is composed of an SFET and a flip-flop circuit including a driving MISFET formed on the main surface of the semiconductor substrate and a load MISFET formed on the driving MISFET, wherein the transfer MISFET and the A buried layer having the same conductivity type as that of the semiconductor substrate and having a higher impurity concentration than that of the semiconductor substrate is provided on the semiconductor substrate in the region where each of the drive MISFETs is formed, and the periphery of the region where the transfer MISFET is formed. Under the field insulation film surrounding
The channel stopper region is not provided.

[0017]

According to the above means, by providing the buried layer in the semiconductor substrate in the regions where the transfer MISFET and the drive MISFET are formed, the minority carriers generated by α rays are prevented from entering the memory cell. Therefore, the α-ray soft error resistance of the memory cell can be improved.

Further, since the channel stopper region is not provided under the field insulating film surrounding the region for forming the transfer MISFET, the channel stopper region and the buried layer overlap each other even when the memory cell is miniaturized. Does not occur. Thus, it is possible to prevent the impurity concentration of the semiconductor substrate in the region where the transfer MISFET is formed from rising, so that it is possible to prevent the threshold voltage of the transfer MISFET from rising, and the power supply voltage margin at the time of writing is increased. Can be large.

Further, by providing a buried layer of the same conductivity type as the channel stopper region in the semiconductor substrate in the region where the transfer MISFET is formed, the channel stopper region for inversion prevention is provided under the field insulating film surrounding the region. It is possible to suppress the parasitic MOS effect even without providing.

[0020]

The present invention will be described in detail below with reference to examples. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 2 shows an SRAM according to an embodiment of the present invention.
3 is a schematic configuration diagram (chip layout) of the whole of FIG.
[Fig. 3] is a schematic configuration diagram showing a part of it in an enlarged manner.

The main surface of the rectangular semiconductor chip 1 is not particularly limited, but for example, 4 megabits [Mbit] to 1
An SRAM having a large capacity of 6 Mbits [Mbit] is formed. The memory cell area of this SRAM is composed of four memory blocks LMB, and each memory block LMB is divided into four memory blocks MB.

A load circuit LOAD is arranged at one end of the memory block LMB, and a Y selector circuit YSW, a Y decoder circuit YDEC and a sense amplifier circuit SA are arranged at the other end. In addition, the memory block LM arranged at the leftmost end of the main surface of the semiconductor chip 1
An X decoder circuit XDEC is arranged between B and the memory block LMB adjacent thereto. Similarly, the memory block L arranged at the rightmost end of the main surface of the semiconductor chip 1
Between the MB and the memory block LMB adjacent to the MB, X
A decoder circuit XDEC is arranged. A bonding pad BP is arranged on the outermost peripheral portion of the semiconductor chip 1.

As shown in FIG. 3, the memory block L is
Each of the memory blocks MB obtained by dividing the MB into four is divided into four memory cell arrays MAY.
Further, one word decoder circuit WDEC is arranged in the center of each memory block MB. The word decoder circuit WDEC has a memory cell array MA.
It is selected by the X decoder circuit XDEC via the main word line MWL extending on Y. Further, the word decoder circuit WDEC includes the first sub-word line SWL ₁ or the second sub-word line S extending over the memory cell array MAY.
The first word line WL ₁ and the second word line WL ₂ are selected via WL ₂ . A control circuit CC is arranged at one end of the word decoder circuit WDEC.

A complementary data line DL extends in the direction orthogonal to the first word line WL ₁ and the second word line WL ₂ on the memory cell array MAY. The complementary data line DL includes a first data line DL ₁ and a second data line DL.
It consists of ₂ and. One end of the complementary data line DL is connected to the load circuit LOAD, and the other end is connected to the Y line.
The sense amplifier circuit SA is provided via the selector circuit YSW.
It is connected to the.

The memory cell MC of the SRAM is provided in a region where the first word line WL ₁ and the second word line WL ₂ of the memory cell array MAY intersect the first data line DL ₁ and the second data line DL _2. They are arranged one by one.

FIG. 4 is an equivalent circuit diagram of the memory cell MC. As shown in the figure, the memory cell MC includes a flip-flop circuit and two transfer MISFETs Qt ₁ and Qt.
t ₂ and. This flip-flop circuit is composed of two n-channel type driving MISFEs.
It is composed of TQd ₁ and Qd ₂ and _two p-channel type load MISFETs Qp ₁ and Qp ₂ .
That is, the SRAM memory cell MC of the present embodiment has a complete CMOS structure. The flip-flop circuit is configured as an information storage unit and stores 1-bit information (“1” or “0”). The two transfer MISFETs Qt ₁ and Qt ₂ of the memory cell MC are n-channel type, and one of the source region to the drain region is connected to a pair of input / output terminals of the flip-flop circuit. _One of the source region and the drain region of the transfer MISFET Qt ₁ is connected to the first data line DL ₁ , and its gate electrode is connected to the first word line WL ₁ . One of the source region and the drain region of the transfer MISFET Qt ₂ is connected to the second data line DL ₂ , and its gate electrode is connected to the second word line WL ₂ .

Driving MISFET Qd ₁ and load M
The ISFET Qp ₁ has its drain regions (one input / output terminal of the flip-flop circuit) connected to each other and its gate electrodes connected to each other to form a CMOS. Similarly, the drive MISFET Qd ₂ and the load MISF
The ETQp ₂ has a drain region (the other input / output terminal of the flip-flop circuit) connected to each other and a gate electrode connected to each other to form a CMOS.

Driving MISFET Qd ₁ and load M
Each drain region of ISFETQp ₁ is connected to the other of the source region or the drain region of the transfer MISFET Qt _1, and is connected to the gate electrode of the driving MISFET Qd ₂ and load MISFET Qp _2. Similarly, each of the drain region of the driving MISFET Qd ₂ and load MISFET Qp ₂ is connected to the other of the source region or the drain region of the transfer MISFET Qt _2, and driving MISFET Qd
₁ and the load MISFET Qp ₁ are connected to their respective gate electrodes.

The source regions of the driving MISFETs Qd ₁ and Qd ₂ are connected to the reference voltage (V _SS ), and the source regions of the load MISFETs Qp ₁ and Qp ₂ are connected to the power supply voltage (V _CC ). ing. The reference voltage (V _SS ) is, for example, 0 V (ground potential), and the power supply voltage (V _CC ) is, for example, 5 V.

FIG. 1 is a sectional view of an essential part of a semiconductor substrate showing a specific structure of the memory cell MC.

As shown in FIG. 1, the main surface of a semiconductor substrate (semiconductor chip) 1 made of n ^-- type silicon single crystal has p
^{A −} type well 2 is formed, and a field insulating film 4 made of a silicon oxide film for element isolation is formed on the main surface of the inactive region of the p ⁻ type well 2.

Driving MISF that constitutes the memory cell MC
ETQd ₁ , Qd ₂ , transfer MISFETs Qt ₁ , Qt
₂ and load MISFETs Qp ₁ and Qp ₂ among drive MISFETs Qd ₁ and Qd ₂ and transfer MISF
Each of ETQt ₁ and Qt ₂ is formed on the main surface of the active region of the p ⁻ type well 2 surrounded by the field insulating film 4.

MISFET Qd for driving memory cell MC
Each of ₁ and Qd ₂ is composed of a gate insulating film 6, a gate electrode 7, a source region and a drain region.
The gate electrode 7 is formed in the first-layer gate material forming step and is made of, for example, a polycrystalline silicon film. An n-type impurity (for example, P) is introduced into this polycrystalline silicon film in order to reduce the resistance value.

An insulating film 8 is formed on the gate electrodes 7 of the driving MISFETs Qd ₁ and Qd ₂ . The insulating film 8 is made of, for example, a silicon oxide film. A sidewall spacer 9 is formed on the side wall of the gate electrode 7 in the gate length direction. The sidewall spacer 9 is made of, for example, a silicon oxide film.

The source region and drain region of each of the driving MISFETs Qd ₁ and Qd ₂ are composed of a low impurity concentration n-type semiconductor region 10 and a high impurity concentration n ⁺ -type semiconductor region 11 formed thereabove. ing. That is, each of the driving MISFETs Qd ₁ and Qd ₂ has a source region and a drain region having a so-called double diffused drain structure.

Transfer MISFET Qt of memory cell MC
Each of ₁ and Qt ₂ is composed of a gate insulating film 12, a gate electrode 13A, a source region and a drain region. The gate electrode 13A is formed in the second-layer gate material forming step, and is composed of, for example, a laminated film (polycide film) of a polycrystalline silicon film and a refractory metal silicide film. An n-type impurity (for example, P) is introduced into the lower polycrystalline silicon film in order to reduce the resistance value. The upper refractory metal silicide film is, for example, WSi _x , MoS.
i _x , TiSi _x , TaSi _{x, and the} like.

The insulating film 15 and the insulating film 21 are formed on the gate electrodes 13A of the transfer MISFETs Qt ₁ and Qt _2.
Are formed. The insulating film 15 and the insulating film 21
Is made of, for example, a silicon oxide film. A sidewall spacer 16 is formed on the sidewall of the gate electrode 13A. The sidewall spacer 16 is made of, for example, a silicon oxide film.

The source region and drain region of each of the transfer MISFETs Qt ₁ and Qt ₂ are composed of a low impurity concentration n-type semiconductor region 17 and a high impurity concentration n ⁺ -type semiconductor region 18. That is, the transfer MISF
The source region and the drain region of ETQt ₁ and Qt ₂ have an LDD (Lightly Doped Drain) structure.

_One of the source region and the drain region of the transfer MISFET Qt ₁ is connected to the drive MISFET Qd.
It is configured integrally with the drain region of ₁ . Similarly, one of the source region and the drain region of the transfer MISFET Qt ₂ is formed integrally with the drain region of the drive MISFET Qd ₂ .

The gate electrode 1 of the transfer MISFETQt ₁
The first word line WL ₁ is connected to 3A and the transfer MI is
The second word line WL ₂ is connected to the gate electrode 13A of the SFET Qt ₂ . The gate electrode 13A of the transfer MISFET Qt ₁ is integrally formed with the first word line WL _1, and the gate electrode 13A of the transfer MISFET Qt ₂ is formed.
Are integrally formed with the second word line WL ₂ .

First word line WL ₁ and second word line WL ₂
Between the two driving MISFETs Qd ₁ and Qd ₂
Voltage line 13B configured as a common source line for
(V _SS ) is arranged. Reference voltage line 13B (V _SS )
Is the gate electrode 1 of the transfer MISFETs Qt ₁ and Qt _2.
3A and the word line WL (first word line WL ₁ and second word line WL ₂ ), which is formed in the same second layer gate material forming step and extends on the field insulating film 4 in the same direction as the word line WL. is doing. The reference voltage line 13B (V _SS ) is
Through a contact hole 14 which is opened in the insulating film of the driving MISFET Qd _1, the gate insulation Qd ₂ film 6 and the same layer, connected to the respective source region of the driving MISFETQd _1, Qd ₂ (n ⁺ -type semiconductor region 11) Has been done.

Driving MISF that constitutes the memory cell MC
ETQd _1, Qd ₂ and transfer MISFET Qt _1,
In the p ⁻ type well 2 in the region where each of Qt ₂ is formed, a p ⁺ type buried layer (buried layer) is formed for the purpose of preventing minority carriers generated by α rays penetrating the semiconductor substrate 1 from entering the memory cell MC. Type semiconductor region) 19. This p ⁺ type buried layer 19 is a driving MISF.
ETQd _1, Qd ₂ and transfer MISFET Qt _1,
Each Qt ₂ is provided on the entire surface of the formed active region.

Further, the driving MISFETs Qd ₁ and Qd ₂
A p-type channel stopper region 5 for preventing inversion is provided below the field insulating film 4 surrounding the active region in which is formed. On the other hand, transfer MISFET
Below the field insulating film 4 surrounding the active region in which Qt ₁ and Qt ₂ are formed, a p-type channel stopper region 5 is formed.
Is not provided.

MISFE for two loads of memory cell MC
MISFET Qp for load of TQp ₁ and Qp _2
1 is disposed on the region of the driving MISFET Qd ₂ ,
The load MISFET Qp ₂ is a drive MISFET Qd.
It is located on area ₁ . MISFET for load Qp
Each of ₁ and Qp ₂ is composed of a gate electrode 23A, a gate insulating film 24, a channel region 26N, a source region 26P and a drain region 26P.

The gate electrodes 23A of the load MISFETs Qp ₁ and Qp ₂ are formed in the third layer gate material forming step, and are formed of, for example, a polycrystalline silicon film. An n-type impurity (for example, P) is introduced into this polycrystalline silicon film in order to reduce the resistance value.

Gate electrode 2 of load MISFET Qp ₁
3A is an insulating film 21, an insulating film 8 and an insulating film (transferring M
ISFETQt _1, connected Qt through a contact hole 22 which is opened in the insulating film) of the gate insulating film 12 and the same layer of _2, to one of the source region or the drain region of the gate electrode 7 and the transfer MISFET Qt ₂ of the drive MISFET Qd ₁ Has been done. Similarly, load MISFET
The gate electrode 23A of Qp ₂ is driven by the driving MISFET Qd through the contact hole 22 formed in the insulating film 21, the insulating film 8 and the insulating film (the insulating film of the same layer as the gate insulating film 12 of the transfer MISFETs Qt ₁ and Qt ₂ ). _{The second} gate electrode 7 is connected to _one of the source region and the drain region of the transfer MISFET Qt ₁ .

On top of the other of the source region and the drain region of the transfer MISFETs Qt ₁ and Qt ₂ , a load M is provided.
ISFETQp _1, Qp pad layer 23B which is formed with the gate electrode 23A of ₂ in the same third-layer gate material forming step
Are arranged respectively. The pad layer 23B includes an insulating film 21 and an insulating film (transfer MISFETs Qt ₁ , Qt
The transfer MISFET is formed through a contact hole 22 formed in the gate insulating film 12 at t _{2 (} the same insulating film as the gate insulating film 12).
It is connected to the other of the source region and the drain region of Qt ₁ and Qt ₂ .

Above the gate electrodes 23A of the load MISFETs Qp ₁ and Qp ₂ , the load MISFETs Qp ₁ and
A gate insulating film 24 of Qp ₂ is formed. The gate insulating film 24 is made of, for example, a silicon oxide film.

Above the gate insulating film 24 of the load MISFETs Qp ₁ and Qp ₂ , the load MISFETs Qp ₁ and
A channel region 26N, a source region 26P and a drain region 26P of Qp ₂ are formed. Channel region 2
6N is formed in the fourth layer gate material forming step, and is made of, for example, a polycrystalline silicon film. An n-type impurity (for example, P) is introduced into this polycrystalline silicon film in order to set the threshold voltages of the load MISFETs Qp ₁ and Qp ₂ to the enhancement type.

A drain region 26P is formed on one end side of the channel regions 26N of the load MISFETs Qp ₁ and Qp _{2 and} a source region 26P is formed on the other end side thereof.
The drain region 26P and the source region 26P are formed in the same fourth layer gate material forming step as the channel region 26N, and are integrally formed with the channel region 26N. A p-type impurity (for example, BF) is added to the polycrystalline silicon film in the regions forming the drain region 26P and the source region 26P.
₂ ) has been introduced.

The drain region 26P of the load MISFET Qp ₁ is loaded with the load MISFE through the contact hole 25 formed in the insulating film of the same layer as the gate insulating film 24.
It is connected to the gate electrode 23A of TQp ₂ . Similarly, the drain region 26P of the load MISFET Qp ₂
Through the contact hole 25 formed in the insulating film of the same layer as the gate insulating film 24, through the load MISFET Qp.
It is connected to _one gate electrode 23A.

A power supply voltage line (V _CC ) 26P is connected to the source regions 26P of the load MISFETs Qp ₁ and Qp ₂ . The power supply voltage line (V _CC ) 26P includes a channel region 26N, a drain region 26P and a source region 26.
It is formed in the same gate material forming process as the fourth layer as P, and is integrated with these.

Channel regions 26N, source regions 26P and drain regions 26 of the load MISFETs Qp ₁ and Qp ₂
Each of the sub-word line SWL (first sub-word line SWL ₁ , second sub-word line SWL ₂ ) and main word line MWL shown in FIGS. 2 and 3 is provided above P and the power supply voltage line (V _CC ) 26P. It is made of the first layer wiring material (for example, tungsten).
The complementary data line DL (the first data line DL ₁ and the second data line DL ₂ ) is a second layer wiring material (for example, a metal composed of a three-layer film of a TiW film, an aluminum alloy film, and a TiW film).
However, their illustration is omitted.

Of the complementary data lines DL shown in FIG. 3, the first data line DL ₁ is the transfer MISF shown in FIG.
_One of the source region and the drain region of ETQt ₁ (n ⁺
Type semiconductor region 18) and is connected to the second data line DL
₂ is connected to one of the source region and the drain region (n ⁺ type semiconductor region 18) of the transfer MISFET Qt ₂ . Complementary data line DL and transfer MISFETQ
The connection of t ₁ and Qt _{2 with} the n ⁺ type semiconductor region 18 is made through the pad layer 23B.

Next, an example of a specific method for manufacturing the SRAM will be described with reference to FIGS.

First, a semiconductor substrate 1 made of n ^--type silicon single crystal having a specific resistance value of about 10 [Ω / cm] is prepared, and a part of a formation region of a memory cell MC and a formation region of a peripheral circuit (not shown) are prepared. A p ^- type well 2 is formed in the. Further, an n-type well is formed in another part of the peripheral circuit formation region. The p ⁻ type well 2 is formed by expanding and diffusing ion-implanted BF ₂ into the main surface of the semiconductor substrate 1, and the n-type well is formed by expanding and diffusing ion-implanted P into the main surface of the semiconductor substrate 1. .

Next, p ^- -type well 2 of the active region major surface in the silicon nitride film 20, which as a mask p ^-
BF ₂ for a channel stopper is ion-implanted into the main surface of the non-active region of the mold well 2. At this time, transfer MISFET
In order to prevent BF _{2 from} being ion-implanted into the inactive region surrounding the region where Qt ₁ and Qt ₂ are formed, the main surface of this inactive region (and n-type well) is masked with a photoresist film 27. Ion implantation is performed (FIG. 5).

Next, after removing the photoresist film 27 by ashing, the field insulating film 4 for element isolation is formed by a thermal oxidation method (LOCOS method) using the silicon nitride film 20 as an oxidation resistant mask. At this time, due to the diffusion of BF ₂ , a p-type channel stopper region 5 for preventing inversion is formed under the field insulating film 4 except for the periphery of the region where the transfer MISFETs Qt ₁ and Qt ₂ are formed. afterwards,
The silicon nitride film 20 is removed by etching (FIG. 6).

Next, B and BF ₂ are ion-implanted into the main surface of the active region of the p ⁻ type well 2. B is p
For forming the ⁺ type buried layer 19, for example, 20
It is introduced with high energy of about 0 keV. Also, BF ₂
Is introduced to adjust the threshold voltages of the driving MISFETs Qd ₁ and Qd ₂ .

Next, after cleaning the main surface of the active region of the p ^-- type well 2, the driving MISFETs Qd ₁ and Qd are formed on the main surface.
A gate insulating film 6 of d ₂ is formed. This gate insulating film 6
Are formed by a thermal oxidation method. At this time, due to the diffusion of B, the driving MISFETs Qd ₁ and Qd ₂ and the transfer MISF are formed.
P ^{− of the} region where each of ETQt ₁ and Qt ₂ is formed
A p ⁺ type buried layer 19 is formed in the type well 2 (FIG. 7).

Next, a polycrystalline silicon film which is the first-layer gate material is deposited on the entire surface of the semiconductor substrate 1 by the CVD method.
P is introduced into this polycrystalline silicon film at the time of deposition in order to reduce its resistance value. Next, an insulating film 8 made of a silicon oxide film is deposited on this polycrystalline silicon film by the CVD method. This insulating film 8 is a driving MISFET Q.
The gate electrodes 7 of d ₁ and Qd ₂ are formed to electrically separate the conductive layer formed thereabove.

Next, the photoresist film formed on the insulating film 8 is used as a mask to sequentially etch the insulating film 8 and the polycrystalline silicon film below the insulating film 8 to drive MISFE for driving.
The gate electrodes 7 of TQd ₁ and Qd ₂ are formed. afterwards,
This photoresist film is removed by ashing (FIG. 8).

Next, after depositing a silicon oxide film on the entire surface of the semiconductor substrate 1 by the CVD method, this silicon oxide film is RI.
Etching is performed by anisotropic etching such as E (Reactive Ion Etching) to form sidewall spacers 9 on the sidewalls of the gate electrodes 7 of the driving MISFETs Qd ₁ and Qd ₂ . Next, the gate insulating film 6 on the main surface of the active region of the driving MISFETs Qd ₁ and Qd ₂ except under the gate electrode 7.
Is removed by etching with a dilute hydrofluoric acid aqueous solution, and then a new silicon oxide film is formed on the exposed main surface of the active region by a thermal oxidation method.

Next, a photoresist film is formed on the main surface of the semiconductor substrate 1, and using this as a mask, the driving MISFET is formed.
P is formed on the main surface of the p ⁻ type well 2 in the formation region of Qd ₁ and Qd _2.
Is ion-implanted. Next, after removing the photoresist film by ashing, P introduced into the main surface of the p ⁻ type well 2 is expanded and diffused to form the n type semiconductor region 10 of the driving MISFETs Qd ₁ and Qd ₂ (FIG. 9). .

Next, p ^- after the BF ₂ for threshold voltage adjustment of the type well transfer MISFET Qt ₁ on the main surface of the active region of the 2, Qt ₂ is ion-implanted, the silicon oxide of the main surface of the active region The film is removed by etching with a dilute aqueous solution of hydrofluoric acid, and transfer MISFETQ is formed on the exposed main surface of the active region.
The gate insulating film 12 of t ₁ and Qt ₂ is formed by the thermal oxidation method.

Next, a second-layer gate material is deposited on the entire surface of the semiconductor substrate 1. This gate material is composed of a laminated film (polycide film) of a polycrystalline silicon film and a tungsten silicide film. At this time, first, after depositing a polycrystalline silicon film, a photoresist film is formed on the main surface of the semiconductor substrate 1, and using this as a mask, the driving MISFETs Qd ₁ and Qd ₁ are formed.
insulating film on the n-type semiconductor region 10 of d ₂ (gate insulating film 1
The insulating film of the same layer as 2) is etched to form the contact hole 14. Next, after removing the photoresist film by ashing, a polycrystalline silicon film is further deposited.
This polycrystalline silicon film is formed by the CVD method, and P is introduced at the time of deposition in order to reduce its resistance value. Next, a tungsten silicide film is deposited on the upper layer of this polycrystalline silicon film by the CVD method.

Next, an insulating film 15 made of a silicon oxide film is deposited on the tungsten silicide film by the CVD method. The insulating film 15 is formed by the transfer MISFETs Qt ₁ , Qt.
It is formed to electrically separate the gate electrode 12 at t _{2 and} the conductive layer formed thereabove. Next, the insulating film 15
A photoresist film is formed on the gate of the transfer MISFETs Qt ₁ and Qt ₂ by sequentially etching the insulating film 15 and the second-layer gate material (polycide film) as the lower layer using the photoresist film as a mask. Electrode 13A,
Word line WL (first word line WL ₁ , second word line WL
₂ ) and the reference voltage line 13B (V _SS ) are formed respectively. Then, the photoresist film is removed by ashing (FIG. 10).

Next, a photoresist film is formed on the main surface of the semiconductor substrate 1, and using this as a mask, the transfer MISFET is formed.
P is formed on the main surface of the p ⁻ type well 2 in the formation region of Qt ₁ and Qt _2.
Is ion-implanted. Next, after removing the photoresist film by ashing, P introduced into the main surface of the p ⁻ type well 2 is expanded and diffused, and n of the transfer MISFETs Qt ₁ and Qt ₂ is transferred.
The type semiconductor region 17 is formed.

Next, after depositing a silicon oxide film on the entire surface of the semiconductor substrate 1 by the CVD method, this silicon oxide film is RI.
Etch with anisotropic etching such as E, and transfer M
ISFETQt _1, the gate electrode 13A of the Qt _2, to form the sidewall spacers 16 on the respective side walls of the word lines WL (first word line WL _1, the second word line WL ₂₎ and the reference voltage line 13B (V _SS).

Next, a photoresist film is formed on the main surface of the semiconductor substrate 1, and using this as a mask, the driving MISFET is formed.
Forming regions of Qd ₁ and Qd ₂ and transfer MISFET Q
As is ion-implanted into the main surface of each p ⁻ type well _{2 in} the formation regions of t ₁ and Qt ₂ . Next, after removing the photoresist film by ashing, As introduced into the main surface of the p ⁻ type well 2 is stretched and diffused to drive MISFET Qd.
₁ , the n ⁺ type semiconductor region 11 is formed on the main surface of the p ⁻ type well _{2 in} the formation region of Qd ₂ , and the transfer MISFET Qt ₁ ,
An n ⁺ type semiconductor region 18 is formed on the main surface of the p ⁻ type well 2 in the Qt ₂ formation region.

Since the n-type semiconductor region 10 is previously formed on the main surface of the p ^- type well _{2 in} the formation region of the driving MISFETs Qd ₁ and Qd ₂ , the n ⁺ type semiconductor region 1 is formed.
By forming ₁ , the driving MISFET Qd ₁ having the source region and the drain region of the double diffused drain structure,
Qd ₂ is completed. In addition, the transfer MISFET Qt ₁ ,
Since the n-type semiconductor region 17 is formed in advance on the main surface of the p ⁻ -type well 2 in the Qt ₂ formation region, the formation of the n ⁺ -type semiconductor region 18 results in a source region and a drain region having an LDD structure. Transfer MISFETQ
t ₁ and Qt ₂ are completed (FIG. 11).

Next, after an insulating film 21 made of a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1 by the CVD method, a photoresist film is formed on the insulating film 21 and the insulating film 21 is used as a mask. , Insulating film 8 and insulating film (transferring M
The transfer MIS is formed by etching the gate insulating film 12 of the ISFETs Qt ₁ and Qt ₂ and the same insulating film).
A contact hole 22 is formed on one of the source and drain regions of the FETs Qt ₁ and Qt ₂ . At this time, the driving MISFET is formed on the bottom of the contact hole 22.
Part of the gate electrodes 7 of Qd ₁ and Qd ₂ is exposed. At the same time, using the photoresist film as a mask, the insulating film 21 and the insulating film (transfer MISFETs Qt ₁ , Qt _{2) are formed.}
By etching the gate insulating film 12 of the same layer), the other of the source and drain regions of the transfer MISFETs Qt ₁ and Qt ₂ (driving MISFET).
_One of the source region and the drain region of Qd ₁ and Qd ₂ )
A contact hole 22 is formed in the upper part of the.

Next, a polycrystalline silicon film which is a third-layer gate material is deposited on the entire surface of the semiconductor substrate 1 by the CVD method.
P is introduced into this polycrystalline silicon film at the time of deposition in order to reduce its resistance value. Next, the polycrystalline silicon film is etched using the photoresist film formed on the polycrystalline silicon film as a mask, and then the photoresist film is removed by ashing, whereby the load MISF is removed.
Gate electrodes 23A and pad layers 23B of ETQp ₁ and Qp ₂ are formed (FIG. 12).

Next, a load MIS is formed on the entire surface of the semiconductor substrate 1.
After depositing a silicon oxide film to be the gate insulating film 24 of the FETs Qp ₁ and Qp ₂ by the CVD method, the gate insulating film 2 is formed.
4, a photoresist film is formed, and the gate insulating film 24 is etched using this as a mask to form a contact hole 25 in the gate insulating film 24 above the gate electrodes 23A of the load MISFETs Qp ₁ and Qp _2. To do.

Next, after depositing a polycrystalline silicon film which is the fourth layer gate material on the entire surface of the semiconductor substrate 1 by the CVD method, the photoresist film formed on this polycrystalline silicon film is used as a mask. MISFET for load Qp ₁ , Qp ₂
P is ion-implanted into the polycrystalline silicon film in the region for forming the channel region 26N. Next, after removing the photoresist film by ashing, the polysilicon film is newly formed photoresist film on top of which was the mask load MISFET Qp _1, Qp ₂ source region 26P,
BF ₂ is ion-implanted into the polycrystalline silicon film in the region where the drain region 26P and the power supply voltage line (V _CC ) 26P are formed.

Next, after removing the photoresist film by ashing, a new photoresist film is formed on the polycrystalline silicon film, and the polycrystalline silicon film is etched by using this as a mask to load MISFETQ for load.
Channel regions 26N and source regions 26 of p ₁ and Qp ₂
P, drain region 26P and power supply voltage line (V _CC ) 26
Form P respectively. After that, by removing the photoresist film by ashing, the load MISFET Q
p ₁ and Qp ₂ are completed, and the SRAM memory cell MC shown in FIG. 1 is substantially completed.

The SRA of the present embodiment configured as described above
According to M, the following effects can be obtained.

. [0079] (1) transfer MISFET Qt _1, Qt ₂ and p in the region for forming the respective driving MISFET Qd _1, Qd ₂ ^- by providing the p-type buried layer 19 in the mold well 2, caused by α rays Since it is possible to prevent the minority carriers from entering the memory cell MC, it is possible to improve the α-ray soft error resistance of the memory cell MC.

(2) p under the field insulating film 4 which surrounds the periphery of the region where the transfer MISFETs Qt ₁ and Qt ₂ are formed.
Since the p-type channel stopper region 5 and the p-type buried layer 19 do not overlap each other even when the memory cell MC is miniaturized by not providing the type channel stopper region 5, transfer MISFETs Qt ₁ and Qt ₂ are formed. It is possible to prevent an increase in the impurity concentration of the p ⁻ type well 2 in the region to be formed.

As a result, the transfer MISFET Qt ₁ ,
Since it is possible to prevent the threshold voltage of Qt _{2 from} rising and increase the power supply voltage margin at the time of writing, it is possible to improve the operational reliability of the SRAM.

. [0082] (3) p in the region for forming the transfer MISFET Qt _1, Qt ₂ ^- by providing the p-type buried layer 19 in the mold well 2, it is possible to suppress the parasitic MOS effect, surrounding the region There is no problem even if the p-type channel stopper region 5 is not provided below the field insulating film 4.

(4). Due to the above (1) to (3), the memory cell of the SRAM can be miniaturized.

(5). Under the field insulating film 4 surrounding the region where the transfer MISFETs Qt ₁ and Qt ₂ are formed, p
To avoid providing the mold channel stopper region 5,
Since it is only necessary to change the mask pattern of the photoresist film 27 used as a mask when ion-implanting BF ₂ for the channel stopper, the number of SRAM manufacturing steps does not increase.

The invention made by the inventor of the present invention has been specifically described above based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above-described embodiment, the channel stopper region is provided under the field insulating film surrounding the driving MISFET, but the channel stopper region may not be provided under the field insulating film in the entire memory cell. Good.
Even in this case, since the buried layer is provided in the active region over the entire area of the memory cell, the parasitic MOS effect will not be actualized even if the channel stopper region is not provided.

In the above embodiment, the channel region, the source region and the drain region are formed in the upper layer of the gate electrode.
The case of application to an SRAM having a so-called bottom gate structure load MISFET has been described, but a so-called top gate structure load M in which a gate electrode is formed in an upper layer of a channel region, a source region and a drain region is described.
It can also be applied to SRAM having an ISFET.

In the above description, the case where the present invention is applied to the SRAM in which the load MISFET is formed above the drive MISFET has been described, but the present invention is not limited to this, and at least the transfer MISFET and the drive MISFET.
It can be widely applied to an SRAM in which an FET is formed on the main surface of a semiconductor substrate.

[0089]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

Transfer MI formed on the main surface of the semiconductor substrate
An SRAM in which a memory cell is composed of an SFET and a flip-flop circuit including a driving MISFET formed on the main surface of the semiconductor substrate and a load MISFET formed on the driving MISFET, wherein the transfer MISFET and the A buried layer having the same conductivity type as that of the semiconductor substrate and a higher impurity concentration than that of the semiconductor substrate is provided on the semiconductor substrate in a region where each of the driving MISFETs is formed.
By not providing the channel stopper region under the field insulating film surrounding the periphery of the, the α-ray soft error resistance can be improved and the operation reliability can be improved even when the SRAM is miniaturized. Can be improved.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a memory cell of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram showing a chip layout of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a schematic configuration diagram showing a part of FIG. 2 in an enlarged manner.

FIG. 4 is an equivalent circuit diagram of a memory cell of a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate (chip) 2 p ^- type well 4 field insulating film 5 p-type channel stopper region 6 gate insulating film 7 gate electrode 8 insulating film 9 sidewall spacer 10 n-type semiconductor region 11 n ⁺ type semiconductor region 12 gate insulating film 13A Gate electrode 13B Reference voltage line (V _SS ) 14 Contact hole 15 Insulating film 16 Sidewall spacer 17 n-type semiconductor region 18 n ⁺ type semiconductor region 19 p ⁺ type buried layer (embedded type semiconductor region) 20 silicon nitride film 21 Insulating film 22 Contact hole 23A Gate electrode 23B Pad layer 24 Gate insulating film 25 Contact hole 26N Channel region 26P Source region 26P Drain region 26P Power supply voltage line (V _CC ) 27 Photoresist film BP Bonding pad CC Control circuit DL phase Complementary data line DL ₁ First data line DL ₂ Second data line LMB Memory block LOAD Load circuit MAY Memory cell array MB Memory block MC Memory cell MWL Main word line Qd ₁ Driving MISFET Qd ₂ Driving MISFET Qp ₁ Load MISFET Qp ₂ load MISFET Qt ₁ transfer MISFET Qt ₂ transfer MISFET SA sense amplifier circuit SWL subword line SWL ₁ first subword line SWL ₂ second subword line WDEC word decoder circuit WL word line WL ₁ first word line WL ₂ 2 word lines XDEC X decoder circuit YDEC Y decoder circuit YSW Y selector circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Imazu 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Kazuo Yoshizaki, Josuimotocho, Kodaira-shi, Tokyo 5-20-1 Incorporated company Hitachi, Ltd. Semiconductor Division (72) Inventor Yama ▲ Saki ▼ Koji 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hirate Super L.S.I Engineering Co., Ltd. (72) Inventor Soichiro 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Stock company Hitachi Semiconductor Company Division (72) Inventor Keiichi Yoshizumi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division (72) Inventor Yasuko Yoshida 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Chiemi Mori 5-201-1, Kamimizuhoncho, Kodaira-shi, Tokyo Within Hitate Cho-LS Engineering Co., Ltd. (72) Kaji Fukuda 5-chome, Kamimizuhoncho, Kodaira-shi, Tokyo No. 20-1 Incorporated company Hitachi Ltd. Semiconductor Division

Claims (2)

[Claims] 1. A transfer MISFET formed on the main surface of a semiconductor substrate, a drive MISFET formed on the main surface of the semiconductor substrate, and a load MISFET formed on the drive MISFET. A semiconductor integrated circuit device having an SRAM in which a memory cell is composed of a flip-flop circuit, the transfer MISFE
A buried semiconductor region having the same conductivity type as that of the semiconductor substrate and having an impurity concentration higher than that of the semiconductor substrate is provided in the semiconductor substrate in the region where each of the T and the driving MISFET is formed. For MISFE
A semiconductor integrated circuit device characterized in that a channel stopper region for preventing inversion is not provided below the field insulating film surrounding the region where T is formed. 2. A transfer MISFET formed on the main surface of a semiconductor substrate, a drive MISFET formed on the main surface of the semiconductor substrate, and a load MISFET formed on the drive MISFET. A semiconductor integrated circuit device having an SRAM in which a memory cell is composed of a flip-flop circuit, the transfer MISFE
A buried semiconductor region having the same conductivity type as that of the semiconductor substrate and having an impurity concentration higher than that of the semiconductor substrate is provided in the semiconductor substrate in the region where each of the T and the driving MISFET is formed. For MISFE
A semiconductor integrated circuit device characterized in that a channel stopper region for preventing inversion is not provided below the field insulating film surrounding the region where each of T and the driving MISFET is formed.