JPH06275678A - Connecting between chip and substrate using conductive bonding agent improved in repair property - Google Patents
Connecting between chip and substrate using conductive bonding agent improved in repair propertyInfo
- Publication number
- JPH06275678A JPH06275678A JP5058911A JP5891193A JPH06275678A JP H06275678 A JPH06275678 A JP H06275678A JP 5058911 A JP5058911 A JP 5058911A JP 5891193 A JP5891193 A JP 5891193A JP H06275678 A JPH06275678 A JP H06275678A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- adhesive
- conductive adhesive
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 端子を有するチップと基板との電気的接続と
物理的接合とを導電性接着剤を用いて行うにあたり、リ
ペア性を向上させ、かつ信頼性及び生産性を高くする。
【構成】 端子を有するチップと基板とを導電性接着剤
によって接続する方法であって、
ａ．チップ上の端子に導電性接着剤を塗布する工程、
ｂ．チップと基板とを接続する工程、
ｃ．基板上の各上下端子間の導通テストおよび隣接する
端子間の絶縁テストを行う工程、並びに
ｄ．チップと基板との間に接着剤を流し込んで硬化させ
る工程
の各工程を含んでなるチップと基板との接続方法。
(57) [Abstract] [Purpose] Improve repairability and increase reliability and productivity when electrically connecting and physically bonding a chip having terminals to a substrate using a conductive adhesive. To do. A method for connecting a chip having a terminal and a substrate with a conductive adhesive, comprising: a. Applying a conductive adhesive to the terminals on the chip, b. Connecting the chip and the substrate, c. A step of conducting a continuity test between the upper and lower terminals on the substrate and an insulation test between adjacent terminals; and d. A method for connecting a chip and a substrate, which comprises the steps of pouring an adhesive between the chip and the substrate to cure the adhesive.
Description
【０００１】[0001]
【産業上の利用分野】本発明は端子を有するチップと基
板とを導電性接着剤によって接続する方法に関し、更に
詳しくは端子を有するチップと基板との導電性接着剤を
用いる接合において、チップと基板との間の接続工程を
（イ）チップ上の端子と基板の電極のみの接続、及び
（ロ）チップと基板間全面の接続という２工程に分け
て、リペア性を向上させた導電性接着剤を用いる接続方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting a chip having a terminal and a substrate with a conductive adhesive, and more particularly to a method for connecting a chip having a terminal and a substrate using a conductive adhesive. Conductive bonding with improved repairability by dividing the connection process with the board into two steps: (a) connecting only the terminals on the chip and the electrodes on the board, and (b) connecting the entire surface between the chip and the board. Connection method using an agent.
【０００２】[0002]
【従来の技術】最近の半導体工業における発展はめざま
しく、ＩＣ、ＬＳＩが次々に開発され、量産化されてい
るが、かかる発展によるＩＣチップの電極数の増大や高
密度化、高速度化に対応して、ＩＣチップの微小電極を
基板電極に接続する方法の開発が必要となってきた。そ
こで、最近では、古くから行われてきた半田バンプによ
るフリップチップ方式に加え、Ａｕバンプを導電性接着
剤や異方性導電ラバー、Ａｕめっき樹脂ボール等を介し
て基板に接続する方法やＡｕバンプをダイレクトに基板
電極に接続する方法等の検討が行われている。2. Description of the Related Art Recent developments in the semiconductor industry have been remarkable, and ICs and LSIs have been developed and mass-produced one after another. Due to such developments, it is possible to cope with an increase in the number of electrodes of an IC chip, a higher density, and a higher speed. Then, it has become necessary to develop a method for connecting the microelectrodes of the IC chip to the substrate electrodes. Therefore, in recent years, in addition to the flip chip method using solder bumps that has been used for a long time, a method of connecting Au bumps to a substrate via a conductive adhesive, anisotropic conductive rubber, Au plated resin balls, or the like, or Au bumps A method for directly connecting the substrate to the substrate electrode has been studied.
【０００３】これらはいずれも電気的接続はメカニカル
コンタクトでとり、接続の信頼性はチップ周辺に塗布し
た樹脂の接着力や圧縮応力に依存するものであり、かか
る方法により、従来の半田接合では不可能であった微細
接続が可能になりつつある。このように、半田接合に代
わる接合技術として、接着剤の樹脂中に金属粒子を分散
させた導電性接着剤を用いる方法が注目され、それに対
する要求が高まっているが、導電性接着剤を用いる接続
方法においては、チップと基板との間の全面に導電性接
着剤を適用して硬化し接合するという形態であるため、
リペア性という点で問題を抱えている。特に、高密度の
マイクロ接続では、接続法の開発はもちろんのこと、実
装後のリペア技術の開発も併せて行う必要がある。In all of these, mechanical connection is used for electrical connection, and the reliability of connection depends on the adhesive force and compressive stress of the resin applied to the periphery of the chip. The fine connections that were possible are becoming possible. As described above, a method of using a conductive adhesive in which metal particles are dispersed in a resin of an adhesive has attracted attention as a bonding technique instead of the solder bonding, and a demand for the method is increasing. However, the conductive adhesive is used. In the connection method, since a conductive adhesive is applied to the entire surface between the chip and the substrate to cure and bond,
There is a problem in terms of repairability. Especially in the case of high-density micro-connection, it is necessary to develop not only the connection method but also the repair technology after mounting.
【０００４】従来のチップと基板との接続は一般的に
は、図１に示すように、基板１又はチップ２に導電性接
着剤（異方性導電シート）３を全面（基板の場合には基
板電極４の全面）に塗布し、その後基板電極４とチップ
上の端子５の位置合せをして、チップ２と基板１との接
合を行うため、接合後、チップ２と基板１間全面が導電
性接着剤３で接着された状態になる。In the conventional connection between a chip and a substrate, a conductive adhesive (anisotropic conductive sheet) 3 is generally attached to the substrate 1 or the chip 2 (in the case of a substrate, as shown in FIG. 1). After the bonding, the entire surface between the chip 2 and the substrate 1 is bonded because the substrate 2 and the terminal 5 on the chip are aligned and the chip 2 and the substrate 1 are bonded. It is in a state of being bonded with the conductive adhesive 3.
【０００５】前記のような従来の導電性接着剤３を用い
た接合において、各接合の評価は基板とチップ間の各端
子における導通テストや絶縁テストにより行うが、これ
らの評価は接合完了後に行っていた。即ち、この導通テ
ストおよび絶縁テストにおいて不良が発生したときは、
全面が接着剤樹脂で接着しているチップを取り除く必要
があり、また、仮にうまく取り除けたとしても、基板に
残った接着剤を除去する必要があるなどの問題があっ
た。In the joining using the conventional conductive adhesive 3 as described above, each joining is evaluated by a continuity test or an insulation test at each terminal between the substrate and the chip. These evaluations are made after the joining is completed. Was there. That is, when a failure occurs in this continuity test and insulation test,
There is a problem in that it is necessary to remove the chip whose entire surface is bonded with the adhesive resin, and even if it is successfully removed, it is necessary to remove the adhesive remaining on the substrate.
【０００６】[0006]
【発明が解決しようとする課題】従って、本発明は、前
記した従来の導電性接着剤を用いたチップと基板との接
合における問題点を排除して、リペア性を向上させるこ
とができ、かつ信頼性及び生産性の高い、導電性接着剤
による端子を有するチップと基板との接続方法を提供す
ることを目的とする。SUMMARY OF THE INVENTION Therefore, the present invention can improve the repairability by eliminating the above-mentioned problems in joining the chip and the substrate using the conventional conductive adhesive, and An object of the present invention is to provide a highly reliable and highly productive method of connecting a chip having a terminal with a conductive adhesive to a substrate.
【０００７】[0007]
【課題を解決するための手段】本発明に従えば、端子を
有するチップと基板とを導電性接着剤によって接続する
方法であって、 ａ．チップ上の端子に導電性接着剤を塗布する工程、 ｂ．チップと基板とを接続する工程、 ｃ．基板上の各上下端子間の導通テストおよび隣接する
端子間の絶縁テストを行う工程、並びに ｄ．チップと基板との間に接着剤を流し込んで硬化させ
る工程 の各工程を含むことを特徴とするチップと基板との接続
方法が提供される。According to the present invention, there is provided a method of connecting a chip having a terminal and a substrate with a conductive adhesive, the method comprising the steps of: a. Applying a conductive adhesive to the terminals on the chip, b. Connecting the chip and the substrate, c. Conducting a continuity test between the upper and lower terminals on the board and an insulation test between adjacent terminals, and d. There is provided a method of connecting a chip and a substrate, which includes the steps of pouring an adhesive between the chip and the substrate to cure the adhesive.
【０００８】[0008]
【作用】本発明に従えば、先ず、従来は図１に示すよう
に、基板電極とチップ端子との電気的接続と、チップと
基板との接着力向上のための接合を同時にまとめて行っ
ていたのに対し、図２に示すように、接合工程を２段階
にし、図２の工程（イ）で基板６上の基板電極７とチッ
プ８上の端子９とを導電性接着剤10で接着接続し、その
終了後に、基板６とチップ８間の上下端子の導通テスト
および隣接する端子間の絶縁テストを行う。これらのテ
ストで問題のない場合には図２工程（ロ）に示すよう
に、チップ−基板間の間隙に導電性接着剤10を流し込
み、加熱硬化させてチップと基板とを接合させる。According to the present invention, first, as shown in FIG. 1, first, the electrical connection between the substrate electrode and the chip terminal and the bonding for improving the adhesive force between the chip and the substrate are simultaneously performed at the same time. On the other hand, as shown in FIG. 2, the joining process is performed in two stages, and the substrate electrode 7 on the substrate 6 and the terminal 9 on the chip 8 are bonded with the conductive adhesive 10 in the process (a) of FIG. After the connection is completed, a continuity test between upper and lower terminals between the substrate 6 and the chip 8 and an insulation test between adjacent terminals are performed. If there is no problem in these tests, as shown in step (b) of FIG. 2, the conductive adhesive 10 is poured into the gap between the chip and the substrate and heat-cured to bond the chip and the substrate.
【０００９】前記導通テスト又は絶縁テストのいずれか
において、不良があった場合には、図３に示すような手
順で、チップ８を取り除き、チップ８’の再搭載を行
う。即ち、図３において、不良チップ８を適当なトルク
をかけて引き上げ、残留接着剤を良溶媒（例えばテトラ
ヒドロフラン）で拭き取り、新たなチップ８’を再搭載
する。このような方式にすることで、従来方法で問題と
なっていた樹脂の残留量は大幅に低減でき、さらに接着
面積が小さいため、微小な力でのリペアが可能となる。
また、基板６とチップ８との接合を圧力等をかけず、熱
のみで行うのでチップ上の端子直下もチップの配線に使
うことができる可能性がある。If there is a defect in either the continuity test or the insulation test, the chip 8 is removed and the chip 8'is remounted according to the procedure shown in FIG. That is, in FIG. 3, the defective chip 8 is pulled up with an appropriate torque, the residual adhesive is wiped off with a good solvent (for example, tetrahydrofuran), and a new chip 8'is mounted again. By adopting such a method, the residual amount of the resin, which has been a problem in the conventional method, can be greatly reduced, and since the bonding area is small, it is possible to perform repair with a minute force.
Moreover, since the substrate 6 and the chip 8 are joined only by heat without applying pressure or the like, there is a possibility that the portion directly under the terminal on the chip can be used for the wiring of the chip.
【００１０】[0010]
【実施例】以下、実施例により本発明を更に具体的に説
明するが、本発明をこれらの実施例に限定するものでな
いことは言うまでもない。実施例１ 本実施例における工程の流れを図４に示す。以下、これ
について詳細に説明する。本実施例においては、次の材
料を用いた。 フィラー（導電性微粒子）：Ｃｕ粒子の表面Ａｇメッキ
をした平均粒径５μｍの粒子 接着剤：エポキシ系一液性接着剤（低粘度3000cps) 基板：ガラスエポキシ基板（電極間 100μｍ、パッド 2
00μｍ角、 128ピン） チップ：電極間 100μｍ、パッド 200μｍ角、 128ピンThe present invention will be described in more detail with reference to the following examples, but it goes without saying that the present invention is not limited to these examples. Example 1 FIG. 4 shows the flow of steps in this example. Hereinafter, this will be described in detail. The following materials were used in this example. Filler (conductive fine particles): Cu particles surface-plated with Ag particles having an average particle diameter of 5 μm Adhesive: Epoxy one-component adhesive (low viscosity 3000 cps) Substrate: Glass epoxy substrate (100 μm between electrodes, pad 2
00 μm square, 128 pins) Chip: 100 μm between electrodes, pad 200 μm square, 128 pins
【００１１】（１）チップ上の端子に導電性接着剤を塗
布する工程 ガラス板上に導電性接着剤（フィラー含有量 10vol％）
を厚さ35μｍに延ばし、その上に上記チップをのせ、そ
の後引き上げる。この際、ガラス板上の接着剤の厚さ
は、チップ上の端子の高さ以下にすることが必要で、さ
もなければ図５（不良品）に示すように隣接する端子同
士がつながってしまうので好ましくない。(1) Process of applying conductive adhesive to terminals on chip Conductive adhesive on glass plate (filler content 10 vol%)
Is extended to a thickness of 35 μm, and the chip is placed on it and then pulled up. At this time, the thickness of the adhesive on the glass plate needs to be equal to or less than the height of the terminals on the chip, or the adjacent terminals are connected to each other as shown in FIG. 5 (defective product). It is not preferable.
【００１２】（２）チップと基板との接合 チップ８と基板６は図６に示すように、上記工程（１）
で作製したチップ８を基板６と、チップ側を、 200℃に
加熱し、30秒保持することにより、接合した。(2) Bonding of Chip and Substrate The chip 8 and the substrate 6 are, as shown in FIG.
The chip 8 produced in 1 was joined to the substrate 6 by heating the chip side to 200 ° C. and holding for 30 seconds.
【００１３】（３）接合後の導通抵抗、絶縁抵抗の測定 上記工程（２）でボンディングしたサンプルの導通抵抗
及び絶縁抵抗を調べた。(3) Measurement of conduction resistance and insulation resistance after joining The conduction resistance and insulation resistance of the sample bonded in the above step (2) were examined.
【００１４】（４）不良箇所発生チップのリペア 上記工程（３）の測定の結果、不良箇所が発生したサン
プルについては、図７に示すように、チップ８にトルク
をかけてチップ８を取り除き、リペアを行った。チップ
８を取り除いた後、前述のようにして基板上の残留樹脂
をテトラヒドロフランにて拭き取り、上記工程（２）の
方法でチップを再搭載した。(4) Repair of Chip Having Defective Portion As to the sample having the defective portion as a result of the measurement in the step (3), as shown in FIG. 7, torque is applied to the chip 8 to remove the chip 8. I did a repair. After removing the chip 8, the residual resin on the substrate was wiped with tetrahydrofuran as described above, and the chip was remounted by the method of the above step (2).
【００１５】（５）チップと基板間に接着剤を流し込み
硬化させる工程 上記工程（２）の導通及び絶縁試験で良品のサンプル並
びに上記工程（２）の測定で不良品と判定され、その後
リペア工程により良品化されたサンプルについて、図８
に示すように、毛細管現象を利用して、チップ８と基板
６との間に接着剤11を流し込み、その後、温度 200℃で
１分間硬化させた。12は硬化接着剤を示す。(5) Step of pouring an adhesive between the chip and the substrate to cure it. A sample of non-defective product in the continuity and insulation test of the step (2) and a defective product by the measurement of the step (2), and then a repair step. Fig. 8 shows a sample that was made good by
As shown in FIG. 3, the adhesive 11 was poured between the chip 8 and the substrate 6 by utilizing the capillary phenomenon, and then cured at a temperature of 200 ° C. for 1 minute. 12 indicates a cured adhesive.
【００１６】（６）接合部の断面観察 作製したサンプルをバフ研磨にて、研磨し、倒置型顕微
鏡によりその断面を観察した。(6) Observation of Cross Section of Joined Part The produced sample was polished by buffing, and its cross section was observed with an inverted microscope.
【００１７】上で得られたサンプルについて、接合後の
導通抵抗及び絶縁抵抗を測定したところ、良品において
は導通抵抗はいずれも１接続点あたり 0.5Ω以下と良好
で、フィラーの含有量が 10vol％という大量使用にもか
かわらず、隣接するパターン間は絶縁を保った。また不
良発生品については、上記工程（４）でリペアを行い、
チップの再搭載を行ったところ、導通抵抗はいずれも１
接続点あたり 0.5Ω以下と良好で、隣接するパターン間
は絶縁を保った。一方、接合部の断面観察したところ、
図９に示すようであった。図９から、チップ８上の端子
先端の導電性接着剤10により、チップ８と基板６との間
の導通が確保でき、接続の信頼性は、チップ８と基板６
との間の接着剤樹脂の接着力により確保されていること
が観察できた。When the conduction resistance and the insulation resistance after joining of the samples obtained above were measured, the conduction resistances of good products were 0.5 Ω or less per connection point, and the content of the filler was 10 vol%. Despite the large amount of use, insulation was maintained between adjacent patterns. For defective products, repair in the above step (4),
When the chip was remounted, the conduction resistance was 1 for each.
It was good at 0.5Ω or less per connection point, and insulation was maintained between adjacent patterns. On the other hand, when observing the cross section of the joint,
It was as shown in FIG. From FIG. 9, it is possible to secure conduction between the chip 8 and the substrate 6 by the conductive adhesive 10 on the tip of the terminal on the chip 8, and the reliability of the connection is determined by the chip 8 and the substrate 6.
It was possible to observe that it was ensured by the adhesive force of the adhesive resin between and.
【００１８】実施例２ 導電性接着剤に粘度が 20,000cpsと極端に大きいものを
用いた以外は実施例１と同一の方法及び条件でチップ８
と基板６とを接続し、実施例１と同一の評価を行った。
結果は以下の通りである。 Example 2 A chip 8 was prepared in the same manner as in Example 1 except that a conductive adhesive having an extremely large viscosity of 20,000 cps was used.
And the substrate 6 were connected, and the same evaluation as in Example 1 was performed.
The results are as follows.
【００１９】（１）接合後の導通抵抗、絶縁抵抗の測定 実施例１と同一の結果を得た。 （２）ボンディングしたサンプルの断面観察 実施例１と同一の結果を得た。 以上の通り、実施例１と実施例２より、導電性接着剤の
粘度が広い範囲で、本発明による効果が有効であること
が確認できた。(1) Measurement of continuity resistance and insulation resistance after joining The same results as in Example 1 were obtained. (2) Cross-sectional observation of bonded sample The same result as in Example 1 was obtained. As described above, it was confirmed from Examples 1 and 2 that the effect of the present invention was effective in a wide range of viscosity of the conductive adhesive.
【００２０】実施例３ 導電性接着剤中のフィラー含有量が 1 vol％のものを用
いた以外は実施例１と同一の方法条件でチップ８と基板
６とを接続し、実施例１と同一の評価を行った。結果は
以下の通りである。 Example 3 The chip 8 and the substrate 6 were connected under the same method conditions as in Example 1 except that a conductive adhesive having a filler content of 1 vol% was used, and the same as in Example 1. Was evaluated. The results are as follows.
【００２１】（１）接合後の導通抵抗、絶縁抵抗の測定 隣接するパターン間は全て絶縁を保っており、導通抵抗
はフィラーの含有量が1 vol％という少量にもかかわら
ず、いずれの点においても１接続点あたり 0.5Ω以下と
良好であった。 （２）ボンディングしたサンプルの断面観察 実施例１と同一の結果を得た。(1) Measurement of Conduction Resistance and Insulation Resistance after Joining Insulation is maintained between all adjacent patterns, and the conduction resistance is at any point despite the small content of filler of 1 vol%. Was as good as 0.5Ω or less per connection point. (2) Cross-sectional observation of bonded sample The same result as in Example 1 was obtained.
【００２２】[0022]
【発明の効果】以上説明したように、本発明に従えば、
端子を有するチップと基板との接合を接合工程を２段階
にわけて実施し、その間に導通抵抗及び絶縁抵抗の測定
を行って良品を選別することにより、リペア性が向上す
る。また、本発明によれば、電気的な接続は導電性接着
剤でとり、接続の信頼性はチップと基板間の接着剤樹脂
の接着力により確保するので、電気的にも強度的にも信
頼性の高い接続が可能となった。As described above, according to the present invention,
By repairing the chip having the terminal and the substrate by performing the bonding process in two steps and measuring the conduction resistance and the insulation resistance during the bonding process to select non-defective products, the repairability is improved. Further, according to the present invention, the electrical connection is made by a conductive adhesive, and the reliability of the connection is secured by the adhesive force of the adhesive resin between the chip and the substrate, so that the electrical and strength are reliable. Highly reliable connection has become possible.
【図１】導電性接着剤による従来の接合手順を示す図面
である。FIG. 1 is a view showing a conventional bonding procedure using a conductive adhesive.
【図２】本発明に従った導電性接着剤によるチップと基
板との接合手順を示す図面である。FIG. 2 is a view showing a procedure for joining a chip and a substrate with a conductive adhesive according to the present invention.
【図３】本発明に従ったリペア手順及びチップの再搭載
手順を示す図面である。FIG. 3 is a diagram showing a repair procedure and a chip remounting procedure according to the present invention.
【図４】本発明の実施例１のフローを示す図面である。FIG. 4 is a diagram showing a flow of the first embodiment of the present invention.
【図５】本発明の実施例１においてチップ上の端子に導
電性接着剤を転写した後のサンプルの断面を示す図面で
ある。FIG. 5 is a drawing showing a cross section of a sample after a conductive adhesive has been transferred to the terminals on the chip in Example 1 of the present invention.
【図６】本発明の実施例１においてチップ上の端子と基
板電極との接合過程を示す図面である。FIG. 6 is a view showing a process of joining a terminal on a chip and a substrate electrode in Example 1 of the present invention.
【図７】本発明の実施例１において不良品のリペア手順
を示す図面である。FIG. 7 is a diagram showing a procedure for repairing a defective product according to the first embodiment of the present invention.
【図８】本発明の実施例１においてチップと基板との接
着工程を示す図面である。FIG. 8 is a drawing showing a step of adhering a chip and a substrate in Example 1 of the present invention.
【図９】本発明の実施例１において得られたサンプルの
接合部の断面観察図である。FIG. 9 is a cross-sectional observation view of the joint portion of the sample obtained in Example 1 of the present invention.
１…基板 ２…チップ ３…導電性接着剤 ４…基板電極 ５…チップ上の端子 ６…基板 ７…基板電極 ８…チップ ９…チップ上の端子 10…導電性接着剤 11…接着剤 12…硬化後の接着剤 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Chip 3 ... Conductive adhesive 4 ... Substrate electrode 5 ... Terminal on chip 6 ... Substrate 7 ... Substrate electrode 8 ... Chip 9 ... Terminal on chip 10 ... Conductive adhesive 11 ... Adhesive 12 ... Adhesive after curing
Claims (6)
着剤によって接続する方法であって、 ａ．チップ上の端子に導電性接着剤を塗布する工程、 ｂ．チップと基板とを接続する工程、 ｃ．基板上の各上下端子間の導通テストおよび隣接する
端子間の絶縁テストを行う工程、並びに ｄ．チップと基板との間に接着剤を流し込んで硬化させ
る工程 の各工程を含むことを特徴とするチップと基板との接続
方法。1. A method of connecting a chip having a terminal and a substrate with a conductive adhesive, comprising: a. Applying a conductive adhesive to the terminals on the chip, b. Connecting the chip and the substrate, c. Conducting a continuity test between the upper and lower terminals on the board and an insulation test between adjacent terminals, and d. A method of connecting a chip and a substrate, comprising the steps of pouring an adhesive between the chip and the substrate to cure the adhesive.
導電性接着剤を均一な厚さに塗布し、それに端子を有す
るチップを付着させ、その後チップを引き上げ端子上に
導電性接着剤を転写することにより接着剤を塗布する請
求項１記載の接続方法。2. In the step a, the conductive adhesive is applied to a glass plate to a uniform thickness, a chip having a terminal is attached to the glass plate, and then the chip is pulled up and the conductive adhesive is transferred onto the terminal. The connecting method according to claim 1, wherein the adhesive is applied by applying.
厚さがチップ上の端子の高さ以下である請求項２記載の
接続方法。3. The connecting method according to claim 2, wherein the coating thickness of the conductive adhesive on the glass plate is not more than the height of the terminal on the chip.
続を熱のみにより行う請求項１記載の接続方法。4. The connecting method according to claim 1, wherein in the step b, the substrate and the chip are connected only by heat.
において不良箇所が発生したものについては、チップを
取り外し、その後にチップの再搭載を行う請求項１記載
の接続方法。5. The connection method according to claim 1, wherein when a defective portion is generated in the continuity test or the insulation test in the step c, the chip is removed, and then the chip is remounted.
してチップと基板の間隙に接着剤を流し込み、加熱硬化
させる請求項１記載の接続方法。6. The connection method according to claim 1, wherein in the step d, an adhesive is poured into a gap between the chip and the substrate by utilizing a capillary phenomenon to heat and cure the adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058911A JPH06275678A (en) | 1993-03-18 | 1993-03-18 | Connecting between chip and substrate using conductive bonding agent improved in repair property |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058911A JPH06275678A (en) | 1993-03-18 | 1993-03-18 | Connecting between chip and substrate using conductive bonding agent improved in repair property |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06275678A true JPH06275678A (en) | 1994-09-30 |
Family
ID=13098005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5058911A Pending JPH06275678A (en) | 1993-03-18 | 1993-03-18 | Connecting between chip and substrate using conductive bonding agent improved in repair property |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06275678A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997027646A3 (en) * | 1996-01-26 | 1997-10-23 | Hewlett Packard Co | Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby |
| US6268739B1 (en) | 1998-03-30 | 2001-07-31 | International Business Machines Corporation | Method and device for semiconductor testing using electrically conductive adhesives |
| US6369450B1 (en) | 1999-01-14 | 2002-04-09 | Matsushita Electric Industrial Co., Ltd. | Method of producing mounting structure and mounting structure produced by the same |
| JP2018101605A (en) * | 2016-12-20 | 2018-06-28 | ザ・ボーイング・カンパニーＴｈｅ Ｂｏｅｉｎｇ Ｃｏｍｐａｎｙ | Conductive fastening system for composite structure |
| CN111477557A (en) * | 2019-01-23 | 2020-07-31 | 丰田自动车株式会社 | Semiconductor element bonding apparatus and semiconductor element bonding method |
-
1993
- 1993-03-18 JP JP5058911A patent/JPH06275678A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997027646A3 (en) * | 1996-01-26 | 1997-10-23 | Hewlett Packard Co | Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby |
| US5842273A (en) * | 1996-01-26 | 1998-12-01 | Hewlett-Packard Company | Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby |
| US6268739B1 (en) | 1998-03-30 | 2001-07-31 | International Business Machines Corporation | Method and device for semiconductor testing using electrically conductive adhesives |
| US6288559B1 (en) | 1998-03-30 | 2001-09-11 | International Business Machines Corporation | Semiconductor testing using electrically conductive adhesives |
| US6559666B2 (en) | 1998-03-30 | 2003-05-06 | International Business Machines Corporation | Method and device for semiconductor testing using electrically conductive adhesives |
| US6369450B1 (en) | 1999-01-14 | 2002-04-09 | Matsushita Electric Industrial Co., Ltd. | Method of producing mounting structure and mounting structure produced by the same |
| US6818461B2 (en) | 1999-01-14 | 2004-11-16 | Matsushita Electric Industrial Co., Ltd. | Method of producing mounting structure and mounting structure produced by the same |
| JP2018101605A (en) * | 2016-12-20 | 2018-06-28 | ザ・ボーイング・カンパニーＴｈｅ Ｂｏｅｉｎｇ Ｃｏｍｐａｎｙ | Conductive fastening system for composite structure |
| CN111477557A (en) * | 2019-01-23 | 2020-07-31 | 丰田自动车株式会社 | Semiconductor element bonding apparatus and semiconductor element bonding method |
| JP2020119983A (en) * | 2019-01-23 | 2020-08-06 | トヨタ自動車株式会社 | Semiconductor element bonding apparatus and semiconductor element bonding method |
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