JPH06275620A - Semiconductor integrated circuit wiring structure - Google Patents
Semiconductor integrated circuit wiring structureInfo
- Publication number
- JPH06275620A JPH06275620A JP6541393A JP6541393A JPH06275620A JP H06275620 A JPH06275620 A JP H06275620A JP 6541393 A JP6541393 A JP 6541393A JP 6541393 A JP6541393 A JP 6541393A JP H06275620 A JPH06275620 A JP H06275620A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor integrated
- integrated circuit
- wiring structure
- amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】
【目的】半導体集積回路において、Cu配線を用い、C
uのSi又はSiO2 への拡散を防止した配線構造を得
る。
【構成】Si基板1の表面にBPSGの絶縁膜2を設
け、その上にNb−Nのアモルファス層3をRFマグネ
トロンスパッタリングによって成長させ、その表面にC
u膜4をRFマグネトロンスパッタリングによって成長
させ、Cu配線5を形成する。
(57) [Abstract] [Purpose] In a semiconductor integrated circuit, Cu wiring is used and C
A wiring structure is obtained in which the diffusion of u into Si or SiO 2 is prevented. [Structure] An insulating film 2 of BPSG is provided on the surface of a Si substrate 1, an amorphous layer 3 of Nb-N is grown thereon by RF magnetron sputtering, and C is formed on the surface thereof.
The Cu film 5 is formed by growing the u film 4 by RF magnetron sputtering.
Description
【0001】[0001]
【産業上の利用分野】本発明は、Cu配線を有する半導
体集積回路(LSI)の配線構造体に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor integrated circuit (LSI) having Cu wiring.
【0002】[0002]
【従来の技術】現在、半導体集積回路の配線材料として
はAlあるいはAlとSiもしくはCuなどとの合金に
よるものが使用されている。このような配線において
は、Alを主材料として用いるため、流しうる許容電流
密度は(2〜3)×105 A/cm2 以下に制限されて
いた。これを越える電流を流した場合にはエレクトロマ
イグレーションによって配線が断線してしまうためであ
る。より多くの電流を流すためには、配線の材料として
Al中に2〜5%のCuを含む合金を用いることがあ
る。しかし、許容しうる電流密度は改善されるものの配
線の比抵抗は増加し、発熱に伴う信頼性低下の問題が生
じる。従って、Al配線に代わって、比抵抗の低い配線
材料として実質的にCuを用いることが提案されてい
る。2. Description of the Related Art At present, a wiring material for semiconductor integrated circuits is made of Al or an alloy of Al and Si or Cu. Since Al is used as the main material in such a wiring, the allowable current density that can be flown is limited to (2 to 3) × 10 5 A / cm 2 or less. This is because when a current exceeding this is applied, the wiring is broken due to electromigration. In order to flow more current, an alloy containing 2 to 5% Cu in Al may be used as a material for the wiring. However, although the allowable current density is improved, the specific resistance of the wiring is increased, which causes a problem of reliability deterioration due to heat generation. Therefore, it has been proposed to use Cu substantially as a wiring material having a low specific resistance in place of the Al wiring.
【0003】[0003]
【発明が解決しようとする課題】ところが、CuはAl
と比べるとSi又はSiO2 中に拡散しやすく、そのた
めトランジスタの正常な動作を妨げるという問題があ
る。このため、Cuの拡散防止層として結晶質バリア材
料を用いることが提案されている。例えば、1992春
応用物理学会30p−ZN−6、特開昭53−1160
89号公報、特開昭63−73645号公報、特開昭6
3−156341号公報、特開平1−20449号公報
等がある。しかし、この場合、結晶粒界からの拡散が発
生して十分な効果があげられていない。However, Cu is Al
There is a problem that it is more likely to diffuse into Si or SiO 2 as compared with the above, and thus the normal operation of the transistor is hindered. Therefore, it has been proposed to use a crystalline barrier material as the Cu diffusion prevention layer. For example, 1992 Spring Society of Applied Physics 30p-ZN-6, JP-A-53-1160.
89, JP-A-63-73645 and JP-A-6.
There are JP-A-3-156341, JP-A-1-20449, and the like. However, in this case, the diffusion from the crystal grain boundaries occurs and the sufficient effect is not obtained.
【0004】したがって、Cu配線の拡散を防止できる
半導体集積回路の配線構造の開発が急務である。本発明
はこの問題を解決した半導体集積回路配線構造体を提供
することを目的とする。Therefore, there is an urgent need to develop a wiring structure of a semiconductor integrated circuit capable of preventing the diffusion of Cu wiring. An object of the present invention is to provide a semiconductor integrated circuit wiring structure that solves this problem.
【0005】[0005]
【課題を解決するための手段】本発明は前記問題点を解
決するために、配線材料として、Al配線の代りに、実
質的にCuを用い、W,Ta,Nb,Ti及びこれらの
窒化物から選ばれた1種の材料のアモルファスバリア層
をCu配線の下地とするか、又はCu配線の上部又は側
面部の被覆として設けた半導体集積回路配線構造体を提
案するものである。In order to solve the above problems, the present invention uses W, Ta, Nb, Ti and their nitrides as a wiring material, substantially using Cu instead of Al wiring. The present invention proposes a semiconductor integrated circuit wiring structure in which an amorphous barrier layer of one kind of material selected from the above is used as a base of Cu wiring or provided as a coating on the upper portion or side surface portion of Cu wiring.
【0006】[0006]
【作用】本発明によれば、配線材料にはCuを用いるた
め、比抵抗はAlより低く、耐エレクトロマイグレーシ
ョンも良好である。しかもアモルファスバリア層によっ
てCu配線を被覆するので、Cuの粒界拡散を抑制する
ことが可能となった。アモルファスバリアとして利用可
能な材料として効果的なものとしては、Cu固溶が少な
く熱処理によってもCuの比抵抗が上昇しないW、T
a、Nb,Ti及びこれらの窒素化合物を挙げることが
できる。これらの材料のアモルファス層を形成するに
は、スパッタリング法、イオンプレーテイング法などに
よって直接アモルファス層を生成させるか、又は結晶層
を成膜後、イオン照射,イオン注入等の手法によってア
モルファス化させる。According to the present invention, since Cu is used as the wiring material, the specific resistance is lower than that of Al and the electromigration resistance is good. Moreover, since the Cu wiring is covered with the amorphous barrier layer, it is possible to suppress the grain boundary diffusion of Cu. Materials that can be effectively used as an amorphous barrier include W and T, which have a small Cu solid solution and whose Cu resistivity does not increase even by heat treatment.
Mention may be made of a, Nb, Ti and nitrogen compounds thereof. To form an amorphous layer of these materials, an amorphous layer is directly formed by a sputtering method, an ion plating method, or the like, or a crystalline layer is formed and then made amorphous by a method such as ion irradiation or ion implantation.
【0007】このようにして形成されたアモルファスバ
リア層を設けることによりCuの拡散防止効果が高めら
れる。By providing the amorphous barrier layer thus formed, the Cu diffusion preventing effect is enhanced.
【0008】[0008]
【実施例】図1は、本発明によるCu配線構造の製造工
程を示す断面図である。図1(a)に示すように、Si
基板1の表面に5000ÅのBPSG(Boro−Ph
ospho−Silicate Glass)の絶縁膜
2を設け、その表面にCuの下地としてNb−Nのアモ
ルファス層3を、全圧が2mTorrで、45%の窒素
を含むAr雰囲気中でRFマグネトロンスパッタリング
によって、成膜速度10Å/sで600Å成長させる。
このアモルファス層3の形成には、基板温度をNb−N
の結晶化温度より低く保つために基板ホルダを液体窒素
で冷却することによってアモルファス層を得た。ここで
Nb−N層はX線回折法によってアモルファス構造であ
ることを確認した。その表面にCu膜4をRFマグネト
ロンスパッタリングによって2mTorrのAr雰囲気
中で成膜速度6000Å/minで5000Å成長させ
る。次に図1(b)に示すように、これをパターニング
してCu配線5を形成する。次に図1(c)のように、
下地と同様に反応性スパッタリングによってCu配線5
の周囲を厚さ500ÅアモルファスNb−N層6で被覆
してCu配線5を作製する。その後、不要部分をエッチ
ングして図1(d)のようなCu配線構造体10を作製
する。さらに、本配線構造を多層化する場合には、アモ
ルファスNb−N層6上にSiO2 等の絶縁膜を設け
て、その上に3〜5の配線構造を同様に作製すればよ
い。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing a manufacturing process of a Cu wiring structure according to the present invention. As shown in FIG. 1A, Si
5000 Å BPSG (Boro-Ph
an insulating film 2 of ospho-Silicate Glass), and an amorphous layer 3 of Nb-N is formed on the surface of the insulating film 2 as an underlayer of Cu by RF magnetron sputtering at a total pressure of 2 mTorr in an Ar atmosphere containing 45% nitrogen. Grow at 600Å at a film speed of 10Å / s.
To form the amorphous layer 3, the substrate temperature is set to Nb-N.
An amorphous layer was obtained by cooling the substrate holder with liquid nitrogen to keep it below the crystallization temperature of. Here, it was confirmed by an X-ray diffraction method that the Nb-N layer had an amorphous structure. A Cu film 4 is grown on the surface thereof by RF magnetron sputtering in an Ar atmosphere of 2 mTorr at a film forming rate of 6000 Å / min and 5000 Å. Next, as shown in FIG. 1B, this is patterned to form Cu wiring 5. Next, as shown in FIG.
Cu wiring 5 by reactive sputtering as well as the base
The periphery of is covered with an amorphous Nb-N layer 6 having a thickness of 500Å to form a Cu wiring 5. After that, unnecessary portions are etched to produce a Cu wiring structure 10 as shown in FIG. Further, when the present wiring structure is formed in multiple layers, an insulating film such as SiO 2 may be provided on the amorphous Nb-N layer 6 and the wiring structures 3 to 5 may be similarly formed thereon.
【0009】表1は、各種のバリア材料を用いた場合の
Cuに対するバリア性をSIMS(Secondary
−Ion Mass Spectroscopy 二次
イオン質量分析)によって評価した結果である。試料
は、Siウエハ上に熱酸化膜を5000Å成長させ、そ
の上に各種のバリア材料をRFマグネトロンスパッタリ
ングで600Å成膜し、さらに、Cuを5000Å積層
したものをH2 中で600℃×1hの熱処理(昇温速
度:100℃/h)を行ったもので、これらをSIMS
を用いてCuのデプスプロファイルを得ることによっ
て、Siウエハ中のCuの濃度を比較したものである。
この表に示すように、これまで提案されている結晶質金
属膜、窒化物膜に比べて本発明によるアモルファスバリ
ア材料を用いた場合には、Cuの拡散を著しく防止する
ことが明らかに示されている。これは結晶粒界を有しな
いアモルファス構造であるため粒界を通してのCuの拡
散が抑制されるためであると考えられる。Table 1 shows the barrier properties against Cu when various barrier materials are used, SIMS (Secondary).
-Ion Mass Spectroscopy secondary ion mass spectrometry). The sample was a thermal oxide film grown on a Si wafer for 5000 Å, various barrier materials were deposited on it by RF magnetron sputtering for 600 Å, and Cu was laminated for 5000 Å in H 2 at 600 ° C for 1 h. Heat treatment (heating rate: 100 ° C / h) was performed, and SIMS
This is a comparison of the Cu concentration in the Si wafer by obtaining the Cu depth profile using.
As shown in this table, it is clearly shown that when the amorphous barrier material according to the present invention is used, the diffusion of Cu is remarkably prevented as compared with the crystalline metal film and the nitride film which have been proposed so far. ing. It is considered that this is because the amorphous structure having no crystal grain boundary suppresses diffusion of Cu through the grain boundary.
【0010】[0010]
【表1】 [Table 1]
【0011】[0011]
【発明の効果】このように、微細な半導体集積回路の配
線構造においてアモルファス層でCu配線を取り囲んだ
構造体又はCu配線の下地とする構造体を作製すること
によって、Cuが周囲に拡散することがなく、Al配線
に比べて比抵抗が低く、エレクトロマイグレーションに
優れた半導体の配線構造体を実現することができた。従
って、半導体集積回路の配線としてCu配線の利用が可
能となり、本技術の工業的意義は大きい。As described above, in the fine wiring structure of the semiconductor integrated circuit, Cu is diffused to the surroundings by forming a structure in which the Cu wiring is surrounded by the amorphous layer or a base body of the Cu wiring. Thus, a semiconductor wiring structure having a lower specific resistance than Al wiring and excellent electromigration could be realized. Therefore, Cu wiring can be used as the wiring of the semiconductor integrated circuit, and the industrial significance of the present technology is great.
【図1】本発明の配線構造体の製造工程をを示す断面図
である。FIG. 1 is a cross-sectional view showing a manufacturing process of a wiring structure of the present invention.
1 Si基板 2 絶縁膜 3 アモルファス層 4 Cu膜 5 Cu配線 6 アモルファ
スNb−N層 10 Cu配線構造体DESCRIPTION OF SYMBOLS 1 Si substrate 2 Insulating film 3 Amorphous layer 4 Cu film 5 Cu wiring 6 Amorphous Nb-N layer 10 Cu wiring structure
Claims (1)
物から選ばれた1種の材料のアモルファスのバリア層を
Cu配線の下地又は被覆として設けたことを特徴とする
半導体集積回路配線構造体。1. A semiconductor integrated circuit wiring structure, characterized in that an amorphous barrier layer of one material selected from W, Ta, Nb, Ti and nitrides thereof is provided as an underlayer or coating of Cu wiring. body.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6541393A JPH06275620A (en) | 1993-03-24 | 1993-03-24 | Semiconductor integrated circuit wiring structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6541393A JPH06275620A (en) | 1993-03-24 | 1993-03-24 | Semiconductor integrated circuit wiring structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06275620A true JPH06275620A (en) | 1994-09-30 |
Family
ID=13286332
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6541393A Pending JPH06275620A (en) | 1993-03-24 | 1993-03-24 | Semiconductor integrated circuit wiring structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06275620A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100243286B1 (en) * | 1997-03-05 | 2000-03-02 | 윤종용 | Method for manufacturing a semiconductor device |
JP2011159959A (en) * | 2010-02-03 | 2011-08-18 | Samsung Electronics Co Ltd | Method for forming thin film, metal wiring for display panel, thin film transistor display panel including the same, and method for manufacturing the same |
CN102851645A (en) * | 2012-10-11 | 2013-01-02 | 电子科技大学 | Preparation method of low-residual-stress copper film |
-
1993
- 1993-03-24 JP JP6541393A patent/JPH06275620A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100243286B1 (en) * | 1997-03-05 | 2000-03-02 | 윤종용 | Method for manufacturing a semiconductor device |
JP2011159959A (en) * | 2010-02-03 | 2011-08-18 | Samsung Electronics Co Ltd | Method for forming thin film, metal wiring for display panel, thin film transistor display panel including the same, and method for manufacturing the same |
US8946025B2 (en) | 2010-02-03 | 2015-02-03 | Samsung Display Co., Ltd. | Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same |
US9799678B2 (en) | 2010-02-03 | 2017-10-24 | Samsung Display Co., Ltd. | Manufacturing method of thin film and metal line for display using the same, thin film transistor array panel, and method for manufacturing the same |
CN102851645A (en) * | 2012-10-11 | 2013-01-02 | 电子科技大学 | Preparation method of low-residual-stress copper film |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20020122 |