JPH06275093A - Sample-and-hold device - Google Patents

Abstract

PURPOSE:To obtain a sample-and-hold device of which operation is stable and an occupancy area is small. CONSTITUTION:Positive and negative input V1, V2 are inputted to a first differential circuit 1, their positive and negative output V3, V4 are inputted to positive side and negative side diode bridge circuits 2, 3, and their positive and negative output V5, V6 are inputted to a second differential circuit 6. And their positive and negative output V7, V8 are inputted to reference voltage impressing terminals 23, 33 of the diode bridge circuit 2, 3. Capacitors 4, 5 are provided between output terminals 22, 32 of the diode bridge circuit 2, 3 and the ground.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold device, and more particularly to a differential sample and hold device for sampling and holding a voltage difference between two input analog signals.

[0002]

2. Description of the Related Art FIG. 14 shows the structure of a conventional sample hold device D. The sample-hold device D is a differential sample-hold device using well-known non-differential sample-hold circuits 100 and 101. 1
Reference numerals 0 and 11 denote positive and negative input terminals of the sample and hold device D, each of which is connected to the positive and negative input terminals of the differential circuit 1. The positive and negative output terminals of the differential circuit 1 are input to the positive sample hold circuit 100 and the negative sample hold circuit 101, respectively. The outputs of the positive sample hold circuit 100 and the negative sample hold circuit 101 are connected to the positive and negative output terminals 12 and 13 of the sample hold device D, respectively.

The positive side sample and hold circuit 100 has the following configuration. Reference numeral 2 is a positive side diode bridge circuit which is a switching means on the positive side, and its input terminal 21
Is connected to the positive output terminal of the differential circuit 1. The output terminal 22 of the positive side diode bridge circuit 2 is connected to one electrode of the positive side capacitor 4 and also to the positive input terminal of the positive side operational amplifier 102. The other electrode of the positive side capacitor 4 is grounded. Reference numeral 23 is a reference voltage application terminal for applying a reference voltage for limiting the voltage of the internal node of the positive diode bridge circuit 2 in the hold period, and will be simply referred to as a reference voltage application terminal hereinafter. . Reference numerals 24 and 25 denote clock input terminals of the positive diode bridge circuit 2, to which complementary clock signals φH and φS are applied. The output from the positive-side operational amplifier 100 is connected to its negative input terminal, and further, the sample-hold device D
Is connected to the positive output terminal 12. The negative side sample circuit 101 also has the same configuration as the positive side sample and hold circuit 100, and includes the negative side diode bridge circuit 3 and the negative side operational amplifier 103.

Next, the operation will be described. The differential circuit 1 is provided to drive the diode bridge circuits 2 and 3, and generates a complementary signal having a potential difference corresponding to the potential difference between its input terminals as a potential difference between its output terminals. That is, if the potentials of the positive input terminal and the negative input terminal of the differential circuit 1 are V ₁ and V ₂ , and the potentials of the positive output terminal and the negative output terminal are V ₃ and V ₄ , respectively, the operation is V ₃ = _{V 01 + (a 1/2} ) (V 1 -V 2) ... (1) V 4 = V 01 - (a 1/2) (V 1 -V 2) ... (2) and can be expressed. Here, V ₀₁ is the common-mode output voltage of the differential circuit 1, that is, the potential of the positive and negative output terminals when the potentials of the positive and negative input terminals are equal, and A ₁ is the differential gain of the differential circuit 1. , That is, the gain of the output potential difference with respect to the input potential difference.

Input terminals of diode bridge circuits 2 and 3
21 and 31 are positive outputs V of the differential circuit 1. ₃And negative output V_Four
Driven by. Diode bridge circuit 2 and 3
Potential V of output terminals 22 and 32_Five, V₆The sample period
(Clock signal φS is “H” level, clock signal φH
Is at the “L” level), the input terminals 21, 31
Potential V₃, V_FourIs equal to That is, sample period
Between the positive side diode bridge circuit 2 output terminal 22
Potential V_FiveIs the positive output V of the differential circuit 1.₃Following changes in
The potential V of the output terminal 32 of the negative side diode bridge circuit 3
₆Is the negative output V of the differential circuit 1._FourTo follow the changes. next,
Hold period (clock signal φS is at “L” level, black
Clock signal φH is at “H” level)
The output terminals 22 and 32 of the ode bridge circuits 2 and 3 are high
And the input / output terminals are electrically disconnected.
Be done. This ensures that at the end of the sample period
Positive and negative output potential V of the differential circuit 1₃, V_FourEach of
Are held in the positive side capacitor 4 and the negative side capacitor 5.
Be done. The operational amplifiers 102 and 103 have these holding potentials.
It is provided to generate a potential equal to.
In each of these operational amplifiers 102 and 103,
The output terminal of is directly connected to the negative input terminal. like this
In this connection, as is well known, the operational amplifier 102,
When the operation of 103 is ideal, its output potential V₇，
V₈Is the potential V of the positive input terminal_Five, V₆Is equal to did
Therefore, the output V of the positive side operational amplifier 102₇, Ie the edge
Output V appearing on child 12₇Is the differential time in the sample period
Positive output V of path 1₃Changes during the hold period
Outputs a constant value, that is, the potential at the last moment of the sample period
To do. The same applies to the potential of the output of the negative side operational amplifier 103.
It

The output voltage V ₇ of the positive side operational amplifier 102 is applied to the reference voltage application terminal 23 of the positive side diode bridge 2, and the node voltage inside the positive side diode bridge 2 is limited. Also, the output voltage V ₈ of the negative side operational amplifier 103
Is applied to the reference voltage application terminal 33 of the negative side diode bridge 3, and the node voltage inside the negative side diode bridge 3 is limited. FIG. 15 shows diode bridge circuits 2 and 3
It is a detailed circuit diagram of and the figure number is the positive side diode bridge 2
Was adapted to. 201 to 204 are diodes forming a bridge, and 205 and 206 are clamping diodes provided to limit the potentials of the nodes A and B during the hold period. Further, 207 and 208 are current sources having a current value I, and 209 is a current value 2 which is twice that.
It is a current source having I. Further, 210 and 211 are current switching transistors, each of which is a clock signal φ.
It is controlled by H and φS.

In the sampling period, the clock signal φS
Becomes "H" level, and the clock signal φH becomes "L" level. As a result, the current of the current source 208 directly flows into the collector of the transistor 211, and the current of the current source 207 flows into the collector of the transistor 211 via the diodes 201 to 204. That is, the diodes 201 to 20
4 is forward biased. On the other hand, the diodes 205 and 20
6 is reverse-biased, and the reference voltage application terminal 23 and the internal nodes A and B are electrically disconnected. Where diode 2
Since the path of 01 and 202 and the path of the diodes 203 and 204 are symmetrical, the potential V _{5 of the} terminal 22 is
Attempt to settle so as to match the potential V _{3 of} . That is, in the sampling period, the potential V ₅ of the output terminal 22 of the diode bridge circuit 2 follows the change of the potential V ₃ of the input terminal 21. Next, in the hold period, the clock signal φS becomes “L” level and the clock signal φH becomes “H” level. As a result, the current of the current source 207 directly flows to the collector of the transistor 210. In addition, the current source 2
The current of 08 tries to flow into the collector of the transistor 210 from the node B via the node A, and the diodes 201 to 204 are reverse biased. by this,
The input terminal 21 and the output terminal 22 are both in a high impedance state and are electrically isolated from each other.

On the other hand, if the diodes 205, 206 and
If the reference voltage applying terminal 23 is not provided,
The current from the current source 208 loses its place at node B.
Yes, the potential of this node rises steadily. Also,
At the node A, the current flowing out to the current source 209 is 207
Since it exceeds the current supplied from
The potential of the do goes down. As a result, node B
Is close to the power supply potential, and node A is close to the ground potential.
Changes greatly. Diode 205, 206 and base
The quasi-voltage applying terminal 23 has a large potential change of this internal node.
It is provided to prevent aging. Diode 20
5,206 are forward biased during the hold period, and the current source 2
Bypass current from 08 to node A. Also this
Diode 205 or 20 produced by forward current
Anode-cathode voltage of 6 is V_D, Reference voltage application terminal
The potential of the child 23 is V_CThen, the potential of the node A is V_C−
V _D, The potential of node B is V_C+ V_DFixed to. Toko
As described above, the output potential V of the operational amplifier 102 is
₇Is the reference voltage V_CGiven as an operational amplifier
102 output potential V₇Is the output terminal of the diode bridge
22 potential V_FiveEqual to the hold period
In addition, the potential of the node A is always the potential V of the output terminal 22.
_FiveLower, the potential of node B must be the potential of output terminal 22
V_FiveGet higher. Therefore, during the hold period
The diodes 203 and 204 are always reverse biased,
As a result, the high impedance state of the terminal 22 is always realized.
It As a result, the capacitor 4 is held in the hold period.
The stored charge should not leak inside the diode bridge 2.
Is sure. In addition, the negative diode bridge 3
The configuration and operation are similar.

[0009]

Although the conventional sample and hold device D is constructed as described above, the potential V ₇ equal to the potentials V ₅ and V ₆ held in the capacitors 4 and 5 as described above. , V ₈ are output, the operational amplifiers 102 and 103 are used. This operational amplifier 102,
The output of 103 is fed back to the input. As is well known, a circuit having a feedback path may oscillate and become unstable in operation. Further, in the conventional sample hold device D, such an operational amplifier 10
Two and two 103 are required. For example, when the sample hold device D is to be integrated on the same semiconductor substrate,
A large occupied area was required.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a sample-hold device which operates stably and occupies a small area.

[0011]

A first sample and hold device according to the present invention is a differential sample and hold device for sample and hold a voltage difference between two input analog signals. And a second input terminal,
A first and a second output terminal, wherein an output voltage difference between the first and second output terminals changes in accordance with an input voltage difference between the first and second input terminals Differential circuit, an input terminal connected to the first output terminal of the first differential circuit, and an input terminal electrically connected to the input terminal during the sampling period and electrically connected to the input terminal during the hold period. First switch means having an output terminal that is electrically shut off, an input terminal connected to the second output terminal of the first differential circuit, and an input terminal electrically connected to the input terminal during the sampling period. A second switch means having an output terminal electrically cut off from the input terminal in the hold period, one electrode of which is connected to the output terminal of the first switch means, and the other electrode of which is a constant potential node. Connected to A first capacitor are connected one electrode to the output terminal of said second switching means,
A second capacitor whose other electrode is connected to a constant potential node, a first input terminal connected to one electrode of the first capacitor, and a second input terminal connected to one electrode of the second capacitor. Input terminal, a first output terminal and a second output terminal, and a potential substantially equal to the potential of the first input terminal is generated from the first output terminal,
And a second differential circuit for generating a potential from the second output terminal that is substantially equal to the potential of the input terminal of.

Further, between the one electrode of the first capacitor and the first input terminal of the second differential circuit, and between the one electrode of the second capacitor and the second electrode of the second differential circuit. A buffer circuit that outputs the same voltage as the input voltage when the input current is 0 may be connected between the input terminals of the.

The second sample and hold device of the present invention is a differential type sample and hold device for sampling and holding the voltage difference between the two input analog signals. An input terminal and first and second output terminals are provided, and an output voltage difference between the first and second output terminals is determined according to an input voltage difference between the first and second input terminals. A changing first differential circuit, an input terminal connected to a first output terminal of the first differential circuit, electrically connected to the input terminal during a sample period, and the input during a hold period. First switch means having an output terminal electrically cut off from the terminal and a reference voltage application terminal to which a reference voltage for limiting the voltage of the internal node is applied during the hold period; and the first difference. Movement An input terminal connected to the second output terminal, an output terminal electrically connected to the input terminal in the sample period and electrically cut off from the input terminal in the hold period, and an internal node in the hold period. Second switch means having a reference voltage application terminal for applying a reference voltage for limiting the voltage of the first switch means, one electrode of which is connected to the output terminal of the first switch means and the other electrode is A first capacitor connected to the constant potential node; a second capacitor having one electrode connected to the output terminal of the second switch means and the other electrode connected to the constant potential node; A first connected to one electrode of the first capacitor
An input terminal of the second capacitor, a second input terminal connected to one electrode of the second capacitor, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal, A potential substantially equal to the potential of the first input terminal is generated from the first and third output terminals, and a potential substantially equal to the potential of the second input terminal is generated from the second and fourth output terminals. , The potential generated from the third output terminal
And a second differential circuit for applying the potential generated from the fourth output terminal to the reference voltage application terminal of the second switch means. .

[0014]

In the first sample and hold device of the present invention, only one differential circuit that does not require feedback is used as means for outputting a potential equal to the potential held in the positive and negative capacitors. There is. Therefore, it is possible to obtain a sample and hold device having a smaller operation area and more stable operation than the conventional example using two operational amplifiers whose outputs are fed back to the input as the above means.

If a buffer circuit that outputs a voltage having an input current of 0 and a voltage equal to the input voltage is connected between the positive and negative capacitors and the second differential circuit, the hold stored in the capacitor during the hold period is held. The current does not leak and the output of the sample hold device does not drift.

In addition, in the second sample and hold device of the present invention, in addition to the first and second output terminals to which the second differential circuit provides the output of the sample and hold device,
It includes third and fourth output terminals that provide independent outputs, the outputs being applied to the reference voltage application terminals of the first and second switch means. Therefore, even if noise occurs in the switch means, the output of the sample hold device is not adversely affected.

[0017]

1 is an electric circuit diagram of a sample hold device A according to an embodiment of the present invention. Reference numeral 6 denotes a second differential circuit, the positive input terminal of which is connected to the output terminal 22 of the positive diode bridge 2 and the negative input terminal of which is connected to the output terminal 32 of the negative diode bridge 3. The positive output of the differential circuit 6 is the positive output terminal 1 of the sample hold device A.
2 and the reference voltage application terminal 23 of the positive diode bridge 2, and the negative output of the differential circuit 6 is the negative output terminal 12 of the sample hold device A and the reference voltage application terminal 33 of the negative diode bridge 3. Connected with. Other configurations are similar to those of the conventional example.

Next, the operation will be described. Figure 2 is this
A time chart showing the operation of the sample hold device A
Yes, FIG. 2A shows the positive and negative inputs V of the differential circuit 1.₁，
V₂2B shows the positive and negative outputs of the differential circuit 1.
V₃, V_Four2C shows clock signals φS and φ.
2H shows the holding potential V of the capacitors 4 and 5.
_Five, V₆2E shows the positive and negative of the differential circuit 2.
Output V₇, V₈Is shown. Similar to the conventional example, differential circuit
1 is a complementary having a potential difference according to the potential difference between its input terminals
The signal is generated as a potential difference between its output terminals,
Input-output relations are given in equation (1) and equation (2)
It Positive and negative outputs V of this differential circuit 1₃, V_FourIs a figure
In-phase output voltage V as shown in 2 (b)₀₁Centered around
It is a complementary signal that changes its name. Switch circuit
Output potential of the diode bridges 2 and 3
The potential V of one electrode of the capacitors 4 and 5_Five, V₆Is the same as the conventional example
Similarly, during the sample period (φS is “H” level), V
₃, V_FourAnd a constant value during the hold period, that is,
The potential at the last moment of the sample period is output. According to
Then, as shown in FIG._Five, V₆Also differential circuit 1
Common-mode output voltage V₀₁Complementary that changes symmetrically around
It is a signal. Therefore, V_FiveV₀₁The potential difference from
Let V be V_Five= V₀₁+ ΔV (3) V₆= V₀₁−ΔV (4) The second differential circuit 6 has its input similar to the differential circuit 1.
A complementary signal with a potential difference according to the potential difference between the terminals
It occurs as a potential difference between the output terminals. That is, differential times
The potentials of the positive output terminal and the negative output terminal of the path 6 are respectively V₇When
V₈Then, the operation is V₇= V₀₂+ (A₂/ 2) (V_Five-V₆)… (5) V₈= V₀₂-(A₂/ 2) (V_Five-V₆)… (6) Where V₀₂Is the in-phase output voltage of the differential circuit 6.
Pressure, A₂Is the differential gain of the differential circuit 6. Differential times here
Differential gain A of path 6₂If is 1, then equations (3)-(6)
And V₇= V₀₂+ ΔV (7) V₈= V₀₂−ΔV (8) Further, the in-phase output voltage V of the differential circuit 6₀₂Is differential
In-phase output voltage V of circuit 1 ₀₁Is equal to V₇= V₀₁+ ΔV (9) V₈= V₀₁−ΔV (10) Expressions (3) and (4) and Expressions (9) and (1
Comparing 0), V_FiveAnd V₇, V₆And V₈Is equal
I understand. That is, the differential gain A of the differential circuit 6₂Is 1
And its in-phase output voltage V₀₂Is the in-phase output voltage of the differential circuit 1
V₀₁And the positive input voltage V of the differential circuit 6_FiveAnd
Force voltage V₇, Negative input voltage V₆And negative output voltage V ₈Are equal
Become. This is the case in the conventional sample and hold device D.
Operational amplifier 10 whose output is fed back to the negative input
The function that I was trying to realize using two 2,103
Realized without feedback using one differential amplifier 6
It is nothing but doing.

It is easy to realize that the differential gain A ₂ of the differential circuit 6 is set to 1 and its in-phase output voltage V ₀₂ is made equal to the in-phase output voltage V ₀₁ of the differential circuit 1. For example, the differential circuit 6 is configured as shown in FIG. This circuit is composed of a differential section and two pairs of emitter followers. Differential part is NPN
Transistors 601, 602, emitter resistors 605, 6
06, load resistors 607 and 608, current sources 609 and 610
including. Two pairs of emitter followers are NPN
It includes a transistor 603 and a current source 611, and an NPN transistor 604 and a current source 612. Also, 61
3 and 614 are positive and negative input terminals of the differential circuit 6, and 6
15 and 616 are positive and negative output terminals of the differential circuit 6,
630 is a power supply terminal for the power supply potential V _CC .

More specifically, the collector of the transistor 601 is connected to the power supply terminal 630 via the node F and the load resistor 608, the emitter of the transistor 601 is grounded via the node C and the current source 609, and the transistor 601 is connected to the ground. The base is connected to the positive input terminal 613 of the differential circuit 6. The collector of the transistor 602 is connected to the power supply terminal 630 via the node E and the load resistor 607, the emitter of the transistor 602 is grounded via the node D and the current source 610,
The base of the transistor 602 is connected to the negative input terminal 614 of the differential circuit 6. Further, the node C and the node D are connected by resistors 605 and 606. The collector of the transistor 603 is connected to the power supply terminal 630, the base is connected to the node E, the emitter is grounded via the current source 611, and the positive output terminal 615 of the differential circuit 6 is connected. There is. Transistor 60
4 has its collector connected to the power supply terminal 630, its base connected to the node F, and its emitter connected to the current source 612.
The negative output terminal 6 of the differential circuit 6 while being grounded via
It is connected to 16.

When the potential V ₅ of the positive input terminal 613 and the potential _{6 of the} negative input terminal 614 are equal, the potentials of the node C and the node D are equal due to the symmetry of the circuit. Therefore, no current flows through the emitter resistors 605 and 606. Therefore, if the current values of the current sources 609 and 610 are equal to I _EE , the emitter currents of the transistors 601 and 602 are equal to I _EE . The current amplification factor (ratio of the collector current to the base current) of these transistors is usually sufficiently large that the collector currents of the transistors 601 and 602 are almost the emitter current, that is, I _EE . Therefore, assuming that the resistance values of the load resistors 607 and 608 are R _L , the potentials of the nodes E and F are V _CC −I _EE · R _L. Furthermore, the base-emitter voltage of the transistor 603 and 604, that is, a voltage shift of the emitter follower and V _EF, the common mode output voltage V ₀₂ of the differential circuit _{6, V 02 = V CC -I E} · R L -V _EF ... (11) The voltage shift amount V _EF of the emitter follower does not have a large variation range of about 0.7 V to 0.9 V in a practical design, but V _CC or the product of I _E and R _L is designed appropriately. As a result, V ₀₂ can be matched with the in-phase output voltage V ₀₁ of the differential circuit 1.

The above is established regardless of the circuit format of the differential circuit 1, but particularly when the differential circuit 1 has the same circuit format as the differential circuit 6, it is easy to obtain the same in-phase output voltage. For example, the differential circuit 1 also has a circuit format as shown in FIG. Further, the same power supply voltage V _CC is applied to the two differential circuits 1 and 6. Further, the product I _E · R _L of the value of the current source and the value of the load resistance of the differential section is made the same. As described above, the voltage shift amount V _EF of the emitter follower does not change much irrespective of the design, so that by making V _CC and I _E · R _L equal, a substantially equal in-phase output voltage can be obtained. In order to equalize I _E · R _L , it suffices to use current sources and load resistors of the same value for the differential circuits 1 and 6.

Further, when configuring the current sources and resistors of the differential circuits 1 and 6, the unit current sources and unit resistors of the same value can be connected in parallel or in series. For example, as shown in FIG. 4, in the differential circuit 6, one unit current source forms the current sources 609 and 610 in the differential section, and two unit resistors connected in direct current form the load resistors 607 and 608. In the differential circuit 1, there is also a method in which two unit current sources connected in parallel form a current source of a differential section and one unit resistor forms a load resistance. On the contrary, as shown in FIG. 5, two unit current sources connected in parallel in the differential circuit 6 form the current sources 609 and 610 of the differential section, and one unit resistor forms the load resistors 607 and 608. On the other hand, in the differential circuit 1, one unit current source may form the current source of the differential section, and two unit resistors connected in series may form the load resistance.

As described above, when the elements and circuits having the same value are used in the same circuit form, the in-phase output voltages of the differential circuits 1 and 6 easily become equal. Elements having the same value and circuits having the same characteristic can be easily obtained by forming the same pattern on the same semiconductor substrate in the same step. As described above, not only the product of the current source value and the load resistance value of the differential section is made the same, but all the elements related to the common mode voltage, that is, the resistors 605 and 606 of the elements shown in FIG. When the characteristics of the elements other than the above are formed so as to be the same in the differential circuits 1 and 6, the in-phase output voltages of these two differential circuits 1 and 6 automatically become completely equal. As described above, the in-phase output voltages of the differential circuits 1 and 6 can be easily equalized.

When a difference occurs in the potentials of the positive input terminal 613 and the negative input terminal 614, the potentials of the nodes C and D are different. As defined above, the potentials of the positive input terminal 613 and the negative input terminal 614 are V ₅ and V _6, and the base-emitter voltages of the transistors 601 and 602 are V _BE1 and V 6.
Let _BE2 and the potentials of the nodes C and D be V _C and V _D , V _C
= Becomes a _{V 5 -V BE1, V D =} V 6 -V BE2, unless no extreme difference in the emitter currents of the transistors 601 and 602, V _BE1 and V _BE2 is almost equal. Therefore, the potential difference V _C -V _D between the node C and the node D is almost equal to the input potential difference V ₅ -V ₆ . Therefore, node C
The current ΔI _EE flowing from D to D is ΔI _EE = (V ₅ −V ₆ ) / 2R _E (12), where R _E is the resistance value of the resistors 605 and 606. The load resistor 608 flows with the current I _EE of the current source 609 added with the above ΔI _EE , and the load resistor 607 flows with the current I _EE of the current source 610 subtracted by the above ΔI _{EE, and} thus the potentials of the nodes E and F. V _E and V _F is, V _E = V _CC - given by _{(I EE + ΔI EE) R} L ... (14) - (I EE -ΔI EE) R L ... (13) V F = V CC. Since the voltage shift amount of the emitter follower is equal on the transistor 603 side and the transistor 604 side, the output potential difference of this differential circuit is finally given by V _E −V _F. Therefore, the differential gain A ₂ is given by the following equations (11) to (13): A ₂ = (V _E −V _F ) / (V ₅ −V ₆ ) = R _L / R _E (15) Therefore, by setting such that R _L = R _E, easily differential circuit of the differential gain 1 is obtained.

In the above discussion, the transistor 601,
Although it has been approximated that the base-emitter voltages V _{BE 1} and V _BE2 of 602 are equal, in reality, the emitter current is modulated by ΔI _EE , and V _BE1 and V _BE2 are slightly different. As a method of correcting this effect and accurately setting the differential gain to 1, as shown in FIG. 6, for example, transistors 801 and 802 having the same characteristics as the transistors 601 and 602 are diode-connected to form a load resistor 607 and a power supply. There is a method of inserting between the terminals 630 and between the load resistor 608 and the power supply terminal 630, so that it is easy to set the differential gain to 1 accurately.

FIG. 7 is an electric circuit diagram of a sample and hold device B according to another embodiment of the present invention. In the above embodiment, the positive output terminal 12 of the sample hold device A and the reference voltage application terminal 23 of the positive diode bridge 2 are commonly used as the positive output terminal of the differential circuit 6 and the negative output terminal 13 of the sample hold device A. The reference voltage application terminal 33 of the negative diode bridge 3 was commonly connected to the negative output terminal of the differential circuit 6. In such a connection, when the diode bridges 2 and 3 driven by the clock generate clock noise, the output of the sample hold device A may be adversely affected. FIG. 7 shows an embodiment for avoiding this. Reference numeral 60 denotes a second differential circuit, which has a pair of output terminals other than the first positive output terminal 615 and the first negative output terminal 616, that is, the second positive output terminal 617 and the second negative output. It has a terminal 618. The second positive output terminal 617 is connected to the reference voltage application terminal 23 of the positive diode bridge 2, and the second negative output terminal 618 is connected to the reference voltage application terminal 33 of the negative diode bridge 3. The first positive output terminal 615 is connected to the sample hold device B.
To the positive output terminal 12 of the sample-hold device B, and the first negative output terminal 616 is connected to the positive output terminal 13 of the sample-hold device B.

The first positive output terminal 615 and the second positive output terminal 617 generate the same voltage, and the first negative output terminal 61.
6 and the second negative output terminal 618 generate equal voltages.
Therefore, the operation is similar to that of the first embodiment,
The positive output terminal 12 of the sample hold device B and the reference voltage application terminal 23 of the positive diode bridge 2 are separated from each other, and the negative output terminal 13 of the sample hold device B and the reference voltage application terminal 33 of the negative diode bridge 3 are separated from each other. .
Therefore, in such a connection, even if the diode bridges 2 and 3 driven by the clock generate clock noise, the output of the sample hold device B is not adversely affected.

The differential circuit 60 as described above can be easily realized. FIG. 8 shows an example of the configuration. In this configuration, the NPN transistor 61 is connected to the node E of the differential circuit 6 shown in FIG.
9 and an emitter follower composed of a current source 621 are connected to a node F by an NPN transistor 620 and a current source 622.
Is an emitter follower. That is, the base of the transistor 619 is connected to the node E, the collector is connected to the power supply terminal 630, the emitter is grounded through the current source 621, and the second positive output terminal 617 is connected. The base of the transistor 20 is connected to the node F, the collector is connected to the power supply terminal 630, the emitter is grounded through the current source 622, and the second negative output terminal 618 is connected. Here, the input / output characteristics of the emitter follower are described as follows.
3, current source 611, transistor 604, current source 612
If the input / output characteristics of the emitter follower are made equal, the first positive output terminal 615 and the second positive output terminal 617 are formed.
Generate equal voltages, the first negative output terminal 616 and the second negative output terminal 616
The negative output terminals 618 of the two generate the same voltage.

If the differential circuit 1 is formed in the same circuit as the differential circuit 60 as in the embodiment shown in FIGS. 1 to 6, the same in-phase output voltage can be easily obtained. In addition, as shown in FIG. 9, the current sources 609 and 610 of the differential circuit 60 are formed by one unit current source, and the load resistors 607 and 608 are formed by two unit resistors, while the current of the differential circuit 1 is changed. The source may be formed by two unit current sources and the load resistance may be formed by one unit resistance. Further, as shown in FIG. 10, the current sources 609 and 610 of the differential circuit 60 are formed of two unit current sources, and the load resistors 607 and 608 are formed of one unit resistor, while the current of the differential circuit 1 is formed. Forming the source with one unit current source,
The load resistor may be formed by two unit resistors. Further, as shown in FIG. 11, in order to correct the difference between the base-emitter voltages V _BE1 and B _BE2 of the transistors 601 and 602 so that the differential gain becomes exactly 1, the diode-connected transistors 801 and 802 are connected to the power supply terminals. 630 and load resistance 60
It may be connected between 7,608.

FIG. 12 is an electric circuit diagram of a sample hold device C according to still another embodiment of the present invention. In the above embodiment, the positive and negative input terminals of the second differential circuits 6 and 60 are the diode bridges 2 and 3 on the positive side and the negative side, respectively.
, But the output potential difference between the diode bridges 2 and 3 on the positive side and the negative side is different from that of the differential circuit 6, 60.
It suffices to be transmitted to the positive and negative input terminals of, and the configuration shown in FIG. In FIG. 12, 7 is a buffer circuit, and a potential difference equal to the potential difference between the input terminals 701 and 703 is output as the potential difference between the output terminals 702 and 704. The buffer circuit 7 has a structure as shown in FIG. Between the input terminal 701 and the output terminal 702, N
An NPN transistor 712 and P-channel MOS transistors 714 and 715 are added to an emitter follower composed of a PN transistor 711 and a current source 713. More specifically, the base of the transistor 711 is connected to the input terminal 701, the emitter is connected to the output terminal 702, and the current source 713 is connected.
Is grounded through and its collector is a transistor 712.
Connected to the emitter. The collector of the transistor 712 is connected to the power supply terminal 630, and its base is connected to the drain and gate of the transistor 714. The gates of the transistors 714 and 715 are connected to each other, and the sources thereof are connected to the power supply terminal 630. The drain of the transistor 715 is connected to the input terminal 701. Further, between the input terminal 703 and the output terminal 704, an N-type transistor 721 and a current source 723 form an emitter follower,
A PN transistor 722 and P-channel MOS transistors 714 and 715 are added, and these are connected in the same manner as between the input terminal 701 and the output terminal 702.

Since the emitter currents of the transistors 711 and 712 are the same, the base currents of the transistors 711 and 712 are the same. The transistors 714 and 715 form a current mirror, and the drain current of the transistor 15 becomes equal to the drain current of the transistor 714.
Therefore, the base current required for the transistor 711 is supplied from the drain of the transistor 715, and it is not necessary to supply the current from the input terminal 701. The same applies to the circuit including the transistors 721, 722, 724, 725 and the current source 723. Therefore, the input current of this buffer circuit 7 is zero. During the hold period, the capacitors 4 and 5 are electrically disconnected from the diode bridges 2 and 3. At the same time, however, the input current of the buffer circuit 7 is always 0, so the holding charge stored in the capacitors 4 and 5 is kept. Does not leak, and therefore the output of the sample hold device C does not drift during the hold period.

[0033]

As described above, in the first sample and hold device of the present invention, as means for outputting the potential equal to the potential held in the positive and negative capacitors,
Since only one differential circuit that does not require feedback is used, the operation is more stable and the occupied area is smaller than the conventional example in which two operational amplifiers whose outputs are fed back to the input are used as the means. small.

If a buffer circuit that outputs a voltage equal to the input voltage with an input current of 0 is connected between the positive and negative capacitors and the differential circuit, the retained charge stored in the capacitor leaks during the hold period. And the output of the sample and hold device does not drift.

Further, in the second sample and hold device of the present invention, in addition to the first and second output terminals which provide the output of the sample and hold device, the third and fourth outputs which provide independent outputs. Including a terminal and its output is the first
Since the voltage is applied to the reference voltage application terminal of the second switch means, the output of the sample hold device is not adversely affected even when noise occurs in the switch means.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a sample and hold device according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the sample hold device shown in FIG.

FIG. 3 is an electric circuit diagram showing a second differential circuit of the sample hold device shown in FIG.

FIG. 4 is an electric circuit diagram showing another configuration of the second differential circuit shown in FIG.

5 is an electric circuit diagram showing still another configuration of the second differential circuit shown in FIG.

FIG. 6 is an electric circuit diagram showing still another configuration of the second differential circuit shown in FIG.

FIG. 7 is an electric circuit diagram of a sample and hold device according to another embodiment of the present invention.

8 is an electric circuit diagram showing a second differential circuit of the sample hold device shown in FIG. 7. FIG.

9 is an electric circuit diagram showing another configuration of the second differential circuit shown in FIG.

10 is an electric circuit diagram showing still another configuration of the second differential circuit shown in FIG.

11 is an electric circuit diagram showing still another configuration of the second differential circuit shown in FIG.

FIG. 12 is an electric circuit diagram of a sample and hold device according to still another embodiment of the present invention.

FIG. 13 is an electric circuit diagram showing a buffer circuit of the sample hold device shown in FIG.

FIG. 14 is an electric circuit diagram of a conventional sample hold device.

FIG. 15 is an electric circuit diagram showing a diode bridge circuit of the sample hold device shown in FIG.

[Explanation of symbols]

1 1st differential circuit 2 Positive side diode bridge circuit (1st switch means) 3 Negative side diode bridge circuit (2nd switch means) 4 1st capacitor 5 2nd capacitor 6,60 2nd difference Moving circuit 7 Buffer circuit A, B, C Sample and hold device

Claims (3)

[Claims] 1. A differential sample and hold device for sampling and holding a voltage difference between two inputted analog signals, which comprises first and second input terminals and first and second output terminals. A first differential circuit having an output voltage difference between the first and second output terminals that changes in accordance with an input voltage difference between the first and second input terminals, An input terminal connected to the first output terminal of the first differential circuit; and an output terminal electrically connected to the input terminal in the sampling period and electrically cut off from the input terminal in the hold period. A first switch means having the input terminal, an input terminal connected to a second output terminal of the first differential circuit, and an input terminal electrically connected to the input terminal during a sampling period and the input terminal during a hold period. And electrical A second switch means having an output terminal that is cut off by a first capacitor, and a first capacitor whose one electrode is connected to the output terminal of the first switch means and whose other electrode is connected to a constant potential node, A second capacitor whose one electrode is connected to the output terminal of the second switch means and whose other electrode is connected to a constant potential node, and a first capacitor which is connected to one electrode of the first capacitor An input terminal, a second input terminal connected to one electrode of the second capacitor, a first output terminal and a second output terminal, and a potential substantially equal to the potential of the first input terminal is provided. And a second differential circuit that generates a potential from the second output terminal that is generated from the first output terminal and is approximately equal to the potential of the second input terminal. 2. Between one electrode of the first capacitor and a first input terminal of the second differential circuit, and the second input terminal of the second differential circuit.
2. A buffer circuit, which has an input current of 0 and outputs the same voltage as the input voltage, is connected between one electrode of the capacitor and the second input terminal of the second differential circuit. Sample hold device. 3. A differential sample and hold device for sampling and holding a voltage difference between two inputted analog signals, which comprises first and second input terminals and first and second outputs. A first differential circuit having a terminal and the output voltage difference between the first and second output terminals changes according to the output voltage difference between the first and second input terminals; An input terminal connected to the first output terminal of the first differential circuit, an output terminal electrically connected to the input terminal during the sample period and electrically disconnected from the input terminal during the hold period, And a first switch means having a reference voltage application terminal to which a reference voltage for limiting the voltage of the internal node is applied during the hold period; and a second output terminal of the first differential circuit. Input terminal, Sun An output terminal that is electrically connected to the input terminal during the pull period and electrically cut off from the input terminal during the hold period, and a reference voltage for limiting the voltage of the internal node during the hold period is applied. Second switch means having a reference voltage application terminal for operating the first switch means, and a first capacitor having one electrode connected to the output terminal of the first switch means and the other electrode connected to a constant potential node. A second capacitor whose one electrode is connected to the output terminal of the second switch means and whose other electrode is connected to a constant potential node; and a first capacitor connected to one electrode of the first capacitor. Input terminal, a second input terminal connected to one electrode of the second capacitor, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal. Has a terminal, wherein the potential substantially equal to the potential of the first input terminal the first and third
Generated from the output terminal of the first switch means, a potential substantially equal to the potential of the second input terminal is generated from the second and fourth output terminals, and a potential generated from the third output terminal is generated from the first switch means. A second differential circuit for applying the reference voltage application terminal to the reference voltage application terminal of the second switch means and applying the potential generated from the fourth output terminal to the reference voltage application terminal.