JPH06274441A - Serial interface for cpu - Google Patents

Abstract

PURPOSE:To send a serial signal to a control object from a CPU at a high speed, with less processing burden by a hardware of a small scale. CONSTITUTION:An I/O PORT is connected to a parallel address bus B1 and a parallel data bus B2 of a CPU. An ADRDEC decodes an address, and enables selectively write enable signals (WD1, WD2, WA1, WA2) to each register. In SDTREGs 1, 2, parallel data signals (D15-D0) are written. In SADREGs 1, 2, parallel address signals (A15-A0) are written. A P/Ss (D), (A) convert the data and the address of the SDTREGs 1, 2 and the SADREGs 1, 2 into serial signals, and send them to a control object. A START receives a final pulse signal WA2 of the ADRDEC and allows the P/Ss (D), (A) to be subjected to output operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface for converting a parallel data signal output from a CPU in a control unit of a transmission device into a serial data signal and outputting the serial data signal to a controlled object.

[0002]

2. Description of the Related Art A serial interface generally has a serial interface as a CPU interface because it has fewer wirings than a parallel interface and is less likely to malfunction during hot-plugging and unplugging. ing.

FIG. 3 shows a block diagram of a conventional serial interface. CPU and I / O port (hereinafter I / O
8bit parallel address bus B during PORT)
1 (AD0 to 7), parallel data bus B2 (DT0 to DT0)
7) and the write enable signal (WR) line W. Clock input to I / O PORT (CL
K) is a serial interface timing signal.

An output signal from the I / O PORT to a control target (not shown) is serially converted 16 bi.
t address (SAD), serially converted 16-bit data (SDT), signal for receiving side to identify address information on SAD (ASCN), signal for receiving side to identify data on SDT ( DSC
N), and the timing signal (CLK) of the serial interface.

The I / O PORT includes an address decoder section (hereinafter referred to as ADR DEC), a transmission address register section (hereinafter referred to as SAD REG1, 2), a transmission data register section (hereinafter referred to as SDT REG1, 2), and a control command. It is composed of a register unit (hereinafter CONTREG), a parallel-serial conversion unit (hereinafter P / S (A), P / S (D)), and a start control unit (hereinafter START).

The ADR DEC decodes an address, and when it matches the unique address of each I / O PORT, a write enable signal (WD1, WD2, WA1, WA) for each register in the I / O PORT is obtained.
2, WC). Which is enabled depends on the address information.

In SDT REG1, the upper 8 bits (D15 to D8) of the data transmitted by the I / O PORT are W
Written on the rising edge of D1. SDT RE
In G2, the lower 8 bits of the data transmitted by the I / O PORT
Bits (D7-D0) are written on the rising edge of WD2. I / O PORT for SAD REG1
The upper 8 bits (A15 to A8) of the address transmitted by are written at the rising edge of WA1. SAD R
The lower 8 bits (A7 to A0) of the address transmitted by the I / O PORT are written in EG2 at the rising edge of WA2. CONT REG has a signal (SR) for controlling transmission of serial address and data.
Q) is written. P / S (D) is SDT REG
The parallel data held in 1 and 2 receives the timing signal TIMD and is converted into serial data. P /
S (A) receives the timing signal TIMA and converts the parallel address held in SAD REG1, 2 into a serial address. When SRQ is enabled, START sends timing signals TIMA and TIMD necessary for parallel-serial conversion of address and data, and P / S (A) and P / S (D) send address and data. While it is active, ASCN and DSCN are activated.

FIG. 4 is a timing chart showing the operation of the conventional serial interface.

In FIG. 4, at time T1, SDT RE
The data D15 to D8 are written to G1, and the data D7 to D0 are written to SDT REG2 at time T2.
At time T3, addresses A15 to A8 are sent to SAD REG1.
Are written, and at time T4, addresses A7 to A0 are written in SAD REG2. At time T5, CONT
It is written to REG so that the SRQ signal is 0, and at time T6, it is written so that the SRQ signal is 1.

Writing is performed according to the address on the address bus from the CPU, SDT REG1, SDT REG
2, SAD REG1, SAD REG2, CONT R
One of EG is selected and is performed at the rising edge of the WR signal.

At time t1, the SRQ signal changes from Low to High.
When it changes to h, the transmission of the serial address (SAD) and the serial data (SDT) is started from the rising time t2 of the CLK signal immediately after that. Then, the transmission is continued for time T7, and at time t3, the transmission of all bits is completed.

[0012]

The above-mentioned conventional serial interface has the following problems.

1. CPU sends data (D15-D
0), after writing the transmission address (A15 to A0) in the register, an operation for controlling the SRQ signal of CONT REG to execute the transmission is required, thus burdening the firmware. 2. Because of the above 1, the number of steps of the program increases, and the processing speed becomes slow. 3. Since the CONT REG is required to control the transmission, the I / O PORT hardware becomes large in scale.

Therefore, an object of the present invention is to provide a serial interface for a CPU, which has a small load on firmware and hardware, a high processing speed, and a small hardware scale.

[0015]

In order to solve the above problems, the present invention converts a parallel data signal sent from a CPU through a parallel bus into a serial signal through a register and a parallel-serial conversion unit, and converts the serial signal into a serial signal. The serial interface of the CPU is configured to use the final pulse signal for writing data in the register as the transmission trigger of the serial signal in the input / output port for transmitting to the controlled object.

[0016]

According to the present invention, when transmitting serial data, the transmission trigger for transmitting the serial data signal based on the final pulse signal for writing the data in the register is transmitted to the parallel-serial conversion unit. As it is sent, the data transmission is automatically started. Therefore, the conventional register for transmitting serial data and the control therefor are not required, and the above-mentioned defects in firmware and hardware are eliminated.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A CPU according to the present invention will now be described with reference to the accompanying drawings.
An example of the I / O interface will be described in detail. It should be noted that the same components as those of the conventional one are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 shows a block diagram of the serial interface of the CPU. The I / O interface of this CPU is similar to the conventional one, and the CPU and a plurality of I / O PO
It is composed of RT, and an 8-bit parallel bus address is provided between the CPU and the I / O PORT.
The data bus and the write enable signal WR line are connected.

The inside of the I / O PORT is ADR DE
C, SAD REG1,2, SDTREG1,2, P /
It is composed of S (A), P / S (D), and START. I
/ OPT is the same as the conventional one, SAD, SD
It outputs T, ASCN, DSCN, and CLK signals.
What is different from the conventional examples is that I / O PORT
CONT REG provided inside to control transmission
Is omitted, and the write pulse signal WA2 of the lower bits (A7 to A0) of the transmission address is input to START.

FIG. 2 is a timing chart showing the operation of the serial interface of this embodiment. At time T1, W
The upper bits (D15 to D8) of the transmission data are written in SDT REG1 at the rising edge of D1. At time T2, SDT REG2 at the rising edge of WD2
The lower bits (D7 to D0) of the transmission data are written in. At time T3, SAD is generated at the rising edge of WA1.
Upper bits of transmission address in REG1 (A15 to A8)
Is written. At time T4, the lower bits (A7 to A0) of the transmission address are written in SAD REG2 at the rising edge of WA2.

At time t1 in the figure, writing of A7 to A0 is completed, but immediately after that, at time t2 at the rising edge of CLK, ASCN and DSCN are activated to transmit serial address (SAD) and serial data (SDT). Start. That is, when the start control unit in FIG. 1 detects the rising edge of WA2, transmission is started. And T
Transmission is performed only for 5 hours, and ASCN and DSC are sent at time t3.
The N is turned off and the transmission ends.

Data to be transmitted at time T1 to T4, address (1) upper bits (D15 to D8) of transmission data,
(2) Lower bits (D7 to D0) of transmission data, (3)
Writing is performed in the order of the upper bits (A15 to A8) of the transmission address and (4) the lower bits (A7 to A0) of the transmission address, and when all the bits have been written, I / OPO
At RT, serial addresses and data are automatically transmitted.

[0023]

As described above, according to the interface of the present invention, when the lower bit of the address transmitted by the I / O PORT is written, the transmission of serial data and address is automatically started. It is possible to expect an effect that the burden on the firmware is reduced because it is not necessary to take a procedure for executing the transmission on the firmware. Further, this can reduce the number of steps of the program, which has the advantage of increasing the processing speed. Further, since a control register for controlling transmission is not required, it is possible to expect a reduction in hardware scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a serial interface of a CPU according to the present invention.

FIG. 2 is a timing chart of a serial interface according to the present invention.

FIG. 3 is a block diagram of a conventional serial interface.

FIG. 4 is a timing chart of a conventional serial interface.

[Explanation of symbols]

CPU central processing unit I / O PORT input / output port B1 parallel address bus B2 parallel data bus ADR DEC address decoder SAD REG1, transmission address register SDT REG1, transmission data register P / S (A) transmission address Parallel-serial conversion unit P / S (D) transmission data parallel-serial conversion unit START start control unit

Claims (1)

[Claims] 1. A register (SAD REG, SDT REG) for parallel data signals sent from a CPU through a parallel bus.
And a serial interface of the CPU having an input / output port (I / OPORT) for converting the serial data signal through the parallel-serial conversion unit (P / S) and transmitting the serial data signal to the control target. Is transmitted based on the final pulse signal (WA2) for writing data to the registers (SAD REG, SDT REG).