JPH06274410A - Display control system - Google Patents

Abstract

PURPOSE:To improve a read-out speed of image data by utilizing effectively a high speed access mode of an image memory and prefetch of the image data. CONSTITUTION:By an access mode deciding circuit 144, an access mode of a CPU 1 or a plotting coprocessor 13 is predicted and decided, and in accordance with a result of its decision, a prefetch processing and a VRAM access mode are controlled. Accordingly, only in the case of a continuous access of address continuation, the prefetch processing and a page mode access can be utilized, and the efficiency for read-out of data from a dual port image memory 30 can be enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control system, and more particularly to a display control system used in a computer such as a personal computer or a workstation.

[0002]

2. Description of the Related Art In a personal computer or the like, when displaying image data such as characters and figures on a display, a display control system accesses a frame buffer in accordance with an access request from a processor to access the image data. Make a change. In this case, the drawing performance of the processor is determined by the access speed of the image memory used as the frame buffer.

When writing data to the frame buffer, it is possible to speed up the processing by releasing the processor quickly by a method such as write buffering. However, in reading data, the processor is used until the image data is read from the image memory. Therefore, the reading of the image data is one of the factors that deteriorate the drawing performance of the processor.

The access mode of the image memory includes a high speed access mode such as a page mode. By using this high-speed access mode, a plurality of image data can be read from the image memory in one cycle.

The memory access instruction of the processor includes a normal memory access instruction and a string move instruction (continuous data transfer instruction). The string move instruction (continuous data transfer instruction) is an instruction to read / write a data string having continuous addresses. If the image memory is accessed in the high-speed access mode when the string move instruction is executed, necessary image data can be transferred to the processor at high speed, and the processor does not have to wait.

However, in the case of random access with address discontinuity as in a normal memory access instruction, if the image memory is accessed in the high speed access mode, useless data transfer occurs, which rather reduces the drawing performance of the processor. It will be. Therefore, in the conventional display control system, the high speed access mode is usually not used.

Further, although there is a data prefetching method for speeding up the reading of image data from the image memory, prefetched data is often wasted because it is not used when there are many random accesses. In this case, useless image memory access will occur due to prefetching, and the access performance will be degraded accordingly.

[0008]

Conventionally, it is impossible to determine whether the instruction executed by the processor is a memory access instruction for random access with address discontinuity or a string move instruction for continuous access with address continuity. However, the high speed access mode of the image memory and the prefetch of the image data cannot be effectively used, and it takes a long time to read the image data by the processor.

The present invention has been made in view of the above circumstances, and makes it possible to control access to the image memory in accordance with the type of instruction executed by the processor, and to perform high-speed access mode of the image memory and image data. An object of the present invention is to provide a display control system capable of reading image data by effectively utilizing prefetch.

[0010]

A display control system according to the present invention includes an image memory for storing image data generated by a processor, and a display for displaying the image data stored in the image memory on a display. The read access by the processor according to the means and a history of changes in the read address supplied from the processor. According to the access mode determination means for determining and the determination result of this access mode determination means,
A first feature is that the image memory is provided with a memory control unit that performs read access in one of a first access mode and a second access mode that is faster than the first access mode.

In this display control system, whether the read access by the processor is continuous access or random access is determined according to the history of changes in the read address supplied from the processor, and the image is determined according to the determination result. The memory access mode is switched. Therefore, access control of the image memory according to the type of instruction executed by the processor can be realized, and the high-speed access mode of the image memory can be effectively used.

Further, according to the present invention, an image memory for storing the image data generated by the processor, a display means for displaying the image data stored in the image memory on a display, and a pre-read from the image memory. According to a history of change in the read address supplied from the processor, which stores image data, a prefetch buffer configured to read the image data in response to a read request from the processor,
Access mode determining means for determining whether or not the read access by the processor is a continuous access mode for sequentially reading continuous data in address order, and the access mode determining means determines that the continuous access mode is set. In this case, a second feature is that the image processing apparatus further comprises a prefetch unit that reads out image data of an address subsequent to the image data requested to be read by the processor from the image memory and prefetches the image data into the prefetch buffer.

In this display control system, it is determined whether the read access by the processor is continuous access according to the history of changes in the read address supplied from the processor, and prefetching is performed only in the case of continuous access. . In the case of continuous access, since the data read next by the processor and the prefetched data match, the image data can be read from the prefetch buffer at high speed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a display control system according to an embodiment of the present invention. This display control system 4 is, for example, 1024 × 768 dots, 2
XGA (eXtended) that has a display mode of simultaneous display of 56 colors
It is a display control system of the Graphics Array) specification and is connected to the system bus 3 of the portable computer. The display control system 4 controls the display of both the flat panel display 40 that is standardly equipped in the main body of the portable computer and the color CRT display 50 that is optionally connected.

The display control system 4 includes a display controller 10 and a dual port image memory (V
RAM) 30 is provided. These display controller 10, dual port image memory (VRA
M) 30 is mounted on a circuit board (not shown).

The display controller 10 is an LSI realized by a gate array and is a main part of the display control system 4. The display controller 10 executes display control for the flat panel display 40 and the color CRT display 50 using a dual port image memory (VRAM) 30 according to an instruction from the host CPU 1. Further, the display controller 10 functions as a bus master and can directly access the main memory 2 of the computer.

Dual port image memory (VRAM) 3
0 has a serial port (serial DATA) used for serial access and a parallel port (DATA) for random access. The serial port (serial DATA) is used to read data for refreshing the display screen, and the parallel port (DA).
TA) is used to update image data. The dual-port image memory (VRAM) 30 is composed of a plurality of dual-port DRAMs and has 1 Mbyte to 4 Mbytes.
It has a storage capacity of M bytes. The dual port image memory (VRAM) 30 is used as a frame buffer, and image data to be displayed on the flat panel display 40 or the color CRT display 50 is drawn.

In this case, the XGA specification drawing data created by an application program or the like conforming to the XGA specification is stored in the dual port image memory (VRAM) 30 by the packed pixel method. The packed pixel method is a color information mapping format in which one pixel is represented by a plurality of consecutive bits on a memory.
A method of representing pixels by 1, 2, 4, 8 or 16 bits is adopted. On the other hand, the VGA specification drawing data is V
It is created by an application program or the like conforming to the GA specifications, and is drawn in the dual port image memory (VRAM) 30 by the memory plane method.
This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address and color information of each pixel is assigned to these planes. For example, 4
If you have planes, one pixel is 1 for each plane.
It is represented by a total of 4 bits of data, bit by bit. Also, a dual port image memory (VRAM) 30
The text data is also stored in. The text data for one character has a total size of 2 bytes including an 8-bit code and an 8-bit attribute in both the XGA and VGA specifications. The attributes are
It is composed of 4-bit data specifying the foreground color and 4-bit data specifying the background color.

The display controller 10 includes a register control circuit 11 and a system bus interface 1
2, a drawing coprocessor 13, a memory control circuit 14,
CRT controller (CRTC) 16, serial port control circuit 18, sprite memory 19, serializer 2
0, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CRT video multiplexer 2
6, sprite control circuit 27, flat panel emulation circuit 28, and DAC (D / A converter)
It is composed of 35.

The register control circuit 11 receives an address and data from the system bus 3 via the system bus interface 12 and performs address decoding and read / write control for various registers designated by the decoding result. . The system bus interface 12 controls the interface with the host CPU 1 via the system bus 3, and supports a bus interface conforming to various specifications such as ISA, EISA, micro channel, and local bus.

The drawing coprocessor 13 is a graphic accelerator, and provides various drawing functions to drawing data in the dual port image memory (VRAM) 30 in response to an instruction from the CPU 1. This drawing coprocessor 13 transfers a block of pixels such as BITBIL, line drawing, area filling, logical / arithmetic operation between pixels, screen cutout, map mask, XY coordinate addressing, and paging memory. It has management functions. This drawing coprocessor 13 has a V
GA / XGA compatible data operation circuit 131, two-dimensional address generation circuit 131, and paging unit 133
Is provided.

The data operation circuit 131 performs data operations such as shifts, logical arithmetic operations, bit masks and color comparisons, and also has a VGA compatible BITBLT function. The two-dimensional address generation circuit 131 generates an XY two-dimensional address for accessing a rectangular area or the like. The two-dimensional address generation circuit 131 also performs a region check and a conversion process to a linear address (real memory address) using segmentation or the like. The paging unit 133 is for supporting the same virtual memory mechanism as the CPU 1, and converts the linear address created by the two-dimensional address generation circuit 131 into a real address by paging when paging is valid. Further, when paging is invalid, the linear address becomes the real address as it is. The paging unit 133 has a TLB for paging. The memory control circuit 14 is for controlling access to the dual port image memory (VRAM) 30, and is parallel to the dual port image memory (VRAM) 30 in response to a read / write request of image data from the CPU 1 or the drawing coprocessor 13. Access control of the port is performed, and CRTC
Data read control from the serial port of the dual port image memory (VRAM) 30 is performed according to the display position address from 16. In this case, the memory control circuit 14
The dual port image memory (VRAM) 30 is accessed by the single access mode (normal mode) or the VRAM page mode. Further, the memory control circuit 14 has a frame buffer cache 141 and an access mode determination circuit 144 built therein.

The access mode determination circuit 144 is a CPU
1 or an instruction executed by the drawing coprocessor 13 is predicted / determined as to whether it is a string move instruction for continuous access with continuous addresses, and the access mode of the dual port image memory (VRAM) 30 is changed according to the result of the determination. Select. The prediction / judgment process is performed by the CPU
1 or according to the history of changes in the read address supplied from the drawing coprocessor 13 to detect whether or not continuous access is continuous.

The frame buffer cache 141 is C
It is used to speed up read / write of image data by the PU 1 and the drawing coprocessor 13. The frame buffer cache 141 is also used as a prefetch buffer that holds image data prefetched from the dual port image memory (VRAM) 30. In this case, the prefetch processing of the image data to the frame buffer cache 141 is executed when it is determined that the access by the CPU 1 and the drawing coprocessor 13 is continuous access, but it is determined that it is random access. In this case, the prefetched data is not used in many cases, so it is not executed.

When the image data requested to be read by the CPU 1 or the drawing coprocessor 13 exists in the frame buffer cache 141, the image data is read from the frame buffer cache 141 and the CPU
1 or to the drawing coprocessor 13. In this case, read access via the parallel port of the dual port image memory (VRAM) 30 is not performed.

The switching of the VRAM access mode using the judgment result of the access mode judgment circuit 144 and the control of the permission / prohibition of the prefetch processing to the frame buffer cache 141 are the features of the present invention. It will be described later in the second and subsequent description.

The CRT controller 16 has various display timing signals (horizontal synchronizing signal, vertical synchronizing signal) for displaying a screen on the flat panel display 40 or the CRT display 50 at a high resolution (for example, 1024 × 768 dots) conforming to the XGA specifications. Signals) and various display timing signals (horizontal synchronization signal, vertical synchronization signal, etc.) for displaying the screen on the flat panel display 40 or the CRT display 50 at a medium resolution (for example, 640 × 460 dots) that meets VGA specifications. Occurs selectively. The CRT controller 15 also generates a display address for reading image data to be displayed on the screen from the serial port (serial DATA) of the dual port image memory (VRAM) 30, and the memory control circuit 14
Supply to.

Serial port control circuit 18, sprite memory 19, serializer 20, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CR
T video multiplexer 26, sprite control circuit 2
The flat panel emulation circuit 28 and the DAC (D / A converter) 35 constitute a display circuit for displaying the image data of the dual port image memory (VRAM) 30 on the flat panel display 40 or the CRT display 50.

The serial port control circuit 18 generates a clock SCK and an output enable signal SOE for controlling the data read timing from the serial data port of the dual port image memory (VRAM) 30. In addition, the memory control circuit 18 uses the sprite memory 1
9 access control and sprite display timing control.

In the sprite memory 19, sprite data is written in the graphic mode, and fonts are written in the text mode. In the text mode, the code of the text data read from the dual port image memory (VRAM) 30 is supplied to the sprite memory 19 as an index, and the font corresponding to the code is read.

The serializer 20 is a parallel / serial conversion circuit that converts parallel pixel data for a plurality of pixels into pixel units (serial). In the graphic mode, the dual port image memory (VRAM) 30 is used.
The memory data read from the serial port and the sprite data read from the sprite memory 19 are parallel / serial converted, and the font data read from the sprite memory 19 is parallel / serial converted in the text mode.

The latch circuit 21 is for delaying the attribute output timing by the delay time of conversion from code data to font data, and is a dual port image memory (VRAM) in the text mode.
The attribute of the text data read from 30 is held. The foreground / background multiplexer 22 selects one of the foreground color (front color) and the background color (background color) of the attribute in the text mode. This choice is for serializer 2
The font data values output from 0 are controlled by "1" (foreground) and "0" (background). The graphic / text multiplexer 23 is for switching between the graphic mode and the text mode. In the graphic mode, the memory data output from the serializer 20 is selected, and in the text mode, the foreground / background multiplexer 22 is selected. Select an output.

The color palette control circuit 24 is for performing color conversion of graphic or text data. The color palette control circuit 24 includes a two-stage color palette table. The first color palette table is composed of 16 color palette registers. Each color palette register contains
6-bit color palette data is stored. The second color palette table is composed of 256 color palette registers. Each color palette register stores 18-bit color data composed of 6 bits for each of R, G, and B.

In the graphic mode, 8-bit / pixel XGA specification memory data is sent directly to the second color palette table without passing through the first color palette table, where R, G and B are each 6 Converted to color data composed of bits. Also,
The 4-bit / pixel VGA memory data is first sent to the first color palette table, where it is converted into 6-bit color data and output. And
To this 6-bit color data, 2-bit data output from the color selection register built in the color palette control circuit 19 is added, whereby a total of 8-bit color data is obtained. After that, the 8-bit color data is sent to the second color palette table, where it is converted into color data of 6 bits for each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA can be read via R, R, and R via the first and second two-stage color palette tables.
It is converted into color data composed of 6 bits for each of G and B.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits. In this case, the memory data of 16 bits / pixel does not go through the color palette control circuit 24. Are directly supplied to the CRT video multiplexer 26.

The sprite color register 25 specifies the sprite display color. CRT video multiplexer 2
Reference numeral 6 selects a CRT video display output, and selects the output of the color palette control circuit 24 or the direct color output from the serializer 20, and further performs the video switching of sprite display. The sprite control circuit 27 controls the CRT video multiplexer 26 in accordance with the sprite data converted from parallel / serial by the serializer 20, and controls video switching during sprite display. Flat panel emulation circuit 28 converts the CRT video output to produce flat video data for flat panel display 40.

The DAC 35 converts the CRT video data output from the CRT video multiplexer 26 into analog R, G, B signals and supplies them to the CRT display 50. Hereinafter, switching of the VRAM access mode, which is a feature of the present invention, and drawing processing using the frame buffer cache 141 will be described. FIG. 2 shows a first configuration example of the memory control circuit 14.

As shown, the memory control circuit 14 includes a frame buffer cache 141, a cache interface 142, a frame buffer control circuit 143, and an access mode determination circuit 144.

The cache interface 142 is C
An interface between each of the PU 1 and the drawing processor 13 and the frame buffer cache 141,
Upon receiving an image data access request from the CPU 1 or the drawing processor 13, the address and data included in the access request are transferred to the frame buffer cache 14
1, and also to the frame buffer control circuit 143 via the direct path P1. At this time, the cache interface 142 generates a read / write signal (R / W) indicating whether the access request is a read access or a write access, and supplies it to the frame buffer cache 141.

The frame buffer control circuit 143 connects the frame buffer cache 141 and the dual port image memory (VRAM) 30 in order to transfer the image data between the frame buffer cache 141 and the dual port image memory (VRAM) 30. Access control. When accessing the frame buffer cache 141, the frame buffer control circuit 143 sets the frame buffer control circuit 143 to the write mode or the read mode by the read / write signal (R / W). Further, the frame buffer control circuit 143 accesses the dual port image memory (VRAM) 30 in a normal access mode or a high speed access mode such as a page mode.

Image data is transferred between the frame buffer cache 141 and the dual port image memory (VRAM) 30 by replacing the image data in the frame buffer cache 141 or by changing the dual port image memory (VRAM).
This is performed for updating the image data in the RAM 30.

For example, in the read access of the frame buffer cache 141 executed by the CPU 1 or the drawing coprocessor 13, if a cache miss occurs, the frame buffer control circuit 143 transfers the read-requested image data to the dual port image memory. The data is read from the (VRAM) 30 and written in the frame buffer cache 141. As a result, the image data in the frame buffer cache 141 is replaced. The image data replacement processing of the frame buffer cache 141 is activated in response to a mishit signal supplied from the frame buffer cache 141.

Further, the frame buffer control circuit 143
Is a dual port image memory (VRAM) that periodically stores the image data written in the frame buffer cache 141 by the CPU 1 or the drawing coprocessor 13.
30, and the dual port image memory (VR
AM) 30 image data is updated.

This update process is performed to reflect the contents of the image data drawn in the frame buffer cache 141 in the dual port image memory (VRAM) 30, and a display timing signal (for example, from the CRTC 16). According to the vertical synchronizing signal), the display screen is refreshed once per frame period.

Further, the frame buffer control circuit 143 is provided with a prefetch circuit 143a for prefetching image data in the cache memory block 141a. The prefetch circuit 143a is for preliminarily storing in the cache memory block 141a image data for which read access is expected in the future by the CPU 1 or the drawing coprocessor 13.

The frame buffer cache 141 reads / writes image data according to a read / write request supplied from the CPU 1 or the drawing coprocessor 13 via the cache interface 142 or a read / write request from the frame buffer control circuit 143. Is configured to run. That is,
The frame buffer cache 141 is composed of a cache memory block 141a for holding image data and a control circuit 142a for controlling read / write of the cache memory block 141a.

The access mode determination circuit 144 is a CPU
1 or the access mode is predicted / determined according to the history of changes in the read address from the drawing coprocessor 13, and the frame buffer control circuit 14 is determined according to the determination result.
3 controls the prefetch operation and the page mode access operation. The access mode prediction / judgment processing of the access mode judgment circuit 144 is activated in response to a read / write (R / W) signal indicating a read access supplied from the cache interface 142, and at that time, the CPU 1 or the drawing coprocessor 13 is activated. The addresses supplied from the are sequentially fetched by the access mode determination circuit 144.

The determination result by the access mode determination circuit 144 is supplied to the frame buffer control circuit 143. When the access mode determination circuit 144 determines that the access by the CPU 1 or the drawing coprocessor 13 is continuous access, the frame buffer control circuit 143 permits the prefetch processing and the page mode access, and the access is random access. If determined, the frame buffer control circuit 143 is prohibited from executing the prefetch process and page mode access. In FIG. 3, the access mode determination circuit 144 is shown.
An example of a concrete circuit configuration of is shown.

The access mode determination circuit 144 includes a register 701, a subtractor 702, and a comparator 70 as shown in the figure.
3, a shift register 704, a selector 705, and an output gate 706.

The read address from the CPU 1 or the drawing coprocessor 13 is directly input to the first input A of the subtractor 702, and the subtractor 70 is also passed through the register 701.
2 is input to the second input B. The register 701 holds the read address for one cycle. Therefore, the read address input to the first input A of the subtractor 702 is the current read address, and the read address input to the second input B is the read address one cycle before.

The subtractor 702 subtracts the value of the previous read address input to the second input B from the value of the current read address input to the first input A. The subtraction result (offset ofs) is supplied to one input of the comparator 703. The other input of the comparator 703 is supplied with the constant (α or β) selected by the selector 705.

The comparator 703 compares the constant and the offset ofs, and the comparison result signal cmp indicating the magnitude relationship between them.
Is output. The comparison result signal cmp is supplied to the shift register 704 and the output gate 706. The shift register 704 sequentially shifts the comparison result signal cmp output from the comparator 703 and holds the comparison result for n times.

The output gate circuit 706 generates a judgment result signal according to the comparison result held in the shift register 704 and the current comparison result output from the comparator 703. The access mode determination circuit 14 configured as described above
In 4, the change state of the read address is determined by the comparison result signal cmp. In this case, the change state of the read address represented by the comparison result signal cmp is
It is classified into three states of rnd, inc, and dec. r
nd indicates that the interval between consecutive read address values is large. This rnd is satisfied under the following conditions. α <ofs ... Cmp = rnd ofs <−α ... Cmp = rnd inc indicates that the read address value continuously changes in the address increasing direction. inc is satisfied under the following conditions. 0 ≦ ofs ≦ α ... cmp = inc dec indicates that the read address value continuously changes in the address decreasing direction. dec is satisfied under the following conditions. −α ≦ ofs <0 cmp = dec The access mode determination process using the comparison result signal cmp having such three states of rnd, inc, and dec is performed as follows.

That is, when the comparison result signal cmp is inc twice consecutively, the output gate 706 determines that the access is continuous access in the address increasing direction, and causes the frame buffer control circuit 143 to execute prefetch processing. In this case, the data to be prefetched is the data of addresses that are continuous in the address increasing direction with respect to the data requested by the read address. Also, the comparison result signal c
When mp is dec twice consecutively, the output gate 706
Is determined to be continuous access in the address decreasing direction,
The frame buffer control circuit 143 is caused to execute prefetch processing. In this case, the prefetched data is
This is data of addresses consecutive in the address decreasing direction with respect to the data requested by the read address. Further, when inc and dec are consecutively repeated n times or more, the output gate 706 determines that a plurality of data may be prefetched collectively, and switches the VRAM access mode of the frame buffer control circuit 143 to the page mode. Here, the page mode is a high-speed memory access mode in which the row address is fixed and only the column address is sequentially incremented.

If the comparison result signal cmp is rnd twice in succession, the output gate 706 determines that it is a random access, and the frame buffer control circuit 143.
Prohibits the prefetch processing of.

In this way, the access mode determination circuit 144
In the CP, according to the history of the comparison result signal cmp,
It is determined whether the access mode by the U1 or the drawing coprocessor 13 is the random access mode, the address decrease continuous access mode, or the address increase continuous access mode. FIG. 4 shows the state transition of these determination results.

In FIG. 4, the state 1 is a state in which the read access mode by the CPU 1 or the drawing coprocessor 13 is determined to be random access, and the VRAM access mode is set to the single mode. The mode determination process is started from this state 1. In this state 1, when the state of the comparison result signal cmp becomes dec twice in succession, the state 1 transits to the state 2.

State 2 is a state in which the read access mode by the CPU 1 or the drawing coprocessor 13 is determined to be continuous access in the address decreasing direction.
In this state 2, the two most recent comparison result signals (cmp {0}, {1}) are (dec, dec), (d
ec, rnd), and (rnd, dec), the state of state 2 is maintained, and otherwise, state 1
Return to the random state. Thus, even if rnd occurs once, it is not determined to be random access. This is because in the case of continuously accessing a two-dimensional rectangular area, the address interval temporarily increases when straddling a line. Also, in state 2,
When dec continues n times, the VRAM access mode is switched to the page mode. On the other hand, in the state 1, the state of the comparison result signal cmp is in continuous twice.
When it becomes c, the state 1 transits to the state 3.

State 3 is a state in which the read access mode by the CPU 1 or the drawing coprocessor 13 is determined to be continuous access in the address increasing direction.
In this state 3, the two most recent comparison result signals (cmp {0}, {1}) are (inc, inc), (i
nc, rnd) and (rnd, inc), the state of the state 3 is maintained, otherwise, the state 1
Return to the random state. As described above, the reason why the random access is not determined even if the rnd occurs once is in consideration of the access to the two-dimensional rectangular area. Further, in state 3, when inc continues n times, the VRAM access mode is switched to the page mode.

In FIG. 5, the access mode determination circuit 144 is shown.
Shows the relationship between each access mode determination state (state 1 to state 3), prefetch processing, and VRAM access mode.

In the state 1, the access of the CPU 1 or the drawing coprocessor 13 is a random access, so the prefetch process is not executed. The access mode (VRAM access mode) of the dual port image memory 30 is the CPU 1 or the drawing coprocessor 13.
The dual port image memory 30 is set to the single mode in which it is accessed once for each read address supplied from. In this case, when a cache miss occurs, the data designated by the read address is read from the dual port image memory 30.

In the state 2, since the access of the CPU 1 or the drawing coprocessor 13 is continuous access by executing a string move instruction or the like, the prefetch process is executed. In this case, the VRAM access mode is initially set to the single mode and the next data is prefetched in consideration of the reduction of the read address. In this state, if dec is generated n times in succession, then the page mode is switched to.

Even in the state 3, since the access of the CPU 1 or the drawing coprocessor 13 is continuous access by executing a string move instruction or the like, the prefetch process is executed. In this case, the VRAM access mode is initially set to the single mode, and the next data is prefetched in consideration of the increase of the read address.
In this state, if inc is generated n times consecutively, the mode is switched to the page mode.

As described above, in the memory control circuit 14 of FIG.
It is possible to predict / determine the access mode of the U1 or the drawing coprocessor 13 and control the prefetch process and the VRAM access mode according to the determination result.
Therefore, the prefetch process and the page mode access can be used only in the case of continuous access, and the efficiency of data reading from the dual port image memory 30 can be improved. Next, the image data read operation by the memory control circuit 14 of FIG. 2 when the CPU 1 executes the string move instruction will be described.

First, the cache memory block 141
No image data is stored in a. In this state,
For example, from the CPU 1 to the dual port image memory (VRA
When a read request for M) 30 is issued, the read request is sent to the cache interface 14 of the memory control circuit 14 via the system interface 12 of FIG.
Sent to 2. The cache interface 142 is
The read address from the CPU 1 is supplied to the frame buffer cache 141, the frame buffer control circuit 143 and the access mode determination circuit 144, and the frame buffer cache 141 is set to the read mode by the read / write signal (R / W).

In this case, the image data designated by the read address is stored in the cache memory block 141.
Does not exist in a (cache miss). Therefore, the frame buffer control circuit 143 performs read access to the dual port image memory 30 in the single mode in response to the mishit signal, and reads the image data designated by the read address. This image data is transferred to the CPU 1 via the direct path P1, the cache interface 142 and the system interface 12 of FIG. 1, and at the same time, the cache memory block 141a.
Stored in. Thus, in the first stage of read access, the read request from the CPU 1 arrives, the mishit is determined, and the read access of the dual port image memory 30 is started. Therefore, the CPU 1 waits until the read data is confirmed. But,
When such read access is repeated several times, the access mode determination circuit 144 determines that the access of the CPU 1 is continuous access.

In response to this determination, the frame buffer control circuit 143 reads the data of the address subsequent to the data designated by the latest read address from the dual port image memory 30, and stores it in the cache memory block 141a. .

Therefore, a cache hit occurs from the next read access from the CPU 1. In this case, the image data is immediately read from the frame buffer cache 141, so that the CPU 1 is not required to wait.

Further, if continuous access continues, this time,
The frame buffer control circuit 143 performs read access to the dual port image memory 30 in page mode, and stores a plurality of data subsequent to the data specified by the latest read address in the cache memory block 141a. In this state, the cache memory block 14
Since the hit state continuously occurs by the number of data stored in 1a, the average read time of the image data from when the CPU 1 issues the access request to when the read data is determined is further shortened. FIG. 6 shows an example of a specific configuration of the frame buffer cache 141.

The cache memory block 141a is C
It is divided into two cache memory blocks 201 and 202 so that the cache access by the PU 1 or the coprocessor 13 and the cache access by the frame buffer control circuit 143 are simultaneously executed. These cache memory blocks 201 and 202 are configured to be able to read / write data independently.

The cache memory block 201 is alternatively connected to the cache interface 142 and the frame buffer control circuit 143 via the multiplexer 301. Similarly, the cache memory block 20
2 also via the multiplexer 302, the cache interface 142 and the frame buffer control circuit 14.
3 is alternatively connected.

The multiplexers 301 and 302 connect the cache memory blocks 201 and 202 to the cache interface 142 and the frame buffer control circuit 14.
3 for switching connection alternately, and their selection operation is complementarily controlled by the selection signals SEL and SEL. Therefore, one of the cache memory blocks 201 and 202 is the cache interface 1
When connected to 42, the other will be connected to the frame buffer control circuit 143. Next, FIG.
6, the frame buffer cache 141 of FIG.
A data read operation using the will be described.

Here, the cache interface 1
It is assumed that the cache memory block 201 is connected to 42 and the cache memory block 202 is connected to the frame buffer control circuit 143. In this case, the cache memory block 201 is a foreground cache (FORE) accessed by the CPU 1 or the drawing coprocessor 13, and the cache memory block 202 is a background cache (BA) accessed by the frame buffer control circuit 143.
CK).

When the CPU 1 or the drawing coprocessor 13 reads the image data, the read address from the CPU 1 or the drawing coprocessor 13 is sent to the cache memory block 201 which is a foreground cache, and the cache memory block 201 is read-accessed. It

When the access mode determination circuit 144 has determined that the access is continuous, the prefetch circuit 143a of the cache memory block 201, which is the background cache, is used by the prefetch circuit 143a in parallel with the read access of the cache memory block 201. The image data in the dual port image memory (VRAM) 30 is prefetched. The prefetched image data is a block of image data that follows the image data stored in the cache memory block 201.
At this time, if the VRAM access mode is set to the page mode, in the prefetch operation, the dual port image memory (VRAM) 30 is read-accessed in the page mode, and a plurality of image data consecutive in the order of addresses are consecutive. It is read at high speed.

If a cache miss occurs in the read access of the cache memory block 201,
The foreground cache and the background cache are exchanged by the multiplexers 301 and 302. As a result, the cache memory block 202
Becomes the foreground cache, and the cache memory block 201 becomes the background cache.

In the case of continuous address read access, since the subsequent image data has already been prefetched in the cache memory block 202, the CPU 1 or the drawing processor 13 can sequentially read the image data without waiting time. FIG. 8 shows the cache memory block 2 during such a cache read.
The state transition of 01 and 202 is shown.

In FIG. 8, state 0 is the initial state, and valid data is not stored in either the foreground cache or the background cache. In this state, when a read request for image data is issued from the CPU 1 or the drawing coprocessor 13, the state transits from state 0 to state 1.

In the state 1, the frame buffer control circuit 143 reads access the dual port image memory 30 in the page mode to read the image data and writes it in the background cache. As a result, the background cache stores an image data block having the read-requested image data as its head. When the data reading from the dual port image memory 30 is completed, the foreground / background are exchanged, and the state 1 transits to the state 2.

In state 2, valid data exists in the foreground cache. The CPU 1 or the drawing coprocessor 13 makes a read access to the foreground cache.

If a cache miss occurs in this read access, the state transits to the above-mentioned state 1.
In this transition, the foreground / background switching is not performed.

When a cache hit occurs in the state of state 2, the state of state 2 is maintained.
In this case, when performing the prefetch operation by the prefetch control circuit 143a, the state transits to the state 3.

In the state 3, the CPU 1 or the drawing coprocessor 13 performs the read access to the foreground cache, and in the continuous access mode, the prefetch control circuit 143a performs the background access in parallel with the read access to the foreground cache. The image data is prefetched to the cache.

In this state 3, when a cache miss occurs in the read access of the foreground cache, the foreground cache and the background cache are exchanged and the state transits to the state 2. On the other hand, when there is a cache hit in state 3, the state of state 3 is maintained. Next, with reference to FIG. 9, a write operation of image data using the frame buffer cache 141 of FIG. 6 will be described.

Here, the cache interface 1
It is assumed that the cache memory block 201 is connected to 42 and the cache memory block 202 is connected to the frame buffer control circuit 143. In this case, the cache memory block 201 is a foreground cache (FORE) that is write-accessed by the CPU 1 or the drawing coprocessor 13, and the cache memory block 202 is the frame buffer control circuit 1.
The background cache (BACK) is read-accessed by 43.

When the CPU 1 or the drawing coprocessor 13 writes image data, the write address and the write data from the CPU 1 or the drawing coprocessor 13 are sent to the cache memory block 201 which is a foreground cache, and the cache memory block 201 Write access is performed. In parallel with the write access to the cache memory block 201, the cache memory block 202, which is a background cache, is read-accessed for updating the dual port image memory (VRAM) 30, and the contents of the cache memory block 202 are dual. Port image memory (VRAM)
30 is written (cache flush).

In this state, the cache memory block 2
When the data is written in all the entries of 01 (cache full), the multiplexers 301 and 302 exchange the foreground cache and the background cache. As a result, the cache memory block 202 becomes a foreground cache, and the cache memory block 201 becomes a background cache.

The foreground cache and the background cache are exchanged not only when the cache is full, but also when the write address value exceeds the writable address range in page mode (Cash miss).
Is also run. This is because the cache flush is executed by performing write access to the dual port image memory (VRAM) 30 in the page mode.

Dual port image memory (VRAM) 3
In order to write-access 0 in page mode, it is necessary that all the image data written in the cache memory block have the same row address. Therefore, if the image data to be written has a different row address from the already written image data, the foreground cache and background cache are swapped to write the image data to another cache memory block. Be seen.

When the foreground / background are switched, this time, the cache memory block 2
02 is a foreground cache, and the cache memory block 201 is a background cache. Therefore, thereafter, the CPU 1 or the drawing coprocessor 13
Performs write access to the cache memory block 202, and the frame buffer control circuit 143 performs read access to the cache memory block 201 to perform cache flush.

As described above, in the configuration of the frame buffer cache 141 shown in FIG. 6, two cache memory blocks 201 and 20 which can be independently access-controlled.
2 is provided, the CPU 1 or the drawing coprocessor 13 and the frame buffer control circuit 143 can asynchronously access the caches without being aware of the operation timing of each other.

Furthermore, since the cache read by the CPU 1 or the drawing coprocessor 13 and the prefetch processing by the frame buffer control circuit 143 can be simultaneously executed,
The data read speed can be further increased.
Next, a second configuration example of the frame buffer cache 141 will be described with reference to FIG.

The structure of the frame buffer cache 141 is intended to speed up the drawing process such as line drawing in which read access and write access to the dual port image memory 30 are mixed. A write cache and a read cache are provided separately so that the cache write does not destroy the data in the read cache.

That is, the cache memory block 14
1a is divided into four cache memory blocks 401 to 404 that can independently read / write data.

Of these cache memory blocks,
The cache memory blocks 401 and 402 are used as a write cache (W), and the cache memory blocks 403 and 404 are used as a read cache (R).

The write cache (W) is a write-only cache for storing write data from the CPU 1 or the drawing coprocessor 13, and is used for speeding up the image data writing operation by the CPU 1 or the drawing coprocessor 13. To be done.

The read cache (R) is a read-only cache for storing the image data read from the dual port image memory 30, and is for speeding up the image data read operation by the CPU 1 or the drawing coprocessor 13. Used for.

Write cache memory block 401
Through the multiplexer 501, the cache interface 142 and the frame buffer control circuit 143.
Is connected alternatively. Similarly, the write cache memory block 402 is also selectively connected to the cache interface 142 and the frame buffer control circuit 143 via the multiplexer 502.

In this case, the multiplexers 501 and 502
Selection operation is performed complementarily by the selection signals SEL1 and SEL2, and the write cache memory block 401,
The foreground cache 402 and the background cache 402 are alternately switched.

Read cache memory block 403,
404 also corresponds to the corresponding multiplexers 503, 5
04, the cache interface 142 and the frame buffer control circuit 143 are alternatively connected.

The selection operations of the multiplexers 503 and 504 are complementarily performed by the selection signals SEL3 and SEL4, and the read cache memory blocks 403 and 404 are also alternately switched to the foreground cache and the background cache. Next, the access operation of the frame buffer cache 141 of FIG. 10 will be described with reference to FIG.

Here, the cache interface 1
It is assumed that the write cache memory block 401 and the read cache memory block 403 are connected to 42, and the write cache memory block 402 and the read cache memory block 404 are connected to the frame buffer control circuit 143. In this case, the cache memory block 401 is the foreground write cache (WF), the cache memory block 402 is the background write cache (WB), and the cache memory block 403 is the foreground read cache (R).
F), the cache memory block 404 becomes a background read cache (RB).

When the CPU 1 or the drawing coprocessor 13 reads image data, the read address from the CPU 1 or the drawing coprocessor 13 is the cache memory block 403 which is a foreground read cache.
And the cache memory block 403 is read-accessed. This cache memory block 40
In parallel with the read access of No. 3, in the continuous access mode, the prefetch circuit 14 is provided in the cache memory block 404 which is the background read cache.
Dual port image memory (VRAM) 3a
Image data of 0 is prefetched. The prefetched image data is a block of image data that follows the image data stored in the cache memory block 403.

In this prefetch operation, for example, the dual port image memory (VRAM) 30 is read-accessed in the page mode, and a plurality of image data consecutive in the address order are continuously read at high speed.

The image data read from the foreground read cache 403 is calculated by the CPU 1 or the drawing processor 13. Then, the operation result data is sent as write data to the cache memory block 401 which is a foreground write cache, and the cache memory block 401 is write-accessed.

Such read access to the foreground read cache (RF) and write access to the foreground write cache (WF) are repeatedly executed. In this state, when data is written in all the entries of the cache memory block 401 (cache full) or when the value of the write address exceeds the writable address range in page mode (cash miss), the multiplexer 501. , 502 replace the foreground write cache (WF) with the background write cache (WB). As a result, the cache memory block 402 becomes a foreground write cache, and the cache memory block 401 becomes a background write cache.

When the foreground / background switching is performed, the CPU 1 or the drawing coprocessor 13 makes a write access to the cache memory block 402, and the frame buffer control circuit 143 makes a read access to the cache memory block 401 to make a cache access. Do a flash.

When a cache miss occurs in the read access of the cache memory block 403, the foreground read cache (RF) and the background read cache (RB) are exchanged by the multiplexers 503 and 504. As a result, the cache memory block 404 becomes the foreground read cache, and the cache memory block 403 becomes the background read cache.

Since the succeeding image data has already been prefetched in the cache memory block 404, the CPU 1 or the drawing processor 13 can sequentially read the image data without waiting time in the case of read access of continuous addresses.

As described above, in the configuration of the frame buffer cache 141 of FIG. 10, since the write cache and the read cache are separately provided, the data read from the dual port image memory 30 to the cache is not destroyed by the cache write. , CPU
It is possible to efficiently execute read / write mixed drawing processing by the 1 or drawing processor 13.

The cache memory blocks 401 to 4
Since 04 is configured to be readable / writable, these four cache memory blocks 401 to 4
All 04 can also be used as a write cache. This is the BI supported by the drawing coprocessor 13.
This is a cache mode (high-speed rectangular transfer mode) suitable for high-speed execution of rectangular transfer such as TBLT.

That is, since the drawing coprocessor 13 is provided with the read buffer, all the four cache memory blocks 401 to 404 can be used as the write cache. Since BitBlt has a high possibility that addresses are continuous, page mode write can be used by increasing the capacity of the write cache, and writing to the image memory 30 can be performed efficiently. Next, the cache access operation in the high speed rectangular transfer mode will be described with reference to FIG.

Here, the cache interface 1
42 is a write cache memory block 401, 402
Is connected, and the write cache memory blocks 403 and 404 are connected to the frame buffer control circuit 143. In this case, both cache memory blocks 401 and 402 are foreground write caches (WF), and both cache memory blocks 403 and 404 are background write caches (WB).

When the drawing coprocessor 13 reads the image data, the read address from the drawing coprocessor 13 does not pass through the frame buffer cache 141 but through the direct path P1.
Sent to 3. The frame buffer control circuit 143 performs read access to the dual port image memory 30 to read image data, and transfers the image data to the drawing coprocessor 13 via the direct path P1. The transferred image data is written in the read buffer 131a incorporated in the arithmetic circuit 131 of the drawing coprocessor 13.

Next, the drawing coprocessor 13 processes the image data in the read buffer 131a and then sends it as write data to the cache memory block 401 or 402 which is a foreground write cache. If there is a free space in the cache memory block 401, the cache memory block 401 is write-accessed, and if there is no free space, the cache memory block 402 is write-accessed. Cache memory block 40
When data is written in all entries 1 and 402 (cache full) or when the value of the write address exceeds the writable address range in page mode (Cash miss), the multiplexer 501,
The foreground write cache (WF) and the background write cache (WB) are replaced by 502, 503, and 504. As a result, the cache memory blocks 403 and 404 become the foreground write cache, and the cache memory block 40
1, 402 are background write caches.

When the foreground / background are exchanged, the drawing coprocessor 13 performs write access to the cache memory blocks 403 and 404 this time. On the other hand, the frame buffer control circuit 143
Performs read access to the cache memory blocks 401 and 402 to perform cache flush. In this cache flash, dual port image memory 3
0 is write-accessed in page mode.

As described above, in the configuration of FIG.
Two types of cache modes can be used: a cache mode in which a write cache and a read cache are separately provided (mixed access mode), and a cache mode in which all cache memory blocks are used as a write cache (high speed rectangular transfer mode). FIG. 13 shows usage patterns of cache blocks in these two types of cache modes.

Here, it is assumed that each cache memory block can store 8 entries of 32-bit data. In this case, in the mixed access mode, the maximum data width that can be read / written by one cache access is 32 bits, but in the high-speed rectangular transfer mode, two cache memory blocks are simultaneously accessed by one access. Up to 64 for cache access
It is possible to read / write bit data.

Therefore, the frame buffer control circuit 1
If the bus width between the parallel port 43 and the parallel port of the dual port image memory 30 is set to 64 bits, the cache flush speed in the high speed rectangular transfer mode can be further increased. FIG. 14 shows an example of the configuration of the cache memory block provided in the frame buffer cache 141.

Since the cache memory blocks provided in the frame buffer cache 141 have the same structure, the cache memory block 4 shown in FIG. 10 is used here.
01 will be described as a representative.

The cache memory block 401 has a circuit configuration suitable for page mode access of the dual port image memory 30. That is, the cache memory block 401 includes a data memory 601, a tag memory 602, a valid flag register 603, a multiplexer 604, a multiplexer control circuit 605, a fixed tag register 606, and a fixed tag comparator 607 as illustrated.

The data memory 601 holds the image data (C DAT) supplied as write data to the cache memory block 401, and has eight entries each having a 32-bit width. Tag memory 60
2 is for holding tag information indicating which address of the dual port image memory 30 the image data of the data memory 601 corresponds to, and has the same eight tag entries as the data memory 601. is doing. Each tag entry stores tag information of the image data held in the corresponding entry of the data memory 601. As the tag information, a 9-bit CAS address (column address) of the dual port image memory 30
Is used. This CAS address is used by the CPU when the cache memory block 401 is read-accessed.
1, a part of the write address output from the drawing coprocessor 13 or the frame buffer control circuit 143. The valid flag register 603 is included in the data memory 6
A valid flag (VF) indicating whether the data of each entry 01 is valid is held. Multiplexer 604
Selects the hit tag information and data from the respective entries of the data memory 601 and the tag memory 602. Since the tag information is the CAS address, the dual port image memory 30 can be accessed in the page mode using the read tag information in the case of the cache flash.

The multiplexer control circuit 605 is for controlling the selection operation of the multiplexer 604,
Eight tag comparators 605a and gate circuit 605b
Is equipped with. The eight tag comparators 605a are lead C
It is for detecting in which entry of the data memory 601 the data designated by the AS address exists, and compares the tag information of each of the eight entries of the tag memory 602 with the read CAS address, An 8-bit comparison result signal is output. The read CAS address is a part of the read address output from the CPU 1, the drawing coprocessor 13, or the frame buffer control circuit 143 when the cache memory block 401 is read accessed.

The gate circuit 605b is a tag comparator 605.
8-bit comparison result signal of a, valid flag (VF0
~ VF7) and the comparison result signal of the fixed tag comparator 607, a cache hit / cache miss at the time of read access is detected. That is, the gate circuit 6
In 05b, first, the data memory 601 in which the data specified by the read CAS address exists
The entry in is checked to see if it is valid. If it is not valid, a cache miss occurs and a mishit signal is output. On the other hand, if valid, the fixed tag comparator 60
The cache hit / cache miss is determined by the comparison result signal of 7. When the comparison result signal of the fixed tag comparator 607 indicates a match, the gate circuit 605b indicates a read H indicating that a cache hit has occurred in a read access.
Output IT signal. At this time, the selection signals C0 to C0
The multiplexer 604 is controlled so that the selection signal corresponding to the entry designated by the read CAS address in C7 is enabled and the tag information and data in the entry designated by the read CAS address are read.

In the fixed tag register 606, the write RAS address output from the CPU 1, the drawing coprocessor 13, or the frame buffer control circuit 143 at the first write access is set. Fixed tag comparator 60
Reference numeral 7 denotes the write RAS address of the fixed tag register 606 and the CPU 1, the drawing coprocessor 13, or the frame buffer control circuit 14 at the time of write or read access.
The RAS address output from 3 is compared. In the case of write access, write R of fixed tag register 606
The cache hit / cache miss is determined only by the match / mismatch between the AS address and the RAS address included in the write address. In the case of read access, a signal indicating match / mismatch between the write RAS address of the fixed tag register 606 and the RAS address included in the read address is sent to the gate circuit 605b.

The write RAS address set in the fixed tag register 606 is used for write access to the dual port image memory 30 in the page mode during cache flush.

As described above, in the cache memory block 401, only the data of the same RAS address can be written by using the write RAS address as the fixed tag. Further, since the CAS address is stored as tag information in the tag entry, the tag information can be effectively used for page mode access of the dual port image memory 30.

As described above, in this display control system, in the image data read processing by the CPU 1 or the drawing coprocessor 13, the probability of a cache hit can be increased by prefetching the image data in the frame buffer cache 141. it can. When a cache miss occurs, the CPU 1 or the drawing coprocessor 13 has to wait until the image data is read from the dual port image memory 30,
In the case of a cache hit, desired image data can be immediately read from the frame buffer cache 141. Therefore, the frame buffer cache 1
Prefetching the image data to 41 can reduce the waiting time of the CPU 1 or the drawing coprocessor 13.

In the above description, the case where the image data is prefetched has been described, but it is a matter of course that a read buffer for prefetching may be provided and the image data may be prefetched there.

Even if such a prefetch buffer is not provided at all, in the case of continuous access, V
Since the RAM access mode is switched to the page mode, the data can be transferred to the C
It can be transferred to the PU 1 or the drawing coprocessor 13. Furthermore, as the VRAM high-speed access mode,
Not only the page mode but also a static column mode, a nibble mode or the like can be used.

[0133]

As described above, according to the present invention, the CPU
It is now possible to control access to the frame buffer according to the type of instructions executed by the drawing coprocessor, and it is possible to read out image data that makes effective use of the high-speed access mode of the frame buffer and prefetching of image data. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a display control system according to an embodiment of the present invention.

2 is a block diagram showing a configuration example of a memory control circuit provided in the display control system of FIG.

3 is a circuit diagram showing an example of a specific configuration of an access mode determination circuit provided in the memory control circuit of FIG.

FIG. 4 is a diagram for explaining a mode determination operation by the access mode determination circuit shown in FIG.

5 is a prefetch process and VRA corresponding to a mode determination result by the access mode determination circuit shown in FIG.
The figure explaining M access mode.

6 is a block diagram showing a first configuration example of a frame buffer cache provided in the memory control circuit of FIG.

FIG. 7 is a diagram for explaining an image data read operation using the frame buffer cache of FIG. 6;

FIG. 8 is a diagram for explaining a foreground / background switching operation of the frame buffer cache of FIG.

9 is a diagram for explaining an image data writing operation using the frame buffer cache of FIG. 6;

10 is a block diagram showing a second configuration example of a frame buffer cache provided in the memory control circuit of FIG.

11 is a diagram for explaining an image data write / read operation using the frame buffer cache of FIG.

12 is a diagram for explaining an image data writing operation in a high speed rectangular transfer mode using the frame buffer cache of FIG.

13 is a diagram for explaining the foreground / background switching of the frame buffer cache of FIG.

14 is a circuit diagram showing an example of a specific configuration of a cache memory block provided in each frame buffer cache shown in FIGS. 2, 6 and 10. FIG.

[Explanation of symbols]

1 ... CPU, 2 ... Main memory, 3 ... System bus, 4
... display control system, 10 ... display controller, 13 ... drawing coprocessor, 14 ... memory control circuit,
16 ... CRT controller, 30 ... Dual port image memory, 141 ... Frame buffer cache, 141
a ... cache memory block, 141b ... control circuit,
142 ... Cache interface, 143 ... Frame buffer control circuit, 144 ... Access mode determination circuit, 201, 202, 401-404 ... Cache memory block, 301, 302, 501-504 ... Multiplexer, 601 ... Data memory, 602 ... Tag memory , 603 ... Valid flag register.

Claims (3)

[Claims] 1. An image memory for storing image data generated by a processor, display means for displaying the image data stored in the image memory on a display, and a change of a read address supplied from the processor. Access mode determining means for determining whether the read access by the processor is random access with discontinuous addresses or continuous access for sequentially reading continuous data in the order of address according to the history; A display control system comprising: a memory control unit that performs read access to the image memory in one of a first access mode and a second access mode that is faster than the first access mode according to a determination result. 2. An image memory for storing image data generated by a processor, display means for displaying the image data stored in the image memory on a display, and image data preread from the image memory. Then
A prefetch buffer configured to read the image data in response to a read request from the processor, and a read access by the processor according to a history of changes in the read address supplied from the processor, Access mode determining means for determining whether or not a continuous access mode for sequentially reading continuous data in address order; and when the access mode determining means determines that the continuous access mode is set, a read request is issued by the processor And a prefetch unit that reads out image data of an address subsequent to the image data from the image memory and prefetches into the prefetch buffer. 3. The prefetch means performs read access to the image memory in a page mode to continuously transfer a plurality of image data consecutive in address order from the image memory to the prefetch buffer. 2. The display control system described in 2.